Tandy 102, 26-3803 Service Manual

TANDY®

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CUSTOM MANUFACTURED FOR RADIO SHACK, A DIVISION OF TANDY CORPORATION

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CONTENTS

PART I. INTRODUCTION ........................................................................................ 1-1

System Overview ............................................................................................. 1-2

External View .................................................................................................... 1-2

Internal View ..................................................................................................... 1-5

Specifications ................................................................................................... 1-7

PART 11. DISASSEMBLY INSTRUCTIONS ............................................................. 2-1

Cases ................................................................................................................. 2-1

Keyboard and LCD PCBs ................................................................................. 2-1

Main PCB ........................................................................................................... 2-2

PART III. MAINTENANCE ....................................................................................... 3-1

To clean the body and LCD display ................................................................ 3-1

PART IV. THEORY OF OPERATION ....................................................................... 4-1

General .............................................................................................................. 4-1

Block Diagram .................................................................................................. 4-2

CPU .................................................................................................................... 4-3

Memory ............................................................................................................. 4-3

I/O Map ............................................................................................................. 4-5

Keyboard .......................................................................................................... 4-6

Cassette Interface Circuit ............................................................................... 4-7

Printer Interface Circuit ................................................................................... 4-8

Bar Code Reader Interface Circuit ................................................................. 4-9

Buzzer Control Circuit ...................................................................................... 4-10

System Bus ....................................................................................................... 4-11

Clock Control Circuit ....................................................................................... 4-12

Serial Interface Circuit ..................................................................................... 4-14

LCD .................................................................................................................... 4-21

Power Supply Circuit ....................................................................................... 4-24

PART V. TROUBLESHOOTING .............................................................................. 5-1

General Guidance ............................................................................................ 5-1

Troubleshooting Guide .................................................................................... 5-1

Check List ......................................................................................................... 5-11

PART VI. EXPLODED VIEW/PARTS LIST ............................................................. 6-1

Electrical Parts List .......................................................................................... 6-2

Mechanical and Assembly Parts List ............................................................. 6-11

PART VII. SCHEMATIC DIAGRAMS/ PCB VIEWS ................................................ 7-1

Schematic Diagrams ........................................................................................ 7-1

PCB Views ......................................................................................................... 7-3

APPENDIX A/ INSTALLATION ............................................................................ A-1

Installation of Optional RAM and ROM .......................................................... A-1

APPENDIX B/ KEYBOARD LAYOUT, CONNECTOR PIN

ASSIGNMENTS AND CHARACTER CODE TABLE ....................... B-1

B-1. Keyboard Layout ..................................................................................... B-1

B-2. Connector Pin Assignments ................................................................... B-2

B-3. Character Code Table ............................................................................. B-7

APPENDIX C/ TECHNICAL INFORMATION .......................................................... C-1

C-1. 80C85A .................................................................................................... C-1

C-2. 81 C55 ....................................................................................................... C-7

C-3. 6402 ......................................................................................................... C-13

C-4. Basic Construction of LCD ..................................................................... C-19

io

List of Illustrations

FIGURE

DESCRIPTION

PAGE

NUMBER NUMBER

1-1

Front View ................................................................................................................................

1-2

1-2

Rear View ................................................................................................................................

1-3

1-3

Bottom View ............................................................................................................................

1-4

1-4

Main PCB (Bottom View) .......................................................................................................

1-5

1-5

LCD PCB .................................................................................................................................

1-6

2-1

Top Case Removal .................................................................................................................

2-1

2-2 Keyboard and LCP PCBs Removal .......................................................................................

2-1

2-3 Main PCB Removal .................................................................................................................

2-4

4-1

Organization of Section IV .....................................................................................................

4-1

4-2

System Block Diagram ...........................................................................................................

4-2

4-3 Functional Block Diagram of Bus Separation Circuit ...........................................................

4-3

4-4 Memory Map ...........................................................................................................................

4-3

4-5

Address Decoding and Bank Selection Circuit ....................................................................

4-4

4-6 I/O Address Decoding Circuit ................................................................................................

4-5

4-7

Condition of Pressing

"T"

Key ...............................................................................................

4-6

4-8

Cassette Interface Circuit .......................................................................................................

4-7

4-9 Printer Interface Circuit ..........................................................................................................

4-8

4-10 Bar Code Reader Interface Circuit ........................................................................................

4-9

4-11 Buzzer Control Circuit ............................................................................................................

4-10

4-12

Time Set Sequence ofuPD1990AC .......................................................................................

4-12

4-13

Time Read Sequence ofuPD1990AC ...................................................................................

4-13

4-14

Functional Block Diagram of the Serial Interface .................................................................

4-14

4-15

RS-232C/MODEM Selection Circuit ......................................................................................

4-15

4-16

RS-232C Interface Circuit ......................................................................................................

4-16

4-17 MODEM IC and Peripheral Circuit .........................................................................................

4-17

4-18 Transmission Filter Circuit .....................................................................................................

4-17

4-19

Reception Filter Circuit ...........................................................................................................

4-18

4-20 MODEM Adjustment ...............................................................................................................

4-19

4-21 MODEM Connector Interface Circuit ....................................................................................

4-20

4-22

HD44103 Internal Logic Diagram ..........................................................................................

4-21

4-23

HD44102 Internal Logic Diagram ..........................................................................................

4-22

4-24 LCD Waveform ........................................................................................................................

4-23

4-25 Power Supply and Reset Circuit ............................................................................................

4-25

6-1

Exploded View ........................................................................................................................

6-1

7-1

Main PCB - Schematic Diagram ............................................................................................

7-1

7-2

LCD PCB - Schematic Diagram ............................................................................................

7-2

7-3

Main PCB - Top View .............................................................................................................

7-3

7-4

Main PCB - Bottom View ........................................................................................................

7-4

7-5 LCD PCB - Top View ..............................................................................................................

7-5

A-1 Installation of RAM and ROM ................................................................................................. A-1

B-1 Keyboard Layout .................................................................................................................... B-1

B-2 System Bus Connector ........................................................................................................... B-2

B-3 RS-232C Connector ............................................................................................................... B-3

B-4 Printer Connector ................................................................................................................... B-4

B-5 Cassette Connector ................................................................................................................ B-5

B-6 MODEM Connector ................................................................................................................ B-5

B-7 Bar Code Reader Connector ................................................................................................. B-6

C-1 Functional Block Diagram ...................................................................................................... C-1

C-2 Pin Configuration of 80C85A ................................................................................................. C-1

C-3 Trap and RESET IN ................................................................................................................. C-5

C-4 80C85A Basic System Timing ............................................................................................... C-7

C-5 Functional Block Diagram ..................................................................................................... C-7

iii

FIGURE

DESCRIPTION

NUMBER NUMPAGEBER

..................................

C-6 Pin Configuration of 81 C55 .................................................................. C-7

C-7 Internal Register of 81 C55 ..................................................................................................... C-9

C-8 Programming the Command/Status Register ...................................................................... C-10

C-9 Reading the C/S Register ....................................................................................................... C-11

C-10 Bit Assignments to the Timer Counter .................................................................................. C-11

C-11 Functional Block Diagram ...................................................................................................... C-13

C-12 Pin Configuration of 6402 ....................................................................................................... C-13

C-,13 Receiver Timing ..................................................................................................................... C-16

C-14 Transmitter Operation ............................................................................................................ C-17

C-15 Start Bit Detection Timing ...................................................................................................... C-18

C-16 Construction of LCD Panel .................................................................................................... C-19

C-17 Operation Theory of LCD Panel ............................................................................................. C-20

List of Tables

TABLE

NUMBER

DESCRIPTION

NUMPAGEBER

4-1 I/O MAP ................................................................................................................................... 4-5

4-2 Port Address of PIO ................................................................................................................ 4-5

4-3 System Bus Pin Assignments ................................................................................................ 4-11

B-1 System Bus Connector Pin Assignments ............................................................................. B-2

B-2 RS-233C Connector Pin Assignments .................................................................................. B-3

B-3 Printer Connector Pin Assignments ...................................................................................... B-4

C-1 Interrupt Priority, Restart Address and Sensitivity ............................................................... C-4

C-2 80C85A Machine Cycle Chart ............................................................................................... C-6

C-3 80C85A Machine State Chart ................................................................................................ C-6

C-4 I/O Address of 81 C55 ............................................................................................................. C-9

C-5 Port Control Assignment ........................................................................................................ C-10

C-6 Control Word Format .............................................................................................................. C-15

iv

I. INTRODUCTION

This manual is prepared for the Tandy 102 technicians working in field or in repair centers. Users of
this manual should be acquainted with the 80C85A microprocessor, the 81 C55 PIO and the 6402

UART. If you need more detailed information, refer to Appendix C in this manual.

This manual consists of seven sections and three appendices:

Section I

This section provides general information on the Tandy 102 such as specifications, external

views and internal views.

Section II

This section describes the disassembly procedures.

Section III

This section describes the maintenance of the Tandy 102.

Section IV

This section describes the general theory of operation for the Tandy 102.

Section V

This section describes how to troubleshoot the Tandy 102.

Section VI

This section provides an exploded view and parts list of the Tandy 102.

Section VII

This section provides the schematics, PCB diagrams, and silkscreen views of the PCBs of the

Tandy 102.

Appendix A

This appendix provides instructions for installing the optional ROM and additional RAMs.

Appendix B

This appendix provides the character code table, keyboard layouts and connector pin

assignments.

Appendix C

This appendix provides the technical information of the 80C85A, 81 C55, 6402 and LCD.

System Overview

Tandy 102 portable computer is a low cost version of the Radio Shack TRS-80 Model 100 Portable
Computer. The Tandy 102 is fully compatible with the Model 100 in its software so that both system
users can take advantage of the large number of programs available.

The Tandy 102 has the following applications programs in the standard ROM: BASIC, TEXT,

TELCOM, ADDRSS, SCHEDL and TELCOM.

External View

1 Keyboard: Can be used like the standard typewriter. However, the Tandy 102 does have a few

speciatkeys. (See Appendix B of this manual for more details.)

2 LCD Screen: The Tandy 102 display has eight lines that allow 40 characters on each line.
3 Power Switch: Move this switch towards the front to turn the power on. To conserve the

batteries, the Tandy 102 automatically turns the power off if you do not use it for 10 minutes in

default setting.

4 Low Battery Indicator: Before the Tandy 102 is operational batteries become exhausted, this

indicator will illuminate.

5 Display Adjustment Dial: This control adjusts the contrast of the LCD display relative to the

viewing angle.

6 External Power Adapter Connector: Connect the appropriate and of Radio Shack's AC Power

Supply (Catalog Number 26-3804, optional/extra) to this connector. Connect the other end of
the power supply to a standard AC wall-outlet or approved power strip.

1 Keyboard 2 LCD Screen 4 Low Battery

Indicator

11-1 11-1

1-1

N,

11-1

ZZ

6 External Power Adapter

Connector

5 Display Adjustment

Dial

3 Power Switch

Figure 1-1. Front View

1-2

1 RESET Switch: If the Tandy 102 "locks up" (i.e., the display "freezes" and all keys seem to be

inoperative), press this button to return to the Main Menu (start-up). It is not likely that the

Tandy 102 will lock-up when you are using the built-in applications programs, however, it may

occur with customized programs.

2 RS-232C Connector: Attach a DB-25 cable (such as Radio Shack Catalog Number 26-1408) to

this connector when you need to receive or transmit serial information. When you

communicating directly with another TRS-80 computer, a Null MODEM Adapter (26-1496) is

required. An 8" Cable Extender (26-1497) may also be required.

3 SYSTEM BUS Connector: Connect this connector to the TRS-80 Disk/Video interface

(26-3806), using the system bus cable.

4 PRINTER Connctor: For hard-copy printouts of information, attach any Radio Shack parallel

printer to this connector, using an optional/extra printer cable.

5 Direct-Connect MODEM (PHONE) Connector: When communicating with another computer via

the Tandy 102's built-in MODEM, connect the round end of the optional/extra MODEM cable

to this connector.

6 CASSETTE Recorder Connector: To save or load information, on a cassette tape, connect the

cassette recorder here. An optional/extra cassette recorder (and cable) is required.

7 Bar Code Wand Connector: Attach the optional/extra bar code wand to this connector. Note

that special bar code reader software is required.

8 DIR/ACP Selector: This selector allows you to select either a direct or acoustic coupler

connection. If you are communicating with another computer over the phone lines via the

built-in, direct-connect MODEM, set this switch to the DIR position. If you are using the
optional/extra Model 100 Acoustic Coupler (26-3805), set this connector to the ACP position.

9 ANS/ ORIG Selector: If you are "originating" a phone call to another computer, set this switch

to ORIG. If another computer is calling your Tandy 102, set to ANS.

5 Direct-Connect

MODEM (PHONE) Connector

6 CASSETTE Recorder

Connector

4 PRINTER Connector

3 SYSTEM BUS Connector

1 RESET Switch

2 RS-232C Connector

Figure 1-2. Rear View

9 ANS/ORIG Selector

8 DIR/ACP Selector

7 Bar Code Wand

Connector

1-3

1 MEMORY POWER Switch: This switch is used to prevent discharge of the internal

Nickel-Cadmium battery, which is used for RAM back-up. The Tandy 102 will operate only

when the power switch is set to ON. Set this switch to the OFF position when the Tandy 102 will

not be used for a long period of time. Note that the RAM will not be backed up when this switch

is set to the OFF position.

2 Optional ROM and RAM Compartment: An optional/extra ROM and RAM can be inserted into

this compartment to enhance the Tandy 102 capabilities.

3 Battery Compartment : When not connected to an AC power source, the Tandy 102 gets its

power from four AA size batteries that must be installed in this compartment.

3 BATTERY Compartment

1 MEMORY POWER 2 OPTIONAL ROM and RAM

Switch Compartment

X

X

11

O

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Figure 1-3. Bottom View

Internal View

The Tandy 102 consists of three printed circuit boards:

• LCD PCB

• Keyboard PCB

• Main PCB

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Specifications
Main Components

Keyboard

Life of key switch
Number of keys

Function keys
Caps/NUM lock key
Other keys

LCD display

Display panel

Dot pitch
Dot size

Effective display area

Operation batteries

Batteries

Operation time

Memory protection battery (On Main PCB)

Battery

Back-up time
Recharge method
Charging current

LSIs

CPU

ROM

RAM

Power consumption

Dimensions

Weight

72 keys (8 x 9 key matrix)
3 millions keystrokes

0.5 million keystrokes
5 millions keystrokes

240 x 64 full-dot matrix

1/32 duty
1/6.66 bias

0.8 x 0.8 mm

0.73x0.73 mm

191.2(W) X 50.4(D) mm

Four type AA

Alkaline-manganese batteries

5 days (Typ.) - 4 hours per day
20 days (Typ.) - 1 hour per day

(Note: without I/O units at normal temparature)

Rechargeable battery (50mAh/3.6V)
More than 20 days-16 KB RAM
More than 10 days-32 KB RAM
Trickle charge by AC adapter
operation batteries

1.2 mA (Typ.)

80C85A

Code and pin compatible with 8085
Maximum 64 KB

Standard 32 KB

Optional 32 KB
Maximum 32 KB

Standard 24 KB

Optional 8 KB

65 mA (Typ.)

11-3/4" (W) X 8-1/2" (D) X 1-1 /2" (H)

300 (W) X 215 (D) X 38.5 (H) mm

3 lbs. 2 oz.

(with batteries)

1.4 kg

I/O Interface

RS-232C

Conforms to EIA standard signal

Communications protocol

Word length

Parity

Stop bit length

Baud rate

Maximum transmission distance
Maximum driver output voltage
Minimum driver output voltage
Maximun receiver input voltage
Minimum receiver input vltage

MODEMICoupler

Conforms to BELL 103 Standard

Data length
Parity

Stop bit length

Baud rate

Full duplex
Transmit output level
Receive sensitivity
Other functions

Printer interface

Conforms to Centronics interface standards

Handshake signals

Audio cassette interface

Data rate

Input level
Output level

Bar code reader interface

Input level

TXR (Transmit Data)

RXR (Receive Data)
RTS (Request to Send)
CTS (Clear to Send)

DSR (Data Set Ready)
DTR (Data Terminal Ready)

6, 7, or 8 bits
NONE, EVEN or ODD
1 or 2 bits
75, 110, 300, 600, 1200, 2400,
4800, 9600 or 19200 BPS
5 meters

± 5 volts
±

3.5 volts
± 18 volts
± 3 volts

6, 7 or 8 bits
NONE, EVEN or ODD
1 or 2 bits
300 BPS

Answer mode/originate mode switchable

15 dBm ± 2dBm

-30 dBm
Hang-up function

Auto pulse dialing function

10/20 PPS

STROBE, BUSY, BUSY

1500 BPS

(Mark 2400 Hz, Space 1200 Hz)

0.8 to 5 volts (Peak to peak)

580 mV ± 10%

3.5 volts (Min.)-High

1.5 volts (Max.)-low

II. DISASSEMBLY INSTRUCTIONS

Cases

1. Disconnect the cables from the unit.

Taking care not to scratch the LCD screen and key tops, turn the unit over and remove 4 screws

A from the upper and lower cases.

2. Remove the upper case.

Therefore, the upper and lower cases are secured by snaps. Pull up the front of the upper case

first, as shown below.
Also, do not apply too much force when pulling it.

A

Figure 2-1. Top Case Removal

Keyboard and LCD PCBs

1. Disconnect the flat cable from the connector on the keyboard PCB.

2. Remove the keyboard PCB.

3. Disconnect the flat cable from the connector on the LCD PCB.

4. Remove the LCD PCB.

V

V

1 I

1

e

C5

Figure 2-2. Keyboard and LCD PCBs Removal

2-1

Main PCB

1. Remove the insulator board.

2. Remove 2 screws B securing the main PCB and bottom case.

3. Remove the main PCB.

B

U

0

C)

CD

U

Figure 2-3. Main PCB Removal

III. MAINTENANCE

To Clean the Body and LCD Display

1. To avoid operational trouble, always keep the Tandy 102 clean.

2. Clean the body and the LCD screen using a soft, dry, lint-free cloth.

3. For tough stains, clean the body or the LCD screen with benzol.

Caution: Do not use any solvents other than benzol.

á

IV. THEORY OF OPERATION

General

Figure 4-1 shows how this section is organized and highlights significant areas.

Theory of

Operation

General

Block

Diagram

CPU I 1

Memory

Address

Decoding and
Bank Selection

Circuit

Keyboard

System Bus

Cassette

Interface

Circuit

11

Read Circuit

Remote Circuit

Clock Control
Circuit

Timer Set

Sequence

Timer Read

Sequence

Printer Interface

Circuit

Serial Interface

Circuit

Bar Code

Reader Interface

Circuit

LCD

fRS-232C/

LCD Common

MODEM

Driver

Selection Circuit

RS-232C LCD Segment
Interface Circuit Driver

MODEM IC LCD Waveform

Transmission

Filter Circuit

Reception Filter

Circuit

MODEM

Transmitting

Level

Adjustment

y

MODEM
Connector

Circuit

Figure 4-1. Organization of Section IV

I

1

I/O Map

Buzzer Control
Circuit

Signal from PB5

of PIO

Using PIO Times
Output

Power Supply
and Auto- Power

ON/OFF Circuit

DC/DC

Converter

Low Power

Detection Circuit

Reset Circuit

4-1

Block Diagram

The Tandy 102 has three principal LSIs.

• 8OC85A CPU

This is the Central Processing Unit which controls all functions.

• 81 C55 PIO

This is the Parallel Input/Output interface controller which controls the printer interface,

keyboard, buzzer, clock and LCD interface.

• 6402 UART

This is the Universal Asynchronous Receiver Transmitter which controls the serial interface

(RS-232C or MODEM).

The input/output for a cassette recorder and the input of the BCR are controlled by CPU directly

through its SOD, SID and RST5.5 terminals.

ROM and RAMs are connected to the system bus. ROM is available only for alternative selection

from Standard or Option.

CPU

8OC85

CASSETTE

INTERFACE

ROM

32KB

STANDARD

RAM
8KB

FKEYBOARD PC B

I

KEYBOARD i

PIO

PRINTER

81 C55

INTERFACE

RAM

8KB

RAM
8KB

I

i

LCD

CONTROL

I I

I RAM

8KB

OPTION

ROM

32KB

OPTION

LCD P

U A RT

6402

SYSTEM BUS

SOCKET

Figure 4-2. System Block Diagram

CLOCK

LCD yPD1990AC

RS-232C

INTERFACE

CPU

The CPU is an 80C85A that runs at a clock speed of 2.4576 MHz. It is an 8-bit, parallel Central

Processing Unit using C-MOS technology.- The instruction set is fully compatible with the 8085A
microprocessor. The 80C85A uses a multiplexed data bus. The CPU bus is divided into two

sections- the 8-bit address bus named the A8-A1 5, and the 8-bit address and data bus named the
ADO-AD7. The address bus signals are separated at M1, using the ALE* (Address Latch Enable)
signal.

M20.M21

CPU

A8-415 ",

M2

ADO-

AD7

RD

ALE

M20

RDA

ALEX

AS -A15

A0-A7

ADO-AD7

M20

Figure 4-3. Functional Block Diagram of Bus Separation Circuit

Memory

The memory of the Tandy 102 consists of a 32 KB standard ROM, three 8 KB C-MOS static RAMs

and a 32 KB optional ROM.

The standard RAMs equipped in the Tandy 102 are M9, M8 and M7. By installing M6, memory

capacity can be increased to 32 KB. The ROM used in the Tandy 102 is a 32 KB (256K bits)

memory.

It is operated only by a +5V power source with an access time of 600 nsec (Max.).

The BASIC program and BIOS program which operate the LCD, printer etc. are stored in the

standard ROM.
An optional ROM can be installed onto the special IC socket by removing the ROM cover on the
bottom case of the Tandy 102. Various types of application programs are stored in the optional

ROM.

0000H

( 32K Byte)

STANDARD

ROM

7FFFH

8000H

OPTION

RAM I

9FFFH ( 8K B te)

AOOOH ST A

RAM 3

BFFFH

(SK B to)

COOOH

STANDARD

DFFFH

RAM 2

E000H STANDARD

RAM I

FFFFH

K

B t

Figure 4-4. Memory Map

OPTION

BAN K

SELECTION (32K Byte)

-- - - - - -STANDARD

4-3

Address Decoding and Bank Selection Circuit

Although four 8 KB static RAMs and two masked ROMs can be installed in the Tandy 102, six

chip-select signals are required.

Because the RAMs are positioned from 8000H to FFFFH, and ROMs are positioned from OOOOH to
7FFFH, address signal Al 5 selects the ROMs or RAMs at M5. At another section of M15, address
signals Al 4 and A13 select each RAM corresponding to the memory map. The ROMs (both
standard and optional) installed in the Tandy 102 are the 32 KB 1-chip type. As shown in the

memory map, the address space is positioned from OOOOH to 7FFFH.

The chip select signals are generated by the A15 and STROM signals. The ADO is latched at M14

by the WR signal and Y6 signal, and then the STROM signal is generated.
The standard ROM is selected by the low level STROM signal and the optional ROM is selected by

the high level STROM signal.

M5

TO 4

Y1 5

Y2 6

M5

0000-7FFFH

Standard ROM

0000-7FFFH

Option ROM

8000-9FFFH

ADO

4 D Q

2 STROM 2 A

7

Y6 10

8

M14

3

Y3

9 26 9 C 8

WR*
RDXE

A15

A13

A14

5 6

4 17

1 11

10 TO 12 Option RAM

13

37

37

85

G

9

Y1 11

12 0 11 A0#

A000-BFFFH

RAM # 3

0000-DFFFH

Y2 10

RAM #2

14 A
13

Y3

9

8

E000-FFFFH

RAM #1

Figure 4-5. Address Decoding and Bank Selection Circuit

I/O MAP

As shown in the figure below, the I/O address decoding circuit, consisting of M16, decodes address

signals A12 to Al 5 and generates I/O selection signals YO to Y7.

The application of the selection signals (YO to Y7) for the I/O devices are shown in Table 4-1.

Table 4-2 shows the port address of the PIO.

16

6

15

10f

G1

14

YO

1

M16

NC

3 4 13

A15

M17

G 2A

Y2

5

12

2

G2B Y3

40H138

1I

Y4

3 10

A 14

C

Y5

2

9

A13

B

Y6

7

A 12

A Y7

8

Figure 4-6. I/O Address Decoding Circuit

Address

Signal

Active Level Application

Free area for an optional unit and other select sig-

OOH - 7FH -

nals of various circuits made by user.

80 - 8FH YO L Device-select signal for optional I/O controller unit.

Enable signal for relay RY3 in MODEM connector

90H - 9FH Y2

L

interface circuit.

BOH - BFH

Y3

L PIO (81 C55) chip-select signal.

COH - CFH Y4 L Enable signal for data input/output port of UART.

Enable signal to set various modes and read port

DOH - DFH Y5 L

of UART.

Enable signal for STROM and REMOTE, and input

EOH - EFH

Y6

L data from keyboard.

Strobe signal for printer and clock.

FOH - FFH Y7

L

Enable signal for LCD driver LSI.

Table 4-1. I/O Map

Address

BOH or B8H

B1 H or B9H

82H or BAH

B3H or BBH
B4H or BCH
B5H or BDH
B6H, B7H, B8H and B9H

Port or Register

Command/status register (internal)
Port A
Port B
Port C

Timer register lower byte

Timer register upper byte

Not used

Table 4-2. Port Address of PIO

4-5

Keyboard

Key strobe signals are emitted from the PAO to PA7 and PBO terminals of the PIO. The return
signals from the keyboard pass through the bus buffers (Ml 5 and M3) and send to the CPU. The I/O

address of the return signals is EOH-EFH.
The condition of pressing the "T" key is shown in the figure below.

33KX8

KR7

17

AD7

L

AD IS

KR6

16

M

AD 5

KR5

15

N

AD4

M15

KR4 - -

--

- 14

- B

M3

AD3

KR3

43

V

A02

KR2

12

C

AD 1

KR1 11

x

KRO

110

ADO

Z

82PXB

K

KEYBOARD UNIT

J U >

H Y

D I E ]

s

A I

W P

Q

0

f8

WRE

ME

a 4

PRI

T

f7

A -e

t

EL

P

E

f6

f5

PS

S +

4

ESC

TAB

f4

f3

co

DE

PH

n4

DEL

f2

RL

/

(

SFA

C E

f1

SHI

FT

2 13 4 5 6 7 8 9

CD

0

D . D D D D D

0 N W A

O W -

Figure 4-7. Condition of Pressing "T" Key

SHI

FT

J

Cassette Interface Circuit

The cassette interface circuit is subdivided into three sections:

• Write circuit

• Read circuit

• Remote circuit

Write Circuit

The write circuit is accomplished in several steps. First, the serial data from the SOD terminal of the

CPU is inverted by M34. Then, the DC component is removed by C63. Finally, the data

passes through an integrator consisting of R51 and C64, and after voltage division, out to a

cassette recorder AUX jack.

Read Circuit

The signal input from the earphone jack of the cassette recorder passes through the clamp circuit

consisting of D5 and D6, and then is input to the comparator circuit consisting of M30.

Finally, the signal is converted into the digital signal and sent to the SID terminal of the CPU.
In this circuit, D7 clamps the negative voltage output of the comparator.

Remote Circuit

As a result of writing data "1" into bit 3 of the output port (Ml 4) specified by I/O address EOH-EFH,

the REMOTE signal is changed to H level.

Then, T6 is switched on and relay RY1 is energized. This causes the drive motor of the cassette

recorder to operate.

0
0

TXC

Y. It

IS) M t0

E-- ,n U

C

D: M

5

R54 R51

C63 2 1

pj j 1j SOD

3

7

12K 2 .2K 0.1p

VDD VDD

4584

R95 R52

4584

RXC

4

8

RY 1

10012 1 K

M

13

M30

4

R72

5 6 SID

REMi

r'---1

VR )X

,n

x

+ 14 33K -

p 11

1 4 5

08

C 0

ti 12

L

REM2

3

I I ( 1-

0 so

I

I p'

N Y VEE

2

0

M

t_ 0

GND 1 I

N

M Y

N

D N

GND 6

6 21

a)

R132150K

L. _ --- .j R50

T6

3.3 K

REMOTE

Figure 4-8. Cassette Interface Circuit

Printer Interface Circuit

The printer interface circuit conforms to Centronics standards. As shown in Figure 4-9, the BUSY
signal from the printer is read from the PC2 of the PIO. If the condition is not busy (PC2 = L), the

8-bit parallel data (PAO - PA7) is sent to the printer. Then, by writing data "1 " into bit 1 of the output

port specified by I/O address EOH-EFH, the PSTB signal is sent to the printer.

As soon as the printer receives this PSTB signal, the BUSY signal is changed to H indicating that

the printer is busy. The CPU then waits for a while until this BUSY signal becomes L. The printer

prints the one character corresponding with the 8-bit parallel data. After completion of the one
character printing, the printer sets the BUSY signal to L. Then, the CPU sends the next 8-bit parallel
data. If the printer is in ONLINE condition, the BUSY signal is H and sent to the CPU, passing

through the PC1 of the PIO. However, when in the OFFLINE condition, the BUSY signal is L and
transmission of print data to the printer is inhibited by the CPU.

PSTB

AD1 5 DM14

Q

6

1

STROBE
GND

PAO

PA 1

0

3

A

PDO

GND

PD1

6

GND

10

PA 2

3

PD2

Y6

26

8

8

GND

9

WR PA3

32

P03

0:

9

PA4

PA 5

10

GND

0

12

PD4

GND

U

PD5

W

Z

# GND

z

PA 6

10

PD6 0

16

GND

U

BUSY

PA 7

10

1 PD7

VDD

GND

0:

W

20

GND

i^

PAO-7 21

BUSY

Z_

5-

PC2

GND

0

STROBE

R 6433K

_

24

NC

R6833K GND

PCI

BUSY

0.5 A (Min)

C38 100P

Ill

Figure 4-9. Printer Interface Circuit

Bar Code Reader Interface Circuit

The input signal from the bar code reader is subjected to waveform shaping, inverted by the
Schmitt-type inverter (M34), and then sent to the PC3 terminal of the PIO and the RST5.5 terminal of
the CPU.
When the bar code reader reads the first white part of the bar code, a L level signal is generated,

then inverted by M34 to notify the CPU of an interruption. As soon as RST5.5 interruption occurs,

the CPU starts the data input operation, passing through the PC3 of the PIO. As the bar code

reader is moved across the bars, H and L signals (which correspond to the white and black bars,
respectively) are generated continuously and inversion signals are sent to the PC3 of the PIO as the
serial input data stream.

BLACK LINE

WHITE LINE

VDD

BLACK LINE

WHITE LINE

CNI

Y

0

M

ti

Q:

M

I

RXD

2

13

M

12

BCR

( 8IC55-PC3)

9

VDD

Voo

RST5.5

GND

5

NC

(CPU)

GND

7

1

3

6

NC

4

8

Figure 4-10. Bar Code Reader Interface Circuit

Buzzer Control Circuit

There are two ways to operate the buzzer. One is to sound the buzzer with the specified frequency

by emitting signals from the PB5 of the PIO and the other, by using the timer output signal of the

PIO.

Signal from PB5 of PIO

When the PB2 of the PIO is H, the buzzer sounds by repeated switching of the buzzer driving
transistor. This is caused by H, L, H, L ... output signals from the PB5 synchronizing with the

frequency for sounding the buzzer. This method is used for the BEEP command in BASIC.

PIO Timer Output

In this method, the buzzer is sounded by setting the PIO timer in the square wave output mode. To

write the value corresponding to the sound frequency, the CPU assigns B4H, B5H, BCH or BDH to
the I/O port address. This frequency is assigned by the first parameter of the SOUND command in

BASIC.

If the above procedures are completed, the TO terminal of the PIO outputs the square waves, and

the P62 of the PIO controls the length of the sound whenever the PB5 is "L". How long the sound is

heard depends on the second parameter of SOUND command in BASIC.

VDD

R4

BUZZER

PB5

M25

VDD

P10

PB2

31

TO

6

R3

33K

33K

R61

33K

12

11

13

M26

R2
33K

T1

2 SA

1162

R113

3.3 K

V EE

Figure 4-11. Buzzer Control Circuit

oa

System Bus

In order to expand the use of external devices, a 40-pin system bus connector is mounted on the

back panel of the Tandy 102.
As shown in the Table 4-3, the address bus, data bus and control bus can be connected to the
external devices passing through the drivers or receivers, thus making system expansion easy.

Pin No.

Signal

Description

1

VDD

+5V power supply

2

VDD

+5V power supply

3

GND

Ground

4

GND

Ground

5

ADO

Address and data signal bit 0

6

AD1

Address and data signal bit 1

7

AD2

Address and data signal bit 2

8

AD3

Address and data signal bit 3

9

AD4

Address and data signal bit 4

10

AD5

Address and data signal bit 5

11

AD6

Address and data signal bit 6

12

AD7

Address and data signal bit 7

13

A8

Address signal bit 8

14

A9

Address signal bit 9

15

A10

Address signal bit 10

16

All

Address signal bit 11

17

A12

Address signal bit 12

18

A13

Address signal bit 13

19

A14

Address signal bit 14

20

A15

Address signal bit 15

21

GND

Ground

22

GND

Ground

23

RD*

Read enable signal

24

WR*

Write enable signal

25

10/M *

I/O or memory select signal

26

SO

Status 0 signal

27

ALE*

Address latch enable signal

28

Si

Status 1 signal

29

CLK Clock signal

30

YO

I/O controller select signal

31

A*

I/O or memory access enable signal

32

RESET*

Reset signal

33

INTR

Interrupt request signal

34

INTA

Interrupt acknowledge signal

35

GND

Ground

36

GND

Ground

37

RAM RST

RAM enable signal

38

NC

No connection

39

NC

No connection

40

NC

No connection

Table 4-3. System Bus Pin Assignments

Clock Control Circuit

A clock LSI (4PD1990AC) is used in the clock control circuit so that the time and date information

can be set and read by the CPU.

As shown in Figures 4-12 to 4-13, when the Tandy 102 is in the operable condition (RESET is H),

commands and data can be input and output to,uPD1990AC from the CPU at will. In addition,
because back-up power supply VB is applied to theuPD1990AC, the clock functions even when the

Tandy 102 power switch is OFF.

The DATA IN, CLOCK and C0-C2 terminals ofpPD1990AC are connected to the PAO-PA4 terminals

of the PIO. The DATA OUT terminal is connected to the PCO terminal of the PIO. The STB signal is
provided from bit 2 of the output port made by M14.

The TP terminal of the ,uPD1990AC is connected to the RST7.5 terminal of the CPU. Square waves

are output from the TP (4 ms cycle), and one key scan occurs every 4 ms because of the RST7.5

interruption to the CPU.

Time Set Sequence

The CPU set 4uPD1990AC to the register shift mode with the "100" pattern of the C0-C2 and the

strobe signal which is generated by the AD2, Y6 and WR* signals passing through M14.

Then, the CPU sends the data of time and date information to the DATA IN terminal of,uPD1990AC

with timing clock PA3.

Finally, the CPU sets APD1990AC to the time set mode with the "010" pattern of the C0-C2 and the

strobe signal.

120 010

Y6 -

WR* -

M26

_FL

AD 2

40H 175

40H175

M14 M14

CK CLR

CK CLR

-- 1

Y6

MZ J

WR*--

0

RESET

MU

rna

a.

RESET

gr

C19

0.047J1

25V

VB VB

T

TP CS STB 12

cis

20P

14 OE TP CS STB 12

cis

20P

T

14 OE

O

T

O

U

7

JJPD I990AC M18 xi c3

13

C17

20P

32.768 kHz

1 i

O N V M

a a a a a

CO C1 C2 DATAIN CLK

11

O.047;,

JJPD1990AC M18 xi c3

25V

7

120 0

10

Y

MU Ma

i-

a.

CO C 1 C2 DATAIN CLK

1 1

t 1

O Cu

a a a

C1

20P

13

32.768 kHz

Figure 4-12. Time Set Sequence of ,uPD1990AC

Time Read Sequence

The CPU sets the pPD1 990AC to the time read mode with the "110" pattern of the C0-C2 and strobe

signal.
Then the CPU sets the register shift mode with the "100" pattern of the C0-C2, and reads the data of
time and date information from the DATA OUT terminal. At the same time, the CPU sends the PA3

signal passing through the PIO for the read timing clock.

Y6 -

WR*--

M26

32.768 kHz

M2

RESET

RESET

-Y y

M O

M U MCL

F-

C19

0.047)J

25V

VB

14 OE D DATA TP CS STB 12

C18

20P

I

T

JJPD I990AC M

18 x1 O

CO Cl C2 DATAIN CLK

13 C17

20P

Y6 -

WR*--

C19

0.047)j

25V

7

CO C1 C2

DATAIN CLK

13

C1720P

32.768 kHz

O - N M

a a a. a

Figure 4-13. Time Read Sequence of ,uPD1990AC

VB

14 OE DATA TP CS STB 12

C18

20P

OUT

11

JJPD1990AC M18 x1p

Serial Interface Circuit

The serial interface circuit supports asynchronous data transmission/reception. The heart of this

circuit is the 6402 (UART). It performs the job of converting the parallel byte data from the CPU to a
serial data stream including start, stop and parity bits.

For a more detailed description of how this IC performs these functions, refer to Appendix C of this

manual.

Figure 4-14 shows the functional block diagram of the serial interface circuit. In this figure, the TO
signal, basic timing clock for the UART, defines the transmission/reception baud rate.
To transmit and receive the serial data from external devices, the RS232C signal selects either

MODEM or RS-232C interface. During the MODEM operation, the MODE signal switches either the

originate mode or answer mode for the MODEM IC.
The serial interface circuit is subdivided into the following circuits:

• RS-232C/MODEM Selection Circuit

• RS-232C Interface Circuit

• MODEM IC

• Transmission Filter Circuit

• Reception Filter Circuit

• MODEM Connector Circuit

RS232C

DT-R

CPU

PI0

R

M

D R

UART

TRO

RRI

OE.FE.PE.

M38 M TS

M13

CL/AS

M33

OORIRIrGo

RXCAR h ANS

RXM

TXM

M31

MODEM

CP/TL

M23

M4

M26

MODE

M24

DIR

ACP

DIR

ACP

CN6

U

N

:Y °

Er

RY2 RY3L

CN4

TXMD

TL

TXM

RXM

RP

Figure 4-14. Functional Block Diagram of the Serial Interface

RS-232C/MODEM Selection Circuit

The RS232C signal (PB3 terminal of the PIO) determines whether the serial port is to be used for

RS-232C or for MODEM. When the RS232C signal is H, the serial port is used for MODEM.
The reception signals, including the control signals, are demultiplexed at M33.

During the RS-232C mode, the CD (Carrier Detect) signal is not used. To make this condition, pin

14 of M33 is connected to the ground.

During the MODEM mode, the CL/AS signal is used as the sensing signal for the ORG/ANS switch,

and CP/TL signal is used as the sensing signal for the ACP/DIR switch. In order to detect the
carrier signal from the telephone line, the CD signal is connected to the RXCAR terminal of the

MODEM IC.

1A 2 RXR

1A 2

1 0

/2A 11 CTSR

Ao

2A 5

r-------- S = 3 DSRR

S =3

3A

14

I //// //4A I

to 4A

RRI 4 1Y Z;w 1B 3 RRI 4 1Y' '+ 1B RXM

CTS

T

2Y 2B

6

CTS 7 Y 2B WAS

DSR

9

3y

3B 10 DSR 9 ' 1 CP/TL

CD 12 4Y 4B 13 CD 12

3Y

4Y 1 RXCAR

9 9

RTS

10 M13

r-

19

TXR 10 M13

8

1011 13

.8 38

12

M RTSR

TRO

3

2

M38

9

108

M38

2

38

1

3 3

A

RS-232C

W
N

n

MODEM

TXM(M31)

RTSM

Figure 4-15. RS-232C/ MODEM Selection Circuit

RS-232C Interface Circuit

In the RS-232C transmission circuit, after the DC component is removed from the signals by the

coupling capacitors, the signals are leveled to ±5V signals by the inverters connected in
parallel, and then are output as RS-232C transmission signals.

In the RS-232C reception circuit, the DSRR, CTSR, and RXR signals from the external RS-232C line

are subjected to waveform shaping and inverted by M24, and then converted to +5V or ground level

signals by the diodes.

(0

GND 1

Z 2

0 TXR

RTSR

DTRR

DSRR

CTSR

RXR

GND

4

20

6

4584

i2_ -- 13 --- -1 VDD

35 1 R75100K R73 33K

2 1

R9 330n 110

35

11

R9433

35

I 4 3

35

18

35 9

R99 330n]

R89

6.2K

5

35

R74 33K

C71 o. 039)1

R7 1OOK R76 33K

M13 (pin8)

M 38 (pin 13)

M 25 (pin 35)

M 33 (pin11 )

R77 33K

C72 0.039 )L

R81 1OOK R79 33K

R80 33K

C 73

O.O39.

R65

DTR

VEE

13 2 12

1 R137 i00K

R96 18K D9

5 R8 6.2K 9 24 8

I

R138 1OOK

R9 18K D10

3 R87 6.2K 11 24 10

R139 1ooK

7 I

I

D8

R9218K L ---------

VEE

33K

VDD

M33 (pin 5)

M 33 (pin 2)

Figure 4-16. RS-232C Interface Circuit

MODEM IC

The Tandy 102 employs the IC MC14412 as a MODEM control device. This IC modulates/
demodulates data to be transmitted/received in accordance with frequencies suitable for originate

or answer mode respectively.

The RXRATE and TYPE terminals of the MC14412 (M31) are pulled up to VDD. The baud rate is set
to 300 bps and the U.S.Standard is selected. Since the ECHO and SELFTEST terminals are not

needed, they are connected to ground.
The Q output (EN signal) of the M36 selected by bit 1 of the Y2 port is input to the ENABLE terminal
when the MODEM mode is selected.

In addition, the signal detected by the ORG/ANS switch is input to the MODE terminal, and it

switches between the ORIGINATE mode or ANSWER mode.

R47 15M

0

MHz

VDD

XTAL1

R46

VDD

16

33K

RXRATE

6

15

TO TRANSMISSION

TTLD

14

FILTER CIRCUIT

TYPE

TXCAR

13

ECHO

2

9

Y2

FROM RECEPTION

FILTER CIRCUIT

SLFTEST

Vss

RXCAR

B

12

C

M13

TT C)02

7H IOOP

10

WR*

VDO

ENABLE

0 D

AD)

10

MODE

7

ORIG

ANS

RXM

1

RS-232C/MODEM

J

R12

TXM

SELECTION CIRCUIT

1K

RESET

5

RESET

MB

(MC14412)

Figure 4-17. MODEM IC and Peripheral Circuit

Transmission Filter Circuit

The DC component of the carrier output from the TXCAR terminal is removed by C61. The signal

level is adjusted by the potentiometer VR2. The signal then passes through the transmission
band-pass filter and is sent to the telephone line or the acoustic coupler.
The transmission filter circuit is composed of an active filter (consisting of an operation amplifier)
and the intermediate frequency of the active filter is 1170 Hz for the originate mode, and 2125 Hz

for the answer mode. They are changed by switching T4 ON or OFF.

C60 3500P

R44 242K

CN4

Pin-5

TXMC

OTI

R63620n

DIR 1

ACP

C59

2

3300P

R43 10K

M30

+3

R45

R42

7.97K 2.3K

M31

MC14412

C61 4700P

9 TXCAR

VR2
50K

VDD

R32 22a

C103 2 20,u

CL AS

ANS

R33

ORIG

T4 10K

R11

1K

Figure 4-18. Transmission Filter Circuit

4-17

Reception Filter Circuit

As shown in Figure 4-19, the reception input signal is amplified when passing through coupling

capacitor (C40), and amplified again as it passes through the 3-stage band-pass filter (composed of
an active filter). The signal then passes through the comparator, and after being changed to a
square wave, is input at the RXCAR terminal of the MC14412. Also, to check a carrier signal, this

signal is input to the demultiplexer M33.

The intermediate frequencies of the 3-stage active filter are shown below. The switching of

intermediate frequency for the originate and answer mode is accomplished by switching T2, T3 and

T5 ON or OFF according to the ORG/ANS switch position, thus changing the input resistance of the
filters.

1st stage 2nd stage 3rd stage

Intermediate

(

Originate Mode 980Hz 1150Hz 1330Hz

Frequercy Answer Mode 1940Hz 2120Hz 2290Hz

(d8)

G
f

(d 8)

GG

I

(dB)

0

I

i f(HZ) f(Hz) ; f(HZ)

C109 68P

C41 4700P C43 4700P C46 4700P , R35 10K

>n

470K 0z

y n C I

1110 VDD 1118 1129

Ma f

R30 n = 00

DIR C40 R19 4 732K 590K 332K 28OKF 422K

2 2K ' 0 I

0T7

13

14 1117

9 R15 7 R31 9 8

1 6 7 R41 D29

12 c

M29 M30 r---- M30

ACP

0047y tSK

M29

g

M29 Y

5

M29

n

*

3 10 5

10K

RXM->•0

+ 11

Qv+

R „{

e

+

cop of + TL064 + +

1-4

IS2076

Pin-4

VEE

R37

ORIG

ANS

1 VDD

R12

1K

R14 R26 R23

T2 T3

10K 10K 10K

C2712 C2712 C2712

TS

Figure 4-19. Reception Filter Circuit

180K

11160

f00K

93CAR

111311

4-18

Modem Transmitting Level Adjustment

1. Set the DIR/ACP switch to the DIR position.

2. Connect a 600-ohm dummy load between pin-3 (RXMD) and pin-7 (TXMD) of the MODEM
connector (CN4).

3. Connect an AC voltmeter across the above dummy load.

4. Set up the Tandy 102 in BASIC mode and enter the following command to generates the carrier
signal:

OUT 178 ,47 [ENTER]
OUT 168 ,02 [ENTER]

5. Adjust VR2 so as to read -14 to -17 dBm on the AC voltmeter for both ANS and ORIG modes.

600n

0

C

o ooooo0000

ooooo000000

0 0 0000 000

O

0

o

0

VR2

0

Figure 4-20. MODEM Adjustment

MODEM Connector Interface Circuit

When the acoustic coupler is used, the transmission and reception signals are directly connected

to the connector (TXM, RXM). When the MODEM cable is used, they are connected to the

secondary side of the driver transformer. The primary side of this transformer is connected to the

telephone line via the connector (TXMD, RXMD).
The ACP/DIR switch is used in the MODEM mode, relay RY3 separates the telephone receiver

audio signal (TL) to prevent interference. RY2, another relay, separates the MODEM circuit and the

telephone at the conclusion of use in the MODEM mode and is also used as an automatic dialer for

the pulse-type telephone line.

D16 VDD

ADO

Y2

WR*

VDD

MODEM

RTSM R49

T7 RY2

C1 03

6

CN4

3.3K R

48

I

220j

2

GND

6

F rom

Transmission

Filter Circuit

To Reception

Filter Circuit

ACP

DIR 620n

R63

ACP N
DIR Iv ""

D M36 p

C R134

3.3K

OT1

R135

68K

R32

TXM

22n 4

RXM

T

1 TL

TX MD

D24 D18

R171 I

RY3

VDD

T24

D21

C102

Figure 4-21. MODEM Connector Interface Circuit

D I D2 R21

RXMD

RP

LCD

The LCD used in the Tandy

102

is composed of electrodes in a matrix arrangement (64 common

signals and 480 segment signals) This part is subdivided into the following three sections:

• LCD Common Driver

• LCD Segment Driver

• LCD Waveform

For a more detailed description of how the LCD operates and its basic construction, refer to

Appendix C of this manual.

LCD Common Driver (HD44103)

The Tandy 102 uses two common driver ICs: M11 and M12. M11 controls the upper half of the LCD

screen and M12 controls the lower half of the LCD screen. M11 and M12 are cascade connected,
and a 1/32-duty backscan signal is made. By using C5 and R10 connected to the C and R terminals
of M11, a timing signal is generated, which controls M12. M11 can be considered to be the master

IC and M12 the slave.

The FRM signal defines the periodic frequency of one-screen display, and determines 70 Hz for the

Tandy 102.

The MB signal is used for changing the driver signal to AC, because the continuous application of

DC to the LCD would shorten the LCD element life.

The CL1 signal is used for the shift clock of the internal shift register.

The 01 and 02 signals are the clock signals for the HD44102 RAM operation.

2OLines

LCD Driver

DL Logic

CL

SHL

FCS

FRM

M Logic

Rf

Cf

OSC

20Lines

20Steps 8i-Directional

Shift Register

Divider Divider

CLK Logic

(01,02)

Frame Frequency Duty Selector

Selector

Logic DR

-f--0 VDD

-00--0 V1

+--o V 2
. --o V 5

----o V 6

--*---o VEE

Figure 4-22. HD44103 Internal Logic Diagram

LCD Segment Driver (HD44102)

M1-M10 (HD44102) on the LCD PCB are segment driver ICs that cause the display data sent from

the main PCB to be memorized in the built-in RAM and automatically generate the LCD drive signal.

One bit of data from the built-in RAM corresponds to one dot of illumination or non-illumination on

the display. The driver outputs are 50 lines.

The transfer of the display data is accomplished by 8-bit parallel data. This IC has several types of

commands. The D/I (H = data, L = command) signal distinguishes between commands and

data. The Tandy 102 has 240 segments each (upper and lower), the segment driver outputs Y41

-Y50 are not used. The power supplied to these ICs, in addition to VDD (+5V) and VEE (-5V), also

includes V1-V6.

VDD and VEE are the power supplies which operates the IC logic. V1 46 operate the LCD driver

signals.

V1 46 are made up by the resistance splitting of R1, R2, R3, R4 and R5. By passing through the
operational amplifier M13, the output impedance of the power supply is lessened.
Capacitors C3, C4, C6, C7 and C8 augment the peak current during LCD illumination.

50 Lines

CS

----0 VDD

----o V 1

---o V2

L C D Driver

-- V 3

----0 V4

D

A

D

A

50 Lines

50 Byte (0 Page)
50 Byte (1 Page)

U

.

--a VEE

r--0 GND

FRM

me

",vv

o

D
A

50 Byte (2 Page)

CL

M

av

D

A

50 Byte (3 Page)

N

3

3

E

R/W

D/1

ADO-7

8

BUSY

Logic CLK(01,02)

Figure 4-23. HD44102 Internal Logic Diagram

LCD Waveform

In order to drive the liquid-crystal element by the 1/32 duty line-sequential drive method, the LCD of

the Tandy 102 makes sequential selection of the 32 scanning electrodes.

For each dot, the display signal passes through the signal electrode and is applied 32 times for one
display.
At this point, the signal is necessary at each dot only one time. The signals for the other 31

times correspond to other dots on the same signal electrode.

The maximum voltage applied to common electrode and segment electrode is the potential

difference between V1 and V2.

In addition, "a" is the bias coefficient which determines, from the standpoint of contrast, the
maximum ratio between the illumination voltage and the non-illumination voltage.
When that ratio is the greatest in relation to the effective ON and OFF voltages, a = 6.66.

Thus, for V1, V2, V3, V4, V5 and V6:

V1 = VEE(-5V)
V2 = V (about 0-4V)

V3 = 2/aV

V4 = (1 -2/a)V

V5 = (1-1 /a)V

V6 = a/aV

VO ID

VO ID

COMMON

LINE

Q_UvOP

I

I I

2

VOP

Non-illumination

2

VOID

Segment Line

Z VOP

2 vOP

VO ID

illumination

Segment Line

Figure 4-24. LCD Waveform

4-23

Power Supply Circuit

The Tandy 102 logic circuit uses +5V for VDD, -5V for VEE and +4 to +5V for VB. These voltages

are supplied by the DC/DC converter. Also, the power supply circuit has the automatic power off

function and reset circuit.

DC/DC Converter Circuit

OT2 is a converter transformer which oscillates T21 and T22 and generates voltages at the
secondary side of the transformer. At the same time the power is switched ON, a very slight
collector current flows to T21 and T22. As the current flowing through OT2 is increased, the voltage

induced between pin 8 and pin 9 of the converter transformer causes pin 9 to be positive. The

positive voltage is applied to the base of T22 passing through R126 and C81 to activate T21 and

T22.

Fully charged, C81 stops the primary current. The secondary magnetic field begins to collapse,
reversing the polarity of the induced voltage, causing pin 9 to be negative. By being applied to the
base of T22 through C81, this voltage is used to turn OFF T21 and T22, as C81 discharges.

Discharged C81 allows the transistor to turn ON again to repeat this cycle. The switching frequency

is determined by R126 and C81.
The output of this circuit is derived from the secondary winding. VEE is from pin 9, rectified by D15,
filtered by C85, and VDD is from pin 7, rectified by D13, filtered by C84.

Also, VDD is fed back to the base of T13 through zener diode D4 to maintain VDD of +5V.

Low Power Detection Circuit

The low power detection circuit illuminates an LED warning lamp when the battery voltage
decreases. If it continues to decrease, the system power will be switched OFF just before the
voltage becomes so low that the converter cannot operate.
There are about 20 minutes between the time when the LED lamp illuminates and the system is

switched OFF.

Battery voltage is detected by splitting the resistance of R105, R108, R144 and R116. When the

battery voltage (VR) becomes 4.2V ± 0.1 V, T16 is switched OFF. T17 is switched ON, T19 is driven,
and the LED illuminates.

When VL becomes 3.7V ±, T14 is switched OFF, T15 is switched ON, and the LPS signal changes

from H to L. This signal is inverted by M34 and fed to the TRAP terminal of the CPU. If the CPU
acknowledges this signal, it sends the PCS signal passing through the PB4 of the PIO after the

internal operations.

When the PCS becomes H, the Q output of M28 becomes H, T20 operates and the oscillation of the

converter is stopped.

If there is no operation for 10 minutes or more (awaiting a command for 10 minutes or more), the

PCS is output from the PB4 of the PIO.
When the power switch is switched OFF, T18 is switched OFF, the RESET terminal of M28 becomes
H and oscillation is resumed by switching the power switch ON. If, however, the power is reduced

by the PCS signal, a battery replacement is necessary.

RESET Circuit

This circuit supplies the RESET signal and also the RAM RST signal as the protecting signal for the

contents of the RAM when the power decreases. C78 and R103 delay the introduction of input

power so that T11 is switched ON and T10 is switched OFF after VDD is activated, with the result
that the RESET signal changed from L to H. In the same way, the RAM RST signal is generated by
T9 and changes from H to L. Thermistor TH2 suppresses the RESET signal fluctuations due to

temperature.

T25 receives the signal from the Q terminal of M28 during automatic power OFF, short-circuiting

both ends of C78, and resets the system. The RESET signal is active L and the RAM RST signal is

active H.

RESET SW

SW4

J_

SPJ312U

C78 3.3p 50V D12 1S2076

1 .

a

no

N v _

N p 0 N 1- 1

R103 <

N

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C80

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0107

270P

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Cl

m

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IOK

R142 33K

O

N

TH2

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R90

ISK

O Si

01

0 R145 15K

A

-

A

`c

R86

CIII

n

x

w

3300P

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R85

m

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a

\

C69 1000 IOK

ml R108 R116

u

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v< c

TN1

22.6KF

R105

1SOKF \

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R83 22K I

27KF C99 P149 r \

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C11O 1000

1

m

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100K

Iy 50

1 +

L---I

023 ERACI-004

DRY BATTERY

D27

N

6

i

w

3-SIFT

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1111

R101

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II II 1.8K

IS2076

C70 O.Ip

SW3

5

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56K

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x

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R106

R123

1

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C90 0 N ro

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p N

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C83 470 p IOV m \

R82

33K

0

33K

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m

v

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A

R152 R153 a p

10K 33K

C82 4.7p 10V

Di051

1

21 +

R140

10K

0

G

A

t

N

150K

RIO?

1.8K

47K

R112

1.8 K

C53 0.1p 12V

C 27 f2

C100

r

2200P

R150

T22 47011

R 110

150K

Rill

150K

f0

O

A

R12T 22K

T13 CCI R126

27011

1000 P N A

r--

J

A

O p

H

1 p

N 04

G

~

O

m

w

m

0p C. 84 C85

+° 470 p6.3V

33y by

t i

0101 1r

4 1

+ 1

A

014

0

ID

RD 5.1 ELI

D

C86 lOOy

+ 6.3v

G) <

Figure 4-25. Power Supply and Reset Circuit

v

4-25

á

V. TROUBLESHOOTING

General Guidance

How to Make Use of This Section

If you have a problem or have to repair the Tandy 102, this section will be very helpful to you.
If the location or condition of the malfunctions are clear, for instance, the buzzer does not function,

refer to the flowchart in the TROUBLESHOOTING GUIDE and find the number circled. Then, you will

be able to find the necessary information, such as corresponding ICs and transistors, for

malfunction repair.

After you complete the malfunction repair, re-check each functional item according to the CHECK

LIST.

You can make use of the CHECK LIST even if the location and condition of the malfunction are not

clear.

Troubleshooting Guide

START

Doesn't work at all?

NO

1

YES

LCD doesn't function?

NO

2

YES

Keys don't function?

NO

3

YES

Buzzer doesn't function?

NO

4

YES

Clock doesn't function?

NO

5

YES

RESET doesn't function?

NO

6

YES

Memory protection doesn't function?

NO

7

YES

A

TO NEXT PAGE

5-1

A

Printer interface doesn't function?

NO

8

YES

Cassette interface doesn't function?

NO

9

YES

B.C.R. interface doesn't function?

NO

10

YES

RS-232C interface doesn't function?

NO

11

YES

MODEM interface doesn't function?

NO

12

YES

All functions check OK? NO

13

END

Checking Procedure

1. Doesn't work at all

1

Check the power.

• Check to be sure that the batteries are in and that the AC adapter is connected.

• Is the memory back-up power switch ON?

• Is the power switch ON?

Check the DC/DC converter circuit.

• Is 3.6 - 8V applied to pin 1 of the converter transformer?

(If not, check C82, C83, battery contacts and adapter jack.)

• Check all output voltages.

a) VDD ..... +5V (if not, check D13, C84 and ZD1)

b) VEE ..... -5V (if not, check D15, C85 and ZD2)

c) VB ..... +5V (if not, check T27 and T28)

• Is T21 oscillating?
(If not, check T22, T13, C81, R126, R127, R140 and T20.)

Check the RESET signal.

• Is it high level (+2.2V - 5.3V)?
If not, check T10, T11, T25, T9 RESET signal.

• Is it low level (0.8V - 0.3V)?
If not, check T10, T11, T25, T9 RESET signal.

• Check the CPU clock frequency.
(X1 terminal = 4.9152 MHz; CLK terminal = 2.4576 MHz)
(If not, check X2 and M 19.)

• Try replacing the LCU unit.

• Check all ICs.

END

2. LCD doesn't function

2

No display at all

YES

NO

Check-the source voltage (VDD, VEE, VB).

Refer to (1) "Doesn't work at all".

Check the RESET signal.
Refer to (6) "Reset doesn't function".

Check the LCD waveform.

(If abnormal, check the LCD power supply operation amplifier.)

Check the interface circuitry.
(Check all ICs connected to the bus line, M17 and M25.)

Check if the connector is correctly connected.

Check LCD drivers (on LCD PCB) HD44102 and HD44103.

(Or replace the LCD unit.)

END

3. Key doesn't function

3

Check if the keyboard connector is correctly connected.

Check the key scan signal.

Is the scan signal present at M25 PAO - PA7 and PB1 ?
(If not, check if pulses are emitted from the TP terminal (pin 10) of M18 and M25 at 4

msec intervals.)

Check the diodes on keyboard.

Check the return signal.

Check M15, M3, M26, M16 and pull-up resistors R163 - R170.

Check the key switching no-input keys.

END

4. Buzzer doesn't function

4

No melody is heard.

YES

NO

Check the connector connections.

• Check if the LCD connector is correctly connected.

• Check if the buzzer connector on LCD PCB is correctly connected.

Check the buzzer control logic.

Check M26 and M25 (PB5 port, TO terminal).

Check the buzzer.

END

5-5

5. Clock doesn't function

5

Check the power supply voltage.

• When power is ON: +5V

• When power is OFF: 2.0 - 4.OV
(If not normal, check power supply circuit.)

Check oscillation frequency (f = 32.768 kHz).

(If not normal, check X1, C17, C18 and M18.)

Check that a 250-Hz pulse is output from TP signal.

Check the clock- setting ICs (M14 and M25) and RESET signal.

END

6. Reset doesn't function

6

Check the RESET circuit.
(Check T11, T10, T9, T25, D20, D12 and C78.)

Check all ICs which have RESET and RESET signals.

(Check M19, M25, M22, M14, M27, M36 and M31. Also check the LCD unit and
RAM.)

END

5-6

7. Memory protection doesn't function

7

Check the power supply voltage.

• When power is ON: VB =+5V (if not, check converter circuit)

• When power is OFF: VB = 2.0 - 4.OV (if not, check Ni-Cad battery, D11 and D22)

Check to be sure that there is no deviation in the timing of the signal and that the
level changes symmetrically when the RAM RST and RESET are switched ON/OFF.

Check the CMOS RAM.

END

8. Printer interface doesn't function

8

Check the strobe signals.

Check M14 and M32.

Check the data signals.

Check M25, M10 and M32.

Check the connector and printer cable.

END

8. Cassette interface doesn't function

9

Check the TXC signals.

Is a modulated waveform output to pin 5 of the cassette connector during program

(DATA) save?
(If not, check M34, M19, C63 and C64.)

Check the RXC signals.

Is a digital waveform input to the SID terminal of the CPU during program (DATA)
load?

(If not, check D5, D6, M30, M34 and M19.)

Check the remote circuit.
Check the relay (RY1), T6 and M14.

Check the cassette connector and cassette cable.

END

10. B.C.R. interface doesn't function

10

Check M34, M25, M19 and L5.

Check the power supply voltage VDD (+5V).

END

11. RS-232C interface doesn't function

11

Check the transmit side.
Check if the switching digital signal (±5V - ±3.5V) is output to connector pin 2
during transmission. Then check if the CTS signal of pin 5 is low level.
(If not output, check M22, M24, M35, C71, C72 and C73.)

Check the receive side.

Check if a digital signal is input to M22 pin 20 (RRI terminal) during data reception.
Check also to be sure that the RTSR signal of pin 4 is low level.

(If not emitted, check M22, M24, M33, D9, D8 and D10.)

Check the RS-232C select signal.
Check if PB3 port (pin 32) of M25 is low level.
(If not, check M25 and M34.)

Check the RS-232C connector and cable.

END

12. Modem interface doesn't function

12

Check the transmit side.
Check if a modulation signal is output to connector pin 5 (in coupler mode) or
pin 7 (during direct mode) in transmission. Then check if the receiver carrier is
input to the M31 Rx Car terminal (pin 1).
(If not, check M22, M30, T4, T7, OT1 and RY2.)

Check receive side.

Check to be sure that the modulation signal is input to M31 pin 1 (Rx Car) during
data reception.

(If not, check M29, M30, OT1, T2, T3, T5, D1, D2 and RY2. If it is input, check M22

and M31.)

Check the automatic dialer.

Check RY2, RY3, T7, T24, M36 and M1 3.

END

13. All functions check ok?

13

Check the unit again, as described in the TROUBLESHOOTING GUIDE.

Check List

After completing all repairs and adjustments, check all functions according to the Test Program as
shown below. A model 100 diagnostics tape available through Radio Shack can also be used.

Before beginning the checking, initialize the RAM contents by performing a cold start. Refer to "(4)
Reset function test".

(1) Buzzer and LCD check (in BASIC mode)

10 FOR 1 = 0 TO 255
20 PRINT CHRS (1);
30 NEXT 1

40 END

After 1 beep and the LCD display clears, all characters are displayed.

(2) Clock test (in BASIC mode)

(a) Setting the year, month, date, day, hour, minute and second:

Year, month, date setting: Date$ = "MM/DD/YY"

Day setting: DAY$ _ "day" (example: Sunday = SUN)

Hour, minute, second setting: TIME$="HH: MM: SS"

(b) Confirmation of set data

Return to the menu by executing the MENU command. Then, check to be sure that the

calendar data changes to set data.

(3) Key board test

Refer to the character code table in Appendix B and check that all keys can be input.

(4) Reset function test (memory protection test)

(a) Warm start

Press the RESET switch on the rear of the case or switch the POWER switch to ON, and

check that initialization is made. Also check that the saved USER files are not erased.

(b) Cold start

While pressing the CTRL and PAUSE keys, press the RESET switch and check that all USER
files are erased.

(5) Printer interface test (in BASIC mode)

Input the characters to be printed out on the LCD display. When the hard copy key PRINT is

pressed, the displayed characters will all be printed out.

(6) Cassette interface test (in BASIC mode)

Input a suitable program, save it on cassette (by CSAVE "file name"), and then read out the
saved program (by CLOAD "file name") and check it.

(7) RS-232C and MODEM tests.

Prepare two units and make the tests while referring to the section on communications in the

Operation Manual.

á

VI. EXPLODED VIEW/PARTS LIST

Exploded View

4

1-1-2

1

V

2

0

t - 6

13

,11

3-1-3

11

8

c\

12

Figure 6-1. Exploded View

3-1-2

3-1-1

3-1-4

16

1-1-3

6-1

Electrical Parts List

Main PCB Assembly

Ref. No.

-7

T--

Description

RS Part No.

Mfr's Part No.

CAPACITORS

Cl-C4

Ceramic 0.047,uF/50V/+80-20%

CD-473ZJCP

CFPD473ZF%

C5-Cll

Ceramic O.1pF/25V/+80-20%

CD-104ZFCP CFPC104ZF%

C12-C16

Ceramic 0.047 juF/50V/+80-20% CD-473ZJCP

CFPD473ZF%

C17,C18

Ceramic 20pF/50V/±10% CD-200KJCP

CFPD200KP%

C19

Ceramic 0.047,uF/50V/+80-20% CD-473ZJCP CFPD473ZF%

C20-C27

Ceramic 82pF/50V/±10%

CD-820KJCP

CFPD820KO%

C28

Ceramic 0.0474F/50V/+80-20%

CD-473ZJCP CFPD473ZF%

C29,C30

Ceramic lOpF/50V/±0.5%

CFPD100DC%

C31

Ceramic 0.1pF/25V/+80-20% CD-104ZFCP

CFPC104ZF%

C32-C35

Ceramic 0.047pF/50V/+80-20%

CD-473ZJCP CFPD473ZF%

C36

Ceramic O.1pF/50V/±10%

CD-104KJCP

CFPD104ZF%

C37

Ceramic 0.1µF'/25V/+80%-20% CD-104ZFCP CFPC104ZF%

C38

Ceramic 100pF/50V/±10%

CD-101KJCP CFPD101KO%

C39

Ceramic 0.0474F/50V/+80-20% CD-473ZJCP CFPD473ZF%

C40

Mylar* 0.047,uF/50V/±5% CC-473JJMP CQMB473JTH

C41-C46

Poly Film 4700pF/100V/±1%

CC-472FLGP

CQPC472FEN

C47,C48

Ceramic 0.1,uF/25V/+80-20% CD-104ZFCP

CFPC104ZF%

C49,C50

Electrolytic 10,uF/16V/±20% CC-106MDAP CEVD100ALX

C51

Ceramic 0.047,uF/50V/+80-20%

CD-473ZJCP

CFPD473ZF%

C52

Electrolytic 1µF/50V/±20%

CC-105MJAP CEVGO10NLX

C53

Ceramic O.l#F'/25V/+80-20% CD-104ZFCP

CFPC104ZF%

C54,C55

Electrolytic lOiF/16V/±20%

CC-106MDAP

CEVD100ALX

C56-C58

Ceramic 0.l F/25V/+80-20%

CD-104ZFCP CFPC104ZF%

C59,C60

Mylar 3300pF/50V/±5%

CC-332JJMP

CQMB332JTH

C61

Mylar 4700pF/50V/±5% CC-472JJMP

CQMB472JTH

C62

Ceramic O.O1,uF/50V/±10%

CD-103KJCP CFPD103KB%

C63

Mylar 0.1µF/50V/±10%

CC-104KJMP

CQMB104KTH

C64

Mylar 0.047µF/50/V/±10% CC-473KJMP

CQMB473KTH

C65-C67

Ceramic 0.047jF'/50V/+80-20%

CD-473ZJCP

CFPD473ZF%

C68,C69

Ceramic 1000pF/50V/±10%

CC-102KJCP

CFPD102KB%

C70

Ceramic O.1juF/25V/+80%-20%

CD-104ZFCP

CFPC104ZF%

C71-C73

Mylar 0.039,uF/50V/±10%

CC-393KJMP

CFPD393KB%

C74

Ceramic 0.047 ,4F'/50V/+80-20%

CD-473ZJCP

CFPD473ZF%

C75-C77

Electrolytic 47,uF/16V/±20%

CC-476MDAP CEVD470NLX

C78

Electrolytic 3.3,uF/50V/+75%-10%

CC-335XJAP

CEVG3R3ALX

C79,C80

Ceramic 0.047uF/50V/+80-20%

CD-473ZJCP CFPD473ZF%

C81

Ceramic 1000pF/50V/±10%

CC-102KJCP

CFPD102KB%

C82

Electrolytic 4.71F/25V/±20%

CC-475MFAP CEVE4R7ALX

C83

Electrolytic 470,uF//16V/1-30-10%

CC-477RCAP

CEVD471UMN

C84

Electrolytic 470,uF/6.3V/+30%-10%

CC-477BBAP CEVB471ALN

C85

Electrolytic 33pF/10V/±20%

CC-336MCAP

CEVC330ALX

C86

Electrolytic 100,uF/6.3V/±20%

CC-107MBAP CEVB101ALX

C87

Ceramic 0.luF'/25V/+80-20%

CD-104ZFCP

CFPC104ZF%

C88-C89

Not used

C90

Electrolytic 1,uF/50V/±20% CC-105MJAP

CEVG010ALX

C91

Ceramic 0.047aF/50V/+80-20%

CD-473ZJCP

CFPD473ZF%

C92

Electrolytic 0.047,uF/50V/±20% CC-474MJAP

CEVGR47ALX

C93

Not used

C94

Ceramic 1000pF/50V/±10%

CC-102KJCP

CFPD102KB%

C95,C96

Not used

C97,C98

Ceramic 1000pF/50V/±10%

CC-102KJCP

CFPD102KB%

C99

Ceramic 0.047µF/50V/+80-20%

CD-473ZJCP CFPD473ZF%

C100

Ceramic 2200pF/50V/±10%

CD-222KJCP

CFPD222KB%

C101

Not used

C102

Ceramic

lOOpF/50V/±10% CD-101KJCP CFPD101KO%

C103

Electrolytic 221pF/1OV/±20%

CC-227MCAP

CEVC221ACX

* Mylar is a registered trademark of E. I. Du Pont de Nemours and Company.

6-2

Ref. No.

Description

RS Part No.

Mfr's Part No.

C104

Ceramic

O.Ol µF/50V/±1O%

CD-103KJCP

CFPD103KB%

C107

Ceramic

270pF/50V/±10%

CD-271KJCP

CFPD271KO%

C108

Mylar

5600pF/50V/±10%

CC-562KJMP

CQMB562KTH

C109

Ceramic

68pF/50V/±10%

CD-680KJCP

CFPD680KO%

C110

Ceramic

1000pF/50V/±10%

CC-102KJCP

CFPD102KB%

C111

Ceramic

3300pF/50V/±10%

CD-332KJCP

CFPD332KB%

CONNECTORS

CN1

Jack, Junction

to Keyboard

AJ-0010

YJF18SO16Z

CN2

Jack, Junction

to BCR

AJ-7342 YJF09SO39Z

CN3

Jack, Junction

to CMT

AJ-7340

YJF08SO33Z

CN4

Jack, Junction

to MODEM

AJ-7341

YJF08SO34Z

CN5

Jack, Junction

to Printer

AJ-7345

YJF26SOlOZ

CN6

Jack, Junction

to RS-232C

AJ-7344 YJF25SO19Z

CN7

Jack, Junction

to LCD

AJ-0013 YJF30SO12Z

CN8

Jack, Junction

to System Bus

AJ-7634 YJF40SO15Z

CN9

Jack, Junction

to AC Adapter

AJ-7627

YJB03SO07Z

DIODES AND SURGE ABSORBERS

D1,D2

Diode, Silicon

1S2076

ADX-1763

QDSS2076#B

D3

Not used

D4

Diode, Zener

RD4.3EL3

DX-0064 QDZ4R3ELCA

D5-D12

Diode, Silicon

1S2076

ADX-1763

QDSS2076#B

D13

Diode, Silicon HRP22

QDSHRP22XB

D14

Diode, Zener RD5.1EL1

DX-0065

QDZ5RIELAA

D15-D17

Diode, Silicon

1S2076

ADX-1763

QDSS2076#B

D18

Surge Absorber

ERZ-CIODK361

ADX-1864 QNHDK361AN

D19

Not used

D20-D22

Diode, Silicon

1S2076

ADX-1763 QDSS2076#B

D23

Diode, Silicon

HRP22

QDSHRP22XB

D24

Surge Absorber ERZ-C10K220 ADX-1863 QNDDK220AN

D25,D26 Not used
D27

Surge Absorber SNR-7D18L ADX-1862 QNB7D18LAD

D28,D29

Diode, Silicon

1S2076

ADX-1763

QDSS2076#B

COILS

Ll,L2

Choke

10µH/500mmA/Axial ACA-8286

LF10OKE04Y

L3,L4 RF (with beeds)

B-O1AT

LBPDG5205A

INTEGRATED CIRCUITS

Ml

Hi-speed C-MOS,

Latch

TC40H373F

MX-2209 QQF40373TT

M2 Hi-speed C-MOS,

Buffer

TC40H245F

MX-2207

QQF40245TT

M3,M4

Hi-speed C-MOS, Buffer

TC40H367F

MX-2208

QQF40367TT

M5

Hi-speed C-MOS,

Decoder

TC40H139F

MX-2204

QQF40139TT

M7-M9

C-MOS, RAM PPD4364C or

MX-2210

QQOD4364AA

TC5565PL-15

QQ005565AT

MiO

Hi-speed C-MOS, Buffer

TC40H367F

MX-2208 QQF40367TT

M12

C-MOS, Masked ROM

HN613256PD-91

MX-2213

QQ061325QB

M13

Hi-speed C-MOS,

OR Gate

TC40HO32F

MX-2202 QQF40032TT

M14

Hi-speed C-MOS,

FF

TC40H175F

MX-2206

QQF40175TT

M15

Hi-speed C-MOS,

Buffer

TC40H367F

MX-2208 QQF40367TT

M16

Hi-speed C-MOS,

Decoder

TC40Hl38F

MX-2203 QQF40138TT

M17

Hi-speed C-MOS,

NAND

TC40H000F

MX-2201

QQF40000TT

M18

Hi-speed C-MOS,

Timer

D1990AC

AMX-5801

QQ001990BA

M19

C-MOS, CPU MSM80C85ARS

AMX-5806 QQ008085A5

M20,M21 Hi-speed C-MOS,

Buffer

TC40H367F

MX-2208 QQF40367TT

M22

C-MOS, UART

D3-6402-9

AMX-5805

QQ006402AZ

6-3

Ref. No.

Description RS Part No. Mfr's Part No.

M23

Hi-speed C-MOS, Buffer TC40H367F

MX-2208 QQF40367TT

M24

C-MOS, Schmitt Trigger TC4584BF MX-2200 QQF04584TT

M25

C-MOS, PIO MSM81C55RS

MX-5577 QQ008155A5

M26

Hi-speed C-MOS, OR Gate TC40H032F

MX-2202 QQF40032TT

M27

C-MOS, NAND Gate TC4011BF

MX-2183

QQF04011UT

M28

C-MOS, Flip-Flop TC4013BF

MX-2184 QQF04013UT

M29,M30

Bipolar, OP-Amp TL064CN

AMX-5800

QQM00064AU

M31

C-MOS, MODEM MC14412VP

AMX-5808

QQ014412AM

M32

Hi-speed C-MOS, Buffer TC40H367F

MX-2208 QQF40367TT

M33

Hi-speed C-MOS, Selector TC40H157F

MX-2205

QQF40157TT

M34,M35

C-MOS, Schmitt Trigger TC4584BF

MX-2200 QQF04584TT

M36

C-MOS, Flip-Flop TC4013BF

MX-2184

QQF04013UT

M37

Hi-speed C-MOS, NAND TC40H000F

MX-2201 QQF40000TT

M38

Hi-speed C-MOS, NOR Gate TC40H002F

QQF40002TT

M39 Hi-speed C-MOS, Buffer TC40H245F

MX-2207

QQF40245TT

M40

Hi-speed C-MOS, Buffer TC40H244F

QQF40244TT

M41,M42

Hi-speed C-MOS, Buffer TC40H367F

MX-2208

QQF40367TT

M43

Hi-speed C-MOS, AND Gate TC40H011F

QQF40011TT

TRANSFORMERS

OT1

Transformer, MODEM

ATB-0472

TDZ19A002K

OT2

Transformer, Converter

ATA-0001

TCA9RZO413

RESISTORS

R1

Chip 1k/l/8W/±5%

ND-0196EBM

RJ8APJ102%

R2-R7

Chip 33k/l/8W/±5%

ND-0324EBM RJ8APJ333%

R8

Chip 1k/1/8W/±5%

ND-0196EBM

RJ8APJ102%

R9

Not used

RIO-R12 Chip 1k/1/8W/t5%

ND-0196EBM

RJ8APJ102%

R13

Metal Film 806ohm/1/4W/±i%

N-0577BEE RQBXF8060X

R14

Chip lOk/l/8W/±5%

ND-281EBM

RJ8APJ103%

R15

Metal Film 33.2k/l/4W/±l%

N-0622BEE

RQBXF3322X

R16

Metal Film 2.05k/l/4W/±l%

N-0716BEE RQBXF2051X

R17

Metal Film 73.2k/l/4W/±i%

N-0612BEE RQBXF7322X

R18

Metal Film 590k/l/4W/±l%

N-0615BEE RQBXF5903X

R19

Chip 15k/l/8W/±5%

ND-0297EBM

RJ8APJ153%

R20

Chip 470k/1/8W/±5%

ND-0423EBM

RJ8APJ474%

R21

Chip 620ohm/l/8W/±5%

ND-0181EBM RJ8APJ621%

R22

Chip 390ohm/l/8W/±5%

ND-0162EBM

RJ8APJ391%

R23

Chip l0k/l/8W/±5%

ND-0281EBM

RJ8APJ103%

R24

Metal Film 665ohm/1/4W/±l%

N-0765BEE RQBXF6650X

R25

Metal Film 1.5k/l/4W/±l%

N-0206BEE

RQBXF1501X

R26

Chip lOk/1/8W/±5%

ND-0281EBM RJ8APJ103%

R27

Metal Film 1.3k/l/4W/±i%

N-0202BEE

RQBXF1301X

R28

Metal Film 3.3k/l/4W/±l%

N-0230BEE

RQBXF3301X

R29

Metal Film 280k/l/4W/±l%

N-0672BEE

RQBXF2803X

R30 Metal Film 422k/1/4W/±l%

N-0419BEE RQBXF4223X

R31 Chip 2.2k/l/8W/±5%

ND-0216EBM RJ8APJ222%

R32 Chip 22ohm/l/8W/±5%

ND-0078EBM

RJ8APJ220%

R33 Chip lOk/l/8W/±5%

ND-0281EBM

RJ8APJ103%

R34 Chip lk/l/8W/±5%

ND-0196EBM RJ8APJ102%

R35 Chip lOk/l/8W/±5%

ND-0281EBM

RJ8APJ103%

R36 Chip 680ohm/l/8W/±5%

ND-0183EBM RJ8APJ681%

R37 Chip 180k/l/8W/±5%

ND-0387EBM

RJ8APJ184%

R38

Metal Film 52.3k/l/4W/±l%

N-0613BEE

RQBXF5232X

R39

Chip lk/l/8W/±5%

ND-0196EBM

RJ8APJ102%

R40,R41 Chip lOk/l/8W/±5%

ND-0281EBM

RJ8APJ103%

R42

Metal Film 2.3k/l/4W/±l%

N-0218BEE

RQBXF2301X

6-4

Ref. No. Description RS Part No.

Mfr's Part No.

R43

Metal Film lOk/l/4W/tl%

N-0281BEE RQBXF1002X

R44 Metal Film 242k/l/4W/±1%

N-0558BEE

RQBXF2423X

R45

Metal Film 7.97k/l/4W/±l%

N-0769BEE RQBXF7971X

R46 Chip 33k/l/8W/±5%

ND-0324EBM RJ8APJ333%

R47

Carbon 15M/l/4W/±5%

N-0486EEC

RD25PJ156X

R48

Chip 68k/1/8W/±5%

ND-0354EBM

RJ8APJ683%

R49,R50

Chip 3.3k/l/8W/±5%

ND-0230EBM RJ8APJ332%

R51

Chip 2.2k/l/8W/±5%

ND-0216EBM RJ8APJ222%

R52 Chip lk/l/8W/±5%

ND-0196EBM RJ8APJ102%

R53

Chip lOOk/l/8W/±5%

ND-0371EBM

RJ8APJ104%

R54

Chip 12k/l/8W/±5%

ND-0288EBM

RJ8APJ123%

R55 Chip 3.3k/1/8W/±5%

ND-0230EBM

RJ8APJ332%

R56 Chip lOk/l/8W/±5%

ND-0281EBM RJ8APJ103%

R57

Not used

R58-R62 Chip 33k/l/8W/±5%

ND-0324EBM

RJ8APJ333%

R63

Chip 620ohm/l/8W/±5%

ND-0181EBM

RJ8APJ621%

R64-R66

Chip 33k/l/8W/±5%

ND-0324EBM

RJ8APJ333%

R67 Not used
R68 Chip 33k/l/8W/±5%

ND-0324EBM RJ8APJ333%

R69

Not used

R70-R74 Chip 33k/l/8W/±5%

ND-0324EBM RJ8APJ333%

R75 Chip lOOk/l/8W/±5%

ND-0371EBM

RJ8APJ104%

R76,R77 Chip 33k/l/8W/±5%

ND-0324EBM RJ8APJ333%

R78 Chip lOOk/l/8W/±5%

ND-0371EBM

RJ8APJ104%

R79,R80

Chip 33k/l/8W/±5%

ND-0324EBM

RJ8APJ333%

R81 Chip 1OOk/1/8W/±5%

ND-0371EBM

RJ8APJ104%

R82

Chip 33k/1/8W/±5%

ND-0324EBM

RJ8APJ333%

R83 Chip 22k/1/8W/±5%

ND-0311EBM

RJ8APJ223%

R84 Chip 33k/l/8W/±5%

ND-0324EBM RJ8APJ333%

R85 Chip lOk/l/8W/±5%

ND-0281EBM

RJ8APJ103%

R86

Chip 33k/l/8W/±5%

ND-0324EBM

RJ8APJ333%

R87-R89

Chip 6.2k/1/8W/±5%

ND-0260EBM RJ8APJ622%

R90

Chip 15k/l/8W/±5%

ND-0297EBM RJ8APJ153%

R91

Chip 330ohm/l/8W/±5%

ND-0159EBM RJ8APJ331%

R92

Chip 18k/l/8W/±5%

ND-0303EBM RJ8APJ183%

R93

Chip 68k/1/8W/±5%

ND-0354EBM

RJ8APJ683%

R94

Chip 330ohm/l/8W/±5% ND-0159EBM RJ8APJ331%

R95

Chip 100ohm/l/8W/}5%

ND-0132EBM RJ8APJ101%

R96

Chip 18k/l/8W/±5%

ND-0303EBM

RJ8APJ183%

R97

Chip 180ohm/l/8W/±5%

ND-0144EBM

RJ8APJ181%

R98

Chip 18k/l/8W/±5%

ND-0303EBM RJ8APJ183%

R99

Chip 330ohm/l/8W/±5% ND-0159EBM

RJ8APJ331%

R100

Not used

R101

Chip 1.8k/l/8W/±5%

ND-0210EBM RJ8APJ182%

R102

Chip 82k/l/8W/±5%

ND-0360EBM

RJBAPJ823%

R103

Chip lOk/l/8W/±5%

ND-0281EBM

RJ8APJ103%

R104

Chip 56k/l/8W/±5%

ND-0345EBM

RJ8APJ563%

R105

Metal Film 2.7k/l/4W/±l%

N-0224BEE

RQBXF2701X

R106 Chip 150k/l/8W/±5%

ND-0384EBM

RJ8APJ154%

R107

Chip

47k/1/4W/±5%

ND-0340EBM RJ8APJ473%

R108

Metal Film 22.6k/l/4W/±l%

N-0729BEE RQBXF2262X

R109

Chip 56k/l/8W/±5%

ND-0345EBM

RJ8APJ563%

R110,R1l

l Chip 150k/l/8W/±5%

ND-0384EBM

RJ8APJ154%

R112

Chip 1.8k/l/8W/±5%

ND-021OEBM

RJ8APJ182%

R113 Chip 3.3k/l/8W/±5%

ND-0230EBM

RJ8APJ332%

R114 Chip 33k/l/8W/±5%

ND-0324EBM

RJ8APJ333%

R115 Chip

lOOk/l/8W/±5%

ND-0371EBM

RJ8APJ104%

R116

Metal Film 150k/l/4W/±l%

N-0384BEE

RQBXF1503X

6-5

Ref. No.

Description

RS Part No.

Mfr's Part No.

R117,R118 Chip l00k/1/8W/±5%

ND-0371EBM

RJ8APJ104%

R119

Chip 33k/1/8W/±5%

ND-0324EBM

RJ8APJ333%

R120 Chip 82k/1/8W/±5%

ND-0360EBM

RJ8APJ823%

R121

Chip 820ohm/1/8W/±5%

ND-0187EBM

RJ8APJ821%

R122

Chip 470ohm/1/8W/±5%

ND-0169EBM

RJ8APJ471%

R123

Chip 1.8k/1/8W/±5%

ND-0210EBM

RJ8APJ182%

R124,R125 Chip lOk/1/8W/±5%

ND-0281EBM

RJ8APJ103%

R126 Chip 270ohm/1/8W/±5%

ND-0155EBM

RJ8APJ271%

R127 Chip 22k/1/8W/±5%

ND-0311EBM

RJ8APJ223%

R128 Chip l00k/1/8W/±5%

ND-0371EBM

RJ8APJ104%
R129-R130 Not used
R131 Chip lk/l/8W/±5%

ND-0196EBM

RJ8APJ102%
R132 Chip 150k/l/8W/±5%

ND-0384EBM

RJ8APJ154%

R133 Not used
R134 Chip 3.3k/l/8W/±5%

ND-0230EBM

RJ8APJ332%

R135,R136 Chip 68k/l/8W/±5%

ND-0354EBM

RJ8APJ683%
R137-R139 Chip lOOk/l/8W/±5%

ND-0371EBM

RJ8APJ104%

R140 Chip lOk/l/8W/±5% ND-0281EBM

RJ8APJ103%
R141 Chip 1M/l/8W/±5%

ND-044 5EBM

RJ8APJ105%
R142 Chip 33k/l/8W/±5%

ND-0324EBM

RJ8APJ333%
R143 Not used
R144,R145 Chip 15k/l/8W/±5%

ND-0297EBM RJ8APJ153%

R146 Chip 33k/l/8W/±5%

ND-0324EBM

RJ8APJ333%

R147,R148 Not used
R149 Chip 56k/l/8W/±5%

ND-0345EBM RJ8APJ563%

R150 Chip 470ohm/l/8W/±5%

ND-0169EBM RJ8APJ471%

R151 Chip 33k/1/8W/±5%

ND-0324EBM

RJ8APJ333%
R152 Chip lOk/l/8W/±5%

ND-0281EBM RJ8APJ103%

R153 Chip 33k/l/8W/±5%

ND-0324EBM

RJ8APJ333%

R154 Chip lOk/l/8W/±5%

ND-0281EBM

RJ8APJ103%

R155 Not used
R156 Chip lOOk/l/8W/±5%

ND-0371EBM

RJ8APJ104%
R157 Chip 33k/l/8W/±5%

ND-0324EBM

RJ8APJ333%

R158-R160 Chip lOOk/l/8W/±5%

ND-0371EBM

RJ8APJ104%

R161 Chip lOk/l/8W/±5%

ND-0281EBM

RJ8APJ103%

R162 Chip 100ohm/l/8W/±5%

ND-0132EBM RJ8APJ101%

R163-R170 Chip 33k/l/8W/±5%

ND-0324EBM

RJ8APJ333%

R171 Cement 39 ohm/3W

RF03SJ390B

R172 Chip 33k/l/8W/±5%

ND-0324EBM

RJ8APJ333%

RESISTOR ARRAYS

MR1,MR2

Not used

MR3

Resistor, Array 33kX8/1/8W/±20%

ARX-0345

RAB333MO8X

MR4

Not used

MR5

Resistor, Array lOOkX8/1/8W/±20%

ARX-0344

RAB104M08X

RELAYS

RY1

FBR211CD005-M

AR-8160

ZRA265101Z

RY2

FRL-764D05/1AS-T

AR-8159

ZRA164102Z

RY3

MZ-5HS-FC

AR-8001

ZRA161301Z

SWITCHES

SW1

Slide, SLD-22-456

AS-0004

SS020270ZZ

SW2

Slide, ST-011-01 AS-0006

SSO40217ZZ

SW3

Slide, SLBT22BP-07

AS-0005

SS020271ZL

SW4

Push, SPJ 312U, without Knob

AS-7573

SPOlABA06A

SW5

Slide, SLD-22-456

AS-0004

SS020270ZZ

6-6

Ref. No.

Description

RS Part No.

Mfr's Part No.

TRANSISTORS

Ti

Silicon, 2SA1162,

PNP, SY or SG

MX-6469

QUA1162XDP

T2-T7

Silicon, 2SC3052,

NPN, No-Rank

2SC-2712Y

QUC3052XCP

T8

Not used

T9-Til

Silicon, 2SC3052,

NPN,

No-Rank

2SC-2712Y QUC3052XCP

T12

Not used

T13-T17 Silicon, 2SC2712, NPN,

LG

2SC-2712 QUC2712XCP

T18

Silicon, 2SC3052,

NPN, No-Rank

2SC-2712Y QUC3052XCP

T19

Silicon, 2SA1162, PNP, SY or SG

MX-6469

QUA1162XDP

T20 Silicon, 2SC3052,

NPN, No-Rank

2SC-2712Y QUC3052XCP

T21 Silicon, 2SC1384, NPN,

S-Rank

2SC-1384

QTC1384XHN

T22 Silicon, 2SC2712,

NPN,

LG

2SC-2712 QUC2712XCP

T23-T25 Silicon, 2SC3052,

NPN,

No-Rank

2SC-2712Y

QUC3052XCP

T26

Not used

T27

Silicon, 2SC3052,

NPN,

No-Rank

2SC-2712Y

QUC3052XCP

T28 Silicon, 2SA1162,

PNP, SY or SG

MX-6469 QUA1162XDP

THERMISTORS

TH1,TH2

10k ohm/t5%, TD5-C310D1H

AT-1235

QHQ5C31HZP

VARIABLE RESISTORS

VR1

50k B-curve, Contrast

AP-7424 RPSNB50306

VR2

Semi-fixed, 50k B-curve, MODEM

AP-7336

RPSNB50303

CRYSTAL OSCILLATORS

X1

32.768 kHz for Clock

MX-2170

XTR1A1001%

X2

4.9152 MHz for CPU Clock

AMX-1010

XBR1A1003X

X3

HC43U/1MHz for Modem

AMX-1009 XAZ1C2001X

6-7

LCD PCB Assembly

Ref. No.

Description RS Part No.

Mfr's Part No.

CAPACITORS

C1-C4

Ceramic 0.1 AF/25V/+80-20% CD-104ZFPC

CFPC104ZF%

C5

Ceramic 18pF/25V/±1O% CD-180KFCX

CFTC180KC%

C6-C10

Ceramic O.luF25V/+80-20%

CD-104ZFPC

CFPC104ZF%

C11-C20

Ceramic 1000pF/25V/+80-20%

CD-102ZFCX

CFPC102ZF%

CONNECTOR

CN1 Jack, Junction to Main PCB

T

[3OSO12Z

INTEGR

ATED CIRCUITS

M1-M5

C-MOS Driver HD44102CRH

MX-2169 QQ044102CB

M6-M10 C-MOS Driver HD44102CH

AMX-5797

QQ044102BB

M11,M12

C-MOS Driver HD44103BLD

AMX-5798 QQ044103BB

M13

C-MOS OP-Amp LA6324 AMX-5796

QQF06324AC

LED

LED

SLP-135B AL-1458

QLlSP135BC

RESISTORS

R1,R2 Chip 10k ohm/1/8W±2%

ND-0281CBM

RJ8APG103%

R3

Chip 26.5k ohm/1/8W±2%

ND-0271CBM RJ8APGA52%

R4,R5

Chip 10k ohm/1/8W±2%

ND-0281CBM

RJ8APG103%

R6-R10

Chip 100k ohm/1/8W±5%

ND-0371EBM RJ8APJ104%

R11

Chip 18 ohm/1/8W±5%

ND-0144EBM

RJ8APJ18O%

R12-R16

Chip 150 ohm/1/8W±5%

ND-0142EBM RJ8APJ151%

6-8

Keyboard Assembly

Ref. No.

Description

RS Part No.

Mfr's Part No.

1-1 Keyboard Kit

AGX1000*02

1-1-1

Spring - SPACE Key

ARB-7737

MW261LJO19

1-1-2

Guide - ENTER Key

AHC-3111

MX422LJ003

1-1-3 Guide - SPACE Key

AHC-3112

MX722LJ002

1-1-4

Lever Guide - ENTER and SPACE Key

AHC-3113

VK112SB001

1-1-5 Lever Stopper - ENTER and SPACE Key

AHC-3114

VK113SH001

1-1-6 Key Guide Pin - SPACE Key

AHC-3115

VM253SH001

1-1-7

Key Guide - SPACE Key

AHC-3116

VM276SB001

1-2 Keytop Kit

AG102***02

1-2-1 Keytop - TACT

AK-5651

VK121SBOO7

1-2-2

Keytop - 1

AK-5206

VK122SBOO4

1-2-3 Keytop - 2

AK-5207

VK122SBOO5

1-2-4 Keytop - 3

AK-5208

VK122SBOO6

1-2-5

Keytop - 4

AK-5209

VK122SBOO7

1-2-6

Keytop - 5

AK-5210

VK122SBOO8

1-2-7 Keytop - 6

AK-5211

VK122SBOO9

1-2-8

Keytop - 7

AK-5212

VK122SBOIO

1-2-9

Keytop - 8

AK-5213

VK122SB011

1-2-10

Keytop - 9

AK-5214

VK122SBO12

1-2-11

Keytop - 0

AK-5215

VK122SBO13

1-2-12

Keytop - A

AK-5216

VK122SBO14

1-2-13

Keytop - B

AK-5217

VK122SBO15

1-2-14

Keytop - C

AK-5218

VK122SBO16

1-2-15

Keytop - D

AK-5219 VK122SB017

1-2-16

Keytop - E

AK-5220

VK122SBO18

1-2-17 Keytop - F

AK-5221

VK122SBO19

1-2-18

Keytop - G

AK-5222

VK122SB020

1-2-19

Keytop - H

AK-5223

VK122SBO21

1-2-20

Keytop - I

AK-5224 VK122SB022

1-2-21

Keytop - J

AK-5225 VK122SB023

1-2-22

Keytop - G

AK-5226 VK122SB024

1-2-23

Keytop - L

AK-5227

VK122SB025

1-2-24

Keytop - M

AK-5228

VK122SB026

1-2-25

Keytop - N

AK-5229

VK122SB027

1-2-26

Keytop - 0

AK-5230

VK122SB028

1-2-27

Keytop - P

AK-5231

VK122SB029

1-2-28

Keytop - Q

AK-5232

VK122SB030

1-2-29

Keytop - R

AK-5233

VK122SBO31

1-2-30

Keytop - S

AK-5234

VK122SB032

1-2-31

Keytop - T

AK-5235

VK122SB033

1-2-32

Keytop - U

AK-5236 VK122SB034

1-2-33

Keytop - V

AK-5237

VK122SB035

1-2-34

Keytop - W

AK-5238

VK122SB036

1-2-35

Keytop - X

AK-5239

VK122SB037

1-2-36

Keytop - Y

AK-5240 VK122SB038

1-2-37

Keytop - Z

AK-5241 VK122SB039

1-2-38

Keytop - ESC

AK-5242

VK122SB040

1-2-39

Keytop - MINUS

AK-5243

VK122SBO41

1-2-40 Keytop - PLUS

AK-5244

VK122SB042

1-2-41 Keytop - DEL

AK-5245

VK122SB043

1-2-42

Keytop - BRACKET

AK-5246

VK122SB044

1-2-43

Keytop - ;

AK-5247

VK122SB045

1-2-44 Keytop - QUOTATION

AK-5248

VK122SB046

1-2-45

Keytop - CAPSL

AK-5249

VK122SB047

1-2-46 Keytop - COMMA

AK-5250

VK122SB048

1-2-47

Keytop - PERIOD

AK-5251

VK122SB049

1-2-48

Keytop - / AK-5252 VK122SB050

1-2-49

Keytop - GRPH

AK-5253

VK122SBO51

6-9

Ref. No.

Description

RS Part No.

Mfr's Part No.

1-2-50

Keytop - CODE

AK-5254

VK122SB052

1-2-51

Keytop - NUM

AK-5255

VK122SB053

1-2-52

Keytop - TAB

AK-5256

VK132SBOO6

1-2-53

Keytop - CTRL

AK-5257

VK132SBOO7

1-2-54

Keytop - SHIFT

AK-5654

VK132SBOO8

1-2-55

Keytop - ENTER

AK-5655 VK142SB003

1-2-56

Keytop - SPACE

AK-5261

VK172SBOO2

1-3

Diode, Silicon, 1S2076

ADX-1763

QDSS2076#B

1-4

Switch, Key - Tact

AS-2910

SK0101X22T

1-5

Switch, Key - Lock

AS-2886

SKO111X08A

1-6

Switch, Key - Push

AS-2911

SKO111X12A

1-7

Insulator

VS873YBOOJ

1-8

Cushion

VS875YB002

1-9

Jack, Junction to Main PCB

AJ-0010

YJF18SO16Z

6-10

Mechanical and Assembly Parts List

Ref. No.

Description

RS Part No.

Mfr's Part No.

1

Keyboard Assembly

AXX-0238

AFY102***1

2

LCD PCB Assembly

AX-4001

APLX142AAQ

2-1

Frame, LCD MB861SF002

2-3

Connector, LCD SG type

AJ-7321

VQ811RX00I

2-5

LCD, LR202-C

AL1459

ZXLR202CXB

3

Main PCB Assembly

AX-4002

APLX144AAQ

3-1

Case Assembly, Battery

AZ-0010

AM102***03

3-1-1

Battery Terminal, Plus MW161SN001

3-1-2

Battery Terminal, Minus MW161SNOO2

3-1-3

Battery Terminal, Rear

MW261LJ009

3-1-4

Battery Terminal, Front

MW261LJ010

3-1-5

Case, Battery, Black

VB662SB003

3-2

Knob, Contrast, Black

AK-5657

VF187SB003

3-3

Knob, RESET, Black

AK-5265

VK121SB004

3-4

Flat Cable, For Keyboard, 18 Lines

AW-0006

WC18140AD1

3-5

Flat Cable, For LCD, 30 Lines

AW-0007

WC30150BD1

3-6

IC Socket, 28-pin, DICF-28CS

AJ-7349

YSC28S005Z

3-7

IC Socket, 28-pin, 5500-28A

AJ-7637 YSC28S007Z

3-8

Battery, Nickel-Cadmium, 3-51FT

ACS-0100

ZBN036102Y

3-9

Buzzer, KBS-27DB-3T

ZYED10006%

4 Case Assembly, Top, Ivory

AZ-0011 AM102***01

4-1

Case, Top, Ivory

VB883SH004

4-2

Filter

VS868AC005

4-3

Plate, Model

VVM102***2

5

Case Assembly, Bottom, Black

AZ-0012

AM102***02

5-1

Foot, Rubber

##P4157***

5-2

Case, Bottom, Black

VB883SB012

6

Screw, Cup Head, Sems, Machine, M3X8, S-ZNCR

AHD-1865

BSP43008NZ

7

Plate, Name

KLX1****Ol

8

Label, FCC (USA Version Only)

KL000355XX

9

Plate, Serial Number

MVS102***1

10

Cap, BCR Connector Cover

AHC-2235 VE32JPBOO1

11

Cover, Knob

AHC-0012

VN230SBOO7

12

Cover, ROM

AHC-0013

VS667SB004

13

Cover, Battery

AHC-0014

VS668SB004

14

Cap, Printer Connector Cover

ART-5559 VU521SB00l

15

Cap. System Bus Connector Cover

AHC-0016

VU611SB0O1

16

Plate, Fiber

VS875FB003

17

Nut, M2.6, Thin Type, S-ZNCR

BNHCL26NSZ

18

Screw, Pan Head, Machine, M3X8, S-ZNCR

BSPC3008NZ

19

Screw, Pan Head, Machine, M2.6X12, S-ZNCR

BSPP2612NZ

20

Screw, Cup Head, Machine, M1.7X3, S-BLACK

BSP21703NB

21

Screw, Pan Head, Tapping, M3X8, S-ZNCR

BTPP3008PZ

Hardware Kit

AHW- AYXM102*01

4 Screws, Pan Head, Tapping, M3X10, S-ZNCR

2603803

Pouch

AZ-0013 AM102***04

6-11

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C$$W .. MIC 0000000

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Figure 7-2. LCD PCB - Schematic Diagram

D

a

a

0

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0

0

p0
an

5. >>

a

x

240 x 64 Full Dot LCD

)/32 duty 6 bias

< LR 202-C>

Can

32 ... 11 240 l

ELCorn2240

Beg Coq

I I N IS

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a

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PCB Views

R156

W77

M34

4013

111-101667

CO

rF M I

__-

R68

M43 4

M231

1 3&7

4011

Figure 7-3. Main PCB - Top View

M37

pv15

40H245

(I ,40 H373 40H367.

M32

4584

7-3

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OMS

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Figure 7-4. Main PCB - Bottom View

7-4

90085

zzN

690 M

34

1 33

i

mil

23

22

80

M5

M4

24

M3

24

2

25

80

I 25 80

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1 25 80

M2

R13 R14

C1

65 40 65 40

65 40 65

6 64

R12

64 1

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R#I HO N HO N HD

N

HO

C2

44102 TO

U 44102

a

0

44102 44102

U U U

18

G20

019

64

M7

64

ml0

64

M8

41

64

41

64

M9

41

c LED

65 40 65

40 65 40 65

HO 4102 HD I H 1 2 HD4 1 2

80,

2425

80

25

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25

24 0 24

80,

24

25 8

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64

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C17

41

40

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444102

64

M6

65

25

24

80

HD441 2

25

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41

C16 33

41

40

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M12

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23

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á

APPENDIX A /INSTALLATION

Installation of Optional RAM and ROM

• Using a coin, remove the RAM and ROM cover on the bottom case.

• Insert the optional RAM into the IC socket marked M6.

• Insert the optional ROM into the IC socket marked M11.

-CP

Optional RAM

a

4

Optional ROM

Figure A-1. Installation of RAM and ROM

á

APPENDIX B/KEYBOARD LAYOUT,

CONNECTOR PIN ASSIGNMENTS AND
CHARACTER CODE TABLE

B-1. Keyboard Layout

TANDY

102

PORTABLE

COMPUTER

OO LAIN MrTm

BREAK

00 O1OO

PAUSE PASTE LABEL PRINT

11

ESC

FI F2 F3 F4

F5 F6 F7 F8

i

i

A DEL

a

3

6

9®7 8

BK

DDooaoao o-Cf

0

0

l

O

TAB

G

O

O li

I P

I

ENT

a

B

SHIFT

[riIRiii co o o

0

O

CODE

F NUM

Figure &1. Keyboard Layout

B-2. Connector Pin Assignments

B-2-1. System Bus Interface

Pin No.

Symbol

Description

1

VDD

2

VDD

3

GND

4

GND

5

DO Address and data signal bit 0

6

D1

Address and data signal bit 1

7

D2

Address and data signal bit 2

8

D3 Address and data signal bit 3

9

D4 Address and data signal bit 4

10

D5

Address and data signal bit 5

11

D6

Address and data signal bit 6

12

D7 Address and data signal bit 7

13

A8

Address signal bit 8

14

A9

Address signal bit 9

15

AlO

Address signal bit 10

16

All

Address signal bit 11

17

A12

Address signal bit 12

18

A13 Address signal bit 13

19

A14 Address signal bit 14

20

A15

Address signal bit 15

21

GND

22

GND

23

RD

Read enable signal

24

WR

Write enable signal

25

10/M

I/O or memory select signal

26

SO

Status 0 signal

27

ALE

Address latch enable signal

28

Si

Status 1 signal

29

CLK

CLock signal

30

IOCONT

I/O controller select signal

31

E I/O or memory access enable signal

32

RESET Reset signal

33

INTR Interrupt request signal

34

INTA Interrupt acknowledge signal

35

GND

36

GND

37

RAMRST RAM enable signal

38

NC

39

NC

40

NC

Table B-1. System Bus Connector Pin Assignments

2

4

6 8

10

12

14

16 18 20

22 24

26 283032

34

36 38

40

1

3

5 7 9 11

13 15

17

19

21

23

25

27 29

31 33

35 37

39

Figure B-2. System Bus Connector

B-2

B-2-2. RS-232C Interface

Pin No. Symbol

1 GND

2 TXR Transmit Data
3 RXR Receive Data
4 RTS Request to send

5 CTS Clear to send

6 DSR Data set ready

7 GND

8 CD Carrier detect

9 NC

10 NC
11 NC
12 NC
13 NC
14 NC
15 NC
16 NC

17 NC

18 NC
19 NC
20 DTR Data terminal ready
21 NC

22 NC
23 NC
24 NC
25 NC

Description

Table B-2. RS-233C Connector Pin Assignments

000000000000

1325122411

23

10229

21

8

20

7

19618

5174

16315

2

14

1

000000000000

Figure B-3. RS-232C Connector

B-2-3. Printer Interface

Pin No. Symbol

1 STROBE

2 GND
3 PDO
4 GND

5 PD1
6 GND
7 PD2
8 GND

9 PD3

10 GND
11 PD4
12 GND

13 PD5

14 GND
15 PD6
16 GND

17 PD7

18 GND
19 NC

20 GND
21 BUSY
22 GND

23 NC

24 GND

25 BUSY

26 NC

0

25
26

23

24

Description

STROBE Pulse

Bit 0 of Print Data

Bit 1 of Print Data

Bit 2 of Print Data

Bit 3 of Print Data

Bit 4 of Print Data

Bit 5 of Print Data

Bit 6 of Print Data

Bit 7 of Print Data

Busy Signal for Computer

Select Signal

Table B-3. Printer Connector Pin Assignments

0

21

22

0

0

19
20

17

18

0

15
16

0

13
14

0

0

9

10

0

7

8

0

5

6

0

0

3
4

1

2

Figure B-4. Printer Connector

B-2-4. Cassette Interface

Pin No. Symbol

Description

1

REM 1 Remote

2

GND

3

REM 2 Remote

4

R x C

Receive data for CMT

5

T x C

Transmit data for CMT

6

GND

7

NC

8

NC

Figure B-5. Cassette Connector

B-2-5. MODEM Interface

Pin No.

Symbol

Description

1 TL

Conventional Telephone Unit

2

GND

3

R x MD Direct Connection to Tel Line (RING)

4

R x MC

Acoustic Coupler Connection (MIC)

5

Tx MC

Acoustic Coupler Connection (Speaker)

6

VDD

7

Tx MD Direct Connection to Tel Line (TIP)

8

RP Ringing Pulse

Figure B-6. MODEM Connector

B-5

B-2-6. Bar Code Reader Interface

Pin No. Symbol

1 NC

2 RxDB

3 NC
4 NC
5 NC
6 NC
7 GND
8 NC
9 VDD

Description

Receive data from bar code reader

1 2 3 4 5

0 0 0 0 0

0 0 0 0

6 7 8 9

Figure B-7. Bar Code Reader Connector

B-3. Character Code Table

Decimal

Hex

Displayed Keyboard

Binary Decimal

Character Character

Hex

Binary

Displayed Keyboard
Character Character

00

00 00000000 CTRL

25 19

00011001

CTRL

Y

1

01

00000001

CTRL A

26 1A

00011010 CTRL

I

Z

2

02 00000010 CTRL B 27 1B

00011011

ESC

3 03

00000011 CTRL C 28 1C

00011100

4 04

00000100

CTRL

D 29 1D

00011101

5

05

00000101

CTRL

I E 30

1E

00011110

t

6

06

00000110

CTRL

F 31 1F

00011111

7 07

00000111

CTRL

G 32

20

00100000

SPACEBAR

8

08

00001000

CTRL

I

H 33

21

00100001

9

09

00001001

CTRL 1 34

22

00100010

10 OA 00001010

J 35

23

00100011

# #

11 OB

00001011 CTRL

K 36 24

00100100

$

$

12 OC 00001100

CTRL

L 37 25

00100101 ; %

13

OD 00001101 CTRL

M

38 26

00100110

a

&

14 OE

00001110

CTRL

N 39

27

00100111

15

OF

00001111

CTRL 1

0 40 28 00101000

16

10

00010000

CTRL

P 41 29

00101001

)

)

17

11

00010001

CTRL

I Q

42 2A

00101010

'

18

12

00010010

CTRL

R 43

28

00101011

+

+

19

13

00010011

CTRL

S 44

2C

00101100

20

14

00010100 CTRL

T 45 2D

00101101

- --

21

15

00010101

CTRL

U 46

2E

00101110

22

16

00010110

cTRL

V 47

2F

00101111

/ /

23

17

00010111 CTRL

I W

48

30

00110000

0

24

18

00011000

CTRL

X 49 31

00110001

1

Decimal

Hex

Binary

Displayed

Character

Keyboard

Character

Decimal Hex

Binary

Display
Character

Keyboard
Character

50

32 00110010

2

2 75

4B 01001011

K

K

51

33 00110011

3

3 76

4C

01001100

L L

52

34

00110100

4

4

77

4D 01001101

M

M

53

35

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I C

APPENDIX C/TECHNICAL INFORMATION

C-1. 80C85A

General Description

The 80C85A is a complete 8-bit, parallel central processor implemented in silicon gate C-MOS

technology and compatible with 8085A.

It is designed with the same processing speed and lower power consumption compared with

8085A, thereby offering a high level of system integration.

The 80C85A uses a multiplexed address/data bus. The address is split between the 8-bit address
bus and the 8-bit data bus.

INTA RST6,5 TRAP

INTR RST55 RST 75

SIO SOD

INTERRUPT CONTROL SERIAL 1/0 CONTROL

BBIT INTERNAL DATA BUS

PGCUMULATOR T

EMP REG

INSTRUCTION

(8)

(8)

REGISTER (8)

FLAG (5)

FLIP-FLOP

B (8)

C

(8)

REG

REG

ARITHMETIC

LOGIC

INSTRUCTION

DECODER

REG

(8)

REG

E

(8)

UNIT

H 8

L (8)

REGISTER

(ALU)

MACHINE

CYCLE

REG REG

ARRAY

ENCODING

STACK POINTER

(16)

PROGRAM COUNTER

(16)

INCREMENT ER/DECREM ENTER

ADDRESS LATCH (16)

TIMING AND CONTROL

Xi No CLK

RESET

Xz GEN

1

CONTROL STATUS DMA r --,

CLX OUT ( RD Wk ALE So Si IO/MtI HLDA RESET OUT

READY HOLD RESET IN

ADDRESS BUFFER

(8)

DATA/ADDRESS BUFFER(8)

A15-A8

ADDRESS BUS

AD? - ADo

ADDRESS/DATA BUS

Figure C-1. Functional Block Diagram

---r X1 I

10 X2

Nq--- RESET OUT 3

Vcc

HOLD

38 HLDA -

1- SOD

8OC85A

37 CLK(OUT) --

-> SID

36 RESET IN .-^

30

35 READY

.4TRAP

1

-r .

RRST 75 7

ST65

10/p

S1 --

- 0

R

ST55

RD

--

- 0 INTR 1

31 WR -

Q---- N-TA 1

3 ALE

ADo

So

H

AD1 I

28 A15

]No

¢ ADo 14

Ala

--

f ADs 15

Ai3

E--- AD4 16

A12

AD5 I

24 A ii

Mo.

.F ADs

2 Aio

--

.0

ADo 19

GND 20

Ae

2 AB

--

am.

Figure C-2. Pin Configuration of 80C85A

C-1

Functional Pin Description

A8 - Ass (Output, 3-state)

Address Bus: The most significant 8 bits of the memory address or the 8 bits of the I/O address,

3-stated during Hold and Halt modes and during RESET.

ADo - AD7 (Input/Output, 3-state)

Multiplexed Address/Data Bus: Lower 8 bits of the memory address (or I/O address) appear on the
bus during the first clock cycle (T state) of a machine cycle. It then becomes the data bus during

the second and third clock cycles.

ALE (Output)

Address Latch Enable : It occurs during the first clock state of a machine cycle and enables the ad­dress to latched onto the on-chip latch of the peripherals . The falling edge of ALE is set to guaran-

tee setup and hold times for the address information . The falling edge of ALE can also be used to

strobe the status information. ALE is never 3-stated.

So, Si and IO/ M

Machine cycle status:

IO/ M

S1

So States

IO/ M

S1

So

States

0 0

1

Memory write

1 1 1

Interrupt Acknowledge

0

1

0

Memory read 0

0 Halt . = 3-state

1

0

1

I/O write

x

x

Hold (high impedance)

1 1 0 I/O read

x x Reset x= unspecified

0

1

1 Opcode fetch

Si can be used as an advanced R/W status. lO/M, So and S, become valid at the beginning of a ma-

chine cycle and remain stable throughout the cycle. The falling edge of ALE may be used to latch

the state of these lines.

RD (Output, 3-state)

READ control: A low level on RD indicates the selected memory or I/O device is to be read and that

the Data Bus is available for the data transfer, 3-stated during Hold and Halt modes and during RE-

SET.

WR (Output, 3-state)

WRITE control: A low level on WR indicates the data on the Data Bus is to be written into the select­ed memory or I/O location. Data is set up at the trailing edge of WR, 3-stated during Hold and Halt

modes and during RESET.

READY (Input)

If READY is high during a read or write cycle, it indicates that the memory or peripheral is ready to

send or receive data. If READY is low, the CPU will wait an integral number of clock cycles for

READY to go high before completing the read or write cycle. READY must conform to specified set­up and hold times.

HOLD (Input)

HOLD indicates that another master is requesting the use of the address and data buses. The CPU,

upon receiving the hold request, will relinquish the use of the bus as soon as the completion of the

current bus transfer. Internal processing can continue. The processor can regain the bus only after

the HOLD is removed. When the HOLD is acknowledged, the Address, Data, RD, WR, and lO/M

lines are 3-stated.
HLDA (Output)

HOLD ACKNOWLEDGE: Indicates that the CPU has received the HOLD request and that it will re­linquish the bus in the next clock cycle. HLDA goes low after the Hold request is removed. The

CPU takes the bus one half clock cycle after HLDA goes Ica.

INTR (Input)

INTERRUPT REQUEST: As a general purpose interrupt, it is sampled only during the next to the last

clock cycle of an instruction and during Hold and Halt states. If it is active, the Program Counter

(PC) will be inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or
CALL instruction can be inserted to jump to the interrupt service routine. The INTR is enabled and

disabled by software. It is disabled by Reset and immediately after an interrupt is accepted.

INTA (Output)

INTERRUPT ACKNOWLEDGE: Used instead of (and has the same timing as ) RD during the instruc-

tion cycle after an INTR is accepted.

RST 5.5, RST 6.5, RST 7.5 (Input)

RESTART INTERRUPTS: These three inputs have the same timing as INTR, except that they cause
an internal RESTART to be automatically inserted.

The priority of these interrupts is ordered as shown in Table C-1. These interrupts have a higher

priority than INTR. In addition, they may be individually masked out using the SIM instruction.

TRAP (Input)

Trap interrupt is a nonmaskable RESTART interrupt. It is recognized at the same timing as INTR or

RST 5.5 - 7.5. It is unaffected by any mask or Interrupt Disable. It has the highest priority of any in-

terrupt. (See Table C-1.)

RESET IN (Input)

Sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops. The data
and address buses and the control lines are 3-stated during RESET and because of the asynchro­nous nature of RESET, the processor's internal registers and flags may be altered by RESET with
unpredictable results. RESET IN is a Schmitt-triggered input, allowing connection to an R-C net­work for power-on RESET delay. The CPU is held in the reset condition as long as RESET IN is ap-

plied.
RESET OUT (Output)

Indicates the CPU is being reset. Can be used as a system reset. The signal is synchronized to the

processor clock and lasts an integral number of clock periods.
X1, X2 (Input)

X1 and X2 are connected to a crystal to drive the internal clock generator. X, can also be an external
clock input from a logic gate. The input frequency is divided by 2 to give the processor's internal

operating frequency.

CLK (Output)
Clock Output for use as a system clock. The period of CLK is twice the X1, X2 input period.

SID (Input)

Serial input data line. The data on this line is loaded into accumulator bit 7 whenever a RIM instruc-

tion is executed.

SOD (Output)

Serial output data line. The output SOD is set or reset as specified by the SIM instruction.

Vcc

+5 volt supply.

GND

Ground reference.

Name

Priority

Address Branched To (1)

When Interrupt Occurs

Type Trigger

TRAP

1

24H

Rising edge and high level

RST 7.5

2

3CH

until sampled.
Rising edge (latched).

RST 6.5

3

34H

High level until sampled.

RST 5.5

4

2CH

High level until sampled.

INTR 5

(2)

High level until sampled.

Notes: (1) The processor pushes the PC on the stack before branching to the indicated address.

(2) The address branched depends on the instruction provided to the CPU when the inter-

rupt is acknowledged.

Table C-1. Interrupt Priority , Restart Address and Sensitivity

Function

The 80C85A has twelve addressable 8-bit registers. Four can function only as two 16-bit

register pairs. Six others can be used interchangeably as 8-bit registers or a 16-bit register pair.

The 80C85A register set is as follows:

Mnemonic

Register

Contents

ACC or A

Accumulator

8-bits

PC

Program Counter

16-bit address

BC, DE, HL

General-Purpose Register; 8-bit x 6 or 16-bits x 3
data pointer (HL)

SP

Stack Pointer

16-bit address

Flags or F

Flag Register

5 flag (8-bit space)

The 80C85A uses a multiplexed Data Bus. The address is split between the higher 8-bit Address

Bus and the lower 8-bit Address/Data Bus. During the first T state (clock cycle) of a machine cycle,
the low order address is sent out on the Address/Data Bus. These lower 8-bits may be latched
externally by the Address Latch Enable signal (ALE). During the rest of the machine cycle, the data

bus is used for memory or I/O data.
The 80C85A provides RD, WR, So, Si and IO/M signals for bus control. An Interrupt Acknowledge

signal (INTA) is also provided. Hold and all Interrupts are synchronized with the processor's inter­nal clock. The 80C85A also provides Serial Input Data (SID) and Serial Output Data (SOD) lines for
a simple serial interface.
In addition to these features, 80C85A has three maskable, vector interrupt pins and one nonmaska-

ble TRAP interrupt.

Interrupt and Serial I/O

The 80C85A has 5 interrupt inputs: INTR, RST 5.5, RST 6.5, RST 7.5, and TRAP. INTR is identical in
function to the 8080A INT. Each of the three RESTART inputs, 5.5, 6.5, and 7.5, has a programma­ble mask. TRAP is also a RESTART interrupt but it is nonmaskable.
The three maskable interrupts cause the internal execution of RESTART (saving the program
counter in the stack and branching to the RESTART address) if the interrupts are enabled and if the
interrupt mask is not set. The nonmaskable TRAP causes the internal execution of a RESTART vec-

tor independent of the state of the interrupt enable or masks. (See Table C-1.)
There are two different types of inputs in the restart interrupts. RST 5.5 and RST 6.5 are high level-

sensitive like INTR (and INT on the 8080A) and are recognized with the same timing as INTR. RST

7.5 is rising edge-sensitive.

C-4

For RST 7.5, only a pulse is required to set an internal flip-flop which generates the internal interrupt
request. The RST 7.5 request flip-flop remains set until the request is serviced. Then it is reset au-

tomatically. This flip-flop may also be reset by using the SIM instruction or by issuing a RESET IN to

the 80C85A. The RST 7.5 internal flip-flop will be set by a pulse on the RST 7.5 pin even when the

RST 7.5 interrupt is masked out.

The interrupts are arranged in a fixed priority that determines which interrupt is to be recognized if

more than one is pending as follows: TRAP-highest priority, RST 7.5, RST 6.5, RST 5.5, INTR-lowest

priority. This priority scheme does not take into account the priority of a routine that was started by

a higher priority interrupt. RST 5.5 can interrupt an RST 7.5 routine if the interrupts are re-enabled

before the end of the RST 7.5 routine.

The TRAP interrupt is useful for catastrophic events such as power failure or bus error. The TRAP

input is recognized just as any other interrupt but has the highest priority. It is not affected by any

flag or mask. The TRAP input is both edge and level sensitive. The TRAP input must go high and

remain high until it is acknowledged. It will not be recognized again until it goes low, then high
again. This avoids any false triggering due to noise or logic glitches. Figure C-3 illustrates the

TRAP interrupt request circuitry within the 80C85A. Note that the servicing of any interrupt (TRAP,

RST 7.5, RST 6.5, RST 5.5, INTR) disables all future interrupts (except TRAPs) until an El instruction

is executed.

The TRAP interrupt is special in that it disables interrupts, but preserves the previous interrupt

enable status. Performing the first RIM instruction following a TRAP interrupt allows you to deter­mine whether interrupts were enabled or disabled prior to the TRAP. All subsequent RIM instruc-

tions provide current interrupt enable status. Performing a RIM instruction following INTR or RST

5.5 - 7.5 will provide current Interrupt Enable status, revealing that Interrupts are disabled.

The serial I/O system is also controlled by the RIM and SIM instructions. SID is read by RIM, and

SIM sets the SOD data.

EXTERNAL
TRAP
INTERRUPT
REQUEST TRAP

INSIDE THE 80C85A

RESET IN SCHMITT

TRIGGER

-

RESET

TRAP

INTERRUPT

+5V

D CLK

REQUEST

D

F/F

CLEAR

TRAP F.F

INTERNAL

TRAP

ACKNOWLEDGE

Figure C-3. Trap and RESET IN

Basic System Timing

The 80C85A has a multiplexed Data Bus. ALE is used as a strobe to sample the lower 8-bits of ad-

dress on the Data Bus. Figure C-4 shows an instruction fetch, memory read and I/O write cycle (as

would occur during processing of the OUT instruction). Note that during the I/O write and read cy-

cle that the I/O port address is copied on both the upper and lower half of the address.
There are seven possible types of machine cycles. Which of these seven takes place is defined by
the status of the three status lines (IO/M,Si, So) and the three control signals (RD, WR, and INTA).

(See Table C-2.) The status line can be used as advanced controls (for device selection, for exam-

ple), since they become active at the T, state, at the outset of each machine cycle. Control lines RD

and WR become active later, at the time when the transfer of data is to take place, so are used as

command lines.

C-5

A machine cycle normally consists of three T states, with the exception of OPCODE FETCH, which
normally has either four or six T states (unless WAIT or HOLD states are forced by the receipt of
READY or HOLD inputs). Any T state must be in one of ten possible states , shown in Table C-3.

Machine Cycle

Status

Control

_

IO/M Si So

RD WR INTA

Opcode Fetch

(OF) 0

1

1

0

1 1

Memory Read

(MR)

0

1

0

0 1

1

Memory Write

(MW) 0

0 1

1

0

1

I/O Read

(IOR)

1

1

0 0

1 1

I/O Write (lOW)

1

0 1 1

0

1

Acknowledge of INTR (INA) 1

1 1

1

1 0

Bus Idle

(BI): DAD

ACK. OF

0

1

0

1

1

1

RST, TRAP 1

1 1 1 1

1

HALT

TS 0

0

TS TS 1

Table C-2. 80C85A Machine Cycle Chart

Status & Buses

Control

Machine State

Si, So

IO/M A8 - A15 ADo - ADS RD, WR

INTA

ALE

Ti X X

X X 1 1

1

(1)

T2 X X

X X X X 0

TWAIT

X

X

X X X X 0

T3

X X

X

X X X 0

T4

1

0(2)

X TS 1 1

0

T5

1

0(2)

X TS 1 1

0

T6

1

()(2)

X TS

1

1 0

TRESET X TS

TS TS TS

1

0

THALT

0

TS

TS

TS

TS 1

0

THOLD X

TS

TS TS

TS 1

0

0 = Logic "0"

1 =Logic "1"

TS =High Impedance

X = Unspecified

Notes : (1) ALE not generated during 2nd and 3rd machine cycles of DAD instruction.

(2) IO/M = 1 during T4-T6 of INA machine cycle.

Table C-3. 80C85A Machine State Chart

Mi M2 M3

Ti T2 T3 T4 Ti T2 T3 Ti T2 T3

CLK

AB-A15

ADo-AD7

ALE

PCH HIGH ORDER ADDRESS) (P Lt1)H(HIGH ORDER ADDRESS) n PORT No.

PCL - ----- - (PC+0L - n DATA TO MEMORY

DATA FROM (OUT n) DATA FROM

OR 1/0

MEMORY MEMORY

RD

WR

I ()/M

STATUS S i =1 , So =1 (FETCH) 1, D(READ) 0, 1(WRITE)

Figure C-4. 80C85A Basic System Timing

C-2. 81 C55

General Description

The MSM81 C55RS/GS is a 2K bit static RAM (256 byte) with parallel I/O ports. It uses silicon gate
CMOS technology and consumes a standby current of 100 micro amperes maximum while the chip

is not selected. Featuring a maximum access time of 400 ns, the MSM81 C55RS/GS can be used in
an 80C85A system without using wait states. The parallel I/O consists of two 8-bit ports and one
6-bit port (both general purpose). The MSM81C55RS/GS also contains a 14-bit programmable
counter/timer which may be used for sequence-wave generation or terminal countpulsing.

1o/M

ADo 7

CE

ALE

RD
WR

RESET

256x8

B

STATIC f-I PORT B

RAM

1 TIMER

PORT A

PA o--7

8 PBo- -7

PORT C

6 PCO - s

TIMER CLK Vcc (+ 5 V)

TIMER OUT

GND(0 V)

Figure C-5. Functional Block Diagram

dll

w I W W

a0 ¢

,p0. t,n

Q

L')

D e

_

C' n

U U U aG a,0

m m

a

6 Q

a

o

Qa

> d O d0.d d Q.

, d

T

Q d 0. O. C d 3 d

6 O. C1

a-

0) N N

N

N

U

ao

r

r

rn

L)

a

w

Uj

w

o[ w

W Cy

F-

U

101CY0

I _ 0a a 0 0a oz

o < a a a a a a a a c

oc

H

WW

A

k

1

y

\V VW W

Figure C-6. Pin Configuration of 81C55

C-7

Functional Pin Description

RESET (Input)

A high level input to this pin resets the chip, placing all three I/O ports in the input mode, and stops

timer.
ALE (Input)

Negative going edge of the ALE (Address Latch Enable) input latches ADo - 7, IO/M, and CE signals

into the respective latches.

ADo - 7 (Input/Output)

Three- state , bi-directional address/data bus. Eight-bit address information on this bus is read into
the internal address latch at the negative-going edge of the ALE. Eight bits of data can be read

from or written to the chip using this bus, depending on the state of the WRITE or READ input.

CE (Input)

When the CE input is high, both read and write operations to the chip are disabled.

IO/M (Input)

A high level input to this pin selects the internal I/O functions. A low level selects the memory.

RD (input)

If this pin is low, data from either the memory or ports is read onto the ADo - 7 lines, depending on

the state of the IO/M line.

WR (Input)

If this pin is low, data on lines ADo - 7 is written into either the memory or into the selected port,

depending on the state of the IO/M line.
PAo -. 7, PBo - 7 (input/Output)

General-purpose I/O pins. Input/output directions can be determined by programming the com-

mand/status (C/S) register.

PCo - 5 (Input/Output)

Three pins are usable either as general-purpose I/O pins or control pins for the PA and PB ports.

When used as control pins, they are assigned to the following functions:

PCO: A INTR (port A interrupt)

PC1 : A BF (port A full)

PC2: A STB (port A strobe)
PC3: B INTR (port B interrupt)

PC4: B BF (port B buffer full)

PC5 : B STB (port B strobe)

TIMER IN (Input)

Input to the counter/timer

TIMER OUT (Output)

Timer output. When the present count is reached during timer operation, this pin provides a

square-wave or pulse output, depending on the programmed control status.

C-8

Function

81 C55 has 3 functions:

•

2K bit, static RAM (256 words x 8 bits)

•

Two 8-bit I/O ports (PA and PB) and a 6-bit I/O port (PC)

• 14-bit timer counter

The internal register is shown in the figure below, and the I/O addresses are described in the table

following.

8-bit Internal Data Bus

Com-

PC PB PA

Timer Timer

mand t MSB LSB

Status Timer Mode

6 bits 8 bits

8 bits

Figure C-7. Internal Register of 81 C55

I/O Address

Selecting Register

A7 A6 A5 A4 A3 A2

Al AO

X X

X X X 0

0 0

Internal command/status register

X

X

X

X X

0 0 1 Universal I/O port A (PA)

X

X

X

X

X

0 1

0

Universal I/O port B (PB)

X X

X X X 0

1 1 1/O port C (PC)

X X

X X X 1

0 0

Timer count lower position 8 bits (LSB)

X X

X X X 1

0

1 Timer count upper position 6 bits and timer mode 2 bits (MSB)

X : Don't care.

Table C-4. I/O Address of 81 C55

(1) Programming the Command/Status (C/S) Register

The contents of the command register can be written during an I/O cycle by addressing it with an

I/O address of xxxxx000. Bit assignments for the register are shown below:

TM1 TM2 IEB IEA PC2 PC1 PB PA

Timer command

Definition of PAo - 7

0 = input

Definition of PBo -,. 7

1 =output

00 = ALT1

See the port

11 =ALT2

control

Definition of PCo - 5

01 =ALT3 assignment

10 =ALT4

table.

Port A interrupt enable

1 = enabled

Port B interrupt enable 0 = disabled

00 = NOP : Does not affect counter operations.

01 = STOP : Stops the timer if it is running.

NOP if the timer is not running.

10 = STOP AFTER TC : Stops the timer when it reaches

TC.

NOP if the timer is not running.

11 = START: If the timer is not running, loads the mode

and the count length, and immediately
starts timer operation. If the timer is run­ning, loads a new mode and the count
length, and starts timer operation imme-

diately after TC is reached.

Figure C-8. Programming the Command/ Status Register

Pin

ALT1

ALT2 ALT3

ALT4

PCo

Input port Output port

A INTR A INTR

PCB

Input port

Output port A BF

A BF

PC2

Input port

Output port A STB

A STB

PC3

Input port

Output port

Output port B INTR

PC4

Input port

Output port

Output port B BF

PC5 Input port

Output port

Output port

B STB

Table C-5. Port Control Assignment

(2) Reading the C/S Register

The I/O and timer status can be accessed by reading the contents of the Status register located at

I/O address xxxxx000. The status word format is shown below:

AD7 AD6 AD5 AD4 AD3 AD2 AD1 ADO

TIMER INTE B B BF INTR B INTE A A BF INTR A

Port A interrupt request
Port A buffer full
Port A interrupt enable
Port B interrupt request

Port B buffer full

Port B interrupt enable

Timer interrupt. This bit is set high when the timer

reaches TC, and is reset when the C/S register is read or
a hardware reset occurs.

Figure C-9. Reading the C/S Register

(3) PA and PB Registers

These registers may be used as either input or output ports depending on the programmed con-

tents of the C/S register. They may also be used either in the basic mode or in the strobe mode.

I/O address of the PA register: xxxxx001
I/O address of the PB register: xxxxx010

(4) PC Register

The PC register may be used as an input port, output port or control register depending on the pro-

grammed contents of the C/S register. The I/O address of the PC register is xxxxx011.

(5) Timer

The timer is a 14-bit counter which counts TIMER IN pulses.

The low order byte of the timer register has an I/O address of xxxxx100, and the high order byte of

the register has an I/O address of xxxxx101.

The count length register (CLR) may be preset with two bytes of data. Bits 0 through 13 are as-

signed to the count length: bits 14 and 15 specify the timer output mode. A read operation of the

CLR reads the contents of the counter and the pertinent output mode. The initial value range which
can initially be loaded into the counter is 2 through 3FFF hex. Bit assignments to the timer counter

and possible output modes are shown in the following.

M2 M1 T13 T12 T11 T10 T9 T8

Output mode High order 6 bits of count length

T7 T6 T5 T4 T3 T2 T1 TO

Low order byte of count length

Figure C-10. Bit Assignments to the Timer Counter

C-11

M2 MI

0 0 Outputs a low-level signal in the latter half (Note 1) of a count period.

0 1 Outputs a low-level signal in the latter half of a count period, automatically loads the pro-

grammed count length, and restarts counting when the TC value is reached.

1 0 Outputs a pulse when the TC value is reached.

1 1 Outputs a pulse each time the preset TC value is reached, automatically loads the pro-

grammed count length, and restarts from the beginning.

Note 1 : When counting an asymmetrical value such as (9), a high level is output during the first

period of five, and a low level is output during the second period of four.

Note 2: If an internal counter of the 81 C55 receives a reset signal, count operation stops but the

counter is not set to a specific initial value or output mode. When restarting count opera­tion after reset, the START command must be executed again through the C/S register.

(6) Standby Mode

The 81 C55 is placed in standby mode when the high level at CE input is latched during the nega-

tive-going edge of ALE. All input ports and the timer input should be pulled up or down to either
Vcc or GND potential.
When using battery back-up, all ports should be set low or in input port mode. The timer output

should be set low. Otherwise, a buffer should be added to the timer output and the battery should

be connected to the power supply pins of the buffer.

By setting the reset input to a high level, the standby mode can be selected. In this case, the com­mand register is reset, so the ports automatically set to the input mode and the timer stops.