Datasheet T4312816A-8S, T4312816A-7.5S, T4312816A-7S, T4312816A-6S, T4312816A-10S Datasheet (Taiwan Memory Technology)

TE

tm

SDRAM

FEATURES

3.3V power supply

•

Four banks operation

•

LVTTL compatible with multiplexed address

•

All inputs are sampled at the positive going

•

edge of system clock

Burst Read Single-bit Write operation

•

DQM for masking

•

Auto refresh and self refresh

•

64ms refresh period (4K cycle)

•

MRS cycle with address key programs

•

- CAS Latency ( 2 & 3 )

- Burst Length ( 1 , 2 , 4 , 8 & full page)

- Burst Type (Sequential & Interleave)

Available package type in 54 pin TSOP(II)

•

Operating temperature : 0 ~ +70 °C

•

ORDERING INFORMATION

PART NO.

T4312816A-6S 166 MHz
T4312816A-7S 143 MHz
T4312816A-7.5S 133 MHz
T4312816A-8S 125 MHz
T4312816A-10S 100 MHz

CH

Preliminary T4312816A

MAX

FREQUENCY

TEMPERATURE

0 ~ +70°C
0 ~ +70°C
0 ~ +70°C
0 ~ +70°C
0 ~ +70°C

8M x 16 SDRAM

2M x 16bit x 4Banks Synchronous DRAM

GRNERAL DESCRIPTION

The T4312816A is 134,217,728 bits
synchronous high data rate Dynamic RAM
organized as 4 x 2,097,152 words by 16 bits,
fabricated with high performance CMOS
technology .

Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clockcycle . Range of operating
frequencies , programmable burst length and
programmable latencies allow the same device to
be useful for a variety of high bandwidth , high
performance memory system applications.

PIN ARRANGEMENT (

V

DD

DD

CS

A0
A1
A2
A3

DD

1

2
3
4
5
6
7
8
9
10
11
12
13

14
15
16
17
18
19
20
21
22
23
24
25
26

(400mil x 875m il)

(0.8 mm PIN PITCH)

54 P IN T S O P( II)

DQ0

DDQ

V

DQ1

DQ2

SSQ

V

DQ3

DQ4

DDQ

V

DQ5

DQ6

SSQ

V

DQ7

V

LDQ M

W E
CAS

RAS

BA0
BA1

A10/AP

V

Top View)

Vss

54

DQ15

53

V SSQ

52

DQ14

51

DQ13

50

V

49
48
47
46
45
44
43
42
41
40
39
38
37

36
35
34
33
32
31
30
29
2827

DDQ

DQ12
DQ11
V SSQ

DQ1
0
DQ9

DDQ

V
DQ8
Vss
N.C/RFU
UDQM
CLK
CKE
N.C
A11
A9
A8
A7
A6
A5
A4
Vss

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TE

tm

BLOCK DIAGRAM

CH

Preliminary T4312816A

I/O Control Output Buffer

CLK

ADD

Bank Select

Refresh Counter

Row Buffeer

Address Register

LCBR

LRA S

Timing Register

Row Decoder

Col. Buffer

Data Input Register

2M x 16
2M x 16

2M x 16
2M x 16

Column D ecoder

Laten c y & Burst Le n g th

Programming Register

Sense AMP

DQi

CAS WE

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L(U)DQ MRASCSCKECLK

Publication Date: APR. 2003

to change products or specifications without notice. Revision: 0.B

TE

tm

PIN DESCRIPTION

CH

Preliminary T4312816A

PIN NAME

CLK System Clock

CS

CKE Clock Enable

A0 ~ A11 Address

BA0 ~ BA1 Bank Select Address

RAS

CAS

Chip Select

Row Address Strobe

Column Address Strobe

INPUT FUNCTION

Active on the positive going edge to sample all input.
Disables or enables device operation by masking or enabling all input
except CLK,CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11,column address : CA0 ~ CA8
Selects bank to be activated during row address latch time.
Select bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK

RAS

with
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK
with

CAS

low.

low.

WE

L(U)DQM

DQ0 ~ DQ15 Data Input/Output

VDD/VSS Power Supply/Ground

V

DDQ/VSSQ

N.C/RFU

Write Enable

Data Input/Output

Mask

Data Output

Power/Ground

No

Connection/Reserved

for Future Use

Enables column access .
Enables write operation and row precharge.
Latches data in starting from
Makes data output Hi-Z,
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
This pin is recommended to be left No Connection on the device.

CAS, WE

t

after the clock and masks the output.

SHZ

active.

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ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit

CH

Preliminary T4312816A

Voltage on Any Pin Relative To Vss VIN,V
Supply Voltage Relative To Vss VDD,V
Short circuit Output Current I
Power Dissipation PD 1 W
Operating Temperature T
Storage Temperature T

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Note :

Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

RECOMMENDED DC OPERATING CONDITIONS

(TA = 0 to +70

Parameter Symbol Min. Typ Max. Unit Notes

Supply Voltage VDD,V

Input High Voltage VIH 2.0 3.0 VDD+0.3V V

Input Low Voltage VIL -0.3 0 0.8 V

Output logic high voltage VOH 2.4 - - V IOH=-4mA

, Voltage referenced to VSS=0V)

°°°°C

3.0 3.3 3.6 V

DDQ

-1.0 to 4.6 V

OUT

-1.0 to 4.6 V

DDQ

50 mA

out

0 to +70

OPR

-55 to +150

stg

C

°

C

°

Output logic low voltage VOL - - 0.4 V IOL=4mA

Input leakage current IIL -1 - 1 uA 1

Output leakage current IOL -1.5 - 1.5 uA 2

Note :

1. Any input 0V

2. Dout = disable, 0V≤ V

VIN ≤ VDD+ 0.3V , all other pin are not under test = 0V.

≤

V

OUT

≤

DD .

CAPACITANCE

(TA =25

RAS,CAS,WE,CS,CKE,LDQM,

,VDD=3.3V, f = 1MHz)

C

°

Pin Symbol Min Max Unit

CLOCK C

ADDRESS C

DQ0 ~ DQ15 C

UDQM

2.5 4.0 pF

CLK

2.5 5.0 pF

ADD

4.0 6.5 pF

OUT

CIN 2.5 5.0 pF

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DC CHARACTERISTICS

CH

Preliminary T4312816A

TA = 0 to 70

, VIH(min)/VIL(max)=2.0V/0.8V

C

°

Parameter Symbol

Operating Current

I

CC1

( One Bank Active)

Precharge Standby

I

CC2

Current in power-

I

down mode

CC2

Precharge Standby

I

Current in non

CC2

power-down mode

I

CC2

Active Standby

I

CC3

Current in power-

I

down mode

CC3

Active Standby

I

Current in non

CC3

power-down mode

I

(One Bank Active)

CC3

Speed version

Unit Test Condition

-6 -7 -7.5 -8 -10

140 120 115 110 100 mA

P 2

mA

PS 2

N 20

mA

NS 8

P 5

mA

PS 4

N 30

mA

NS 20

Burst Length = 1

t

t

≥

RC

RC

CKE≤ VIL(max),

CKE≤ VIL(max),CLK ≤VIL(max),

CKE

≥

Input signals are changed one time during 30ns

CKE≥VIH(min),CLK≤VIL(min),

Input signals are stable

CKE≤ VIL(max),

CKE≤ VIL(max),CLK ≤VIL(max),

CKE≥VIH(min),

Input signals are changed one time during 30ns

CKE≥VIH(min),CLK≤VIL(min),

Input signals are stable

(min) ,

VIH(min),

t

CC

t

(min),IOL= 0 mA

≥

CC

t

=15ns

CC

VIH(min),

≥

CS

t

=15ns

CC

VIH(min),

≥

CS

t

t

CC

t

t

CC

CC

t

CC

=15ns

CC

=∞

t

CC

=15ns

=∞

=∞

=∞

Note

1,3

3

3

3

3

Operating Current

(Burst Mode)

Refresh Current

Self refresh
Current

150 130 125 120 110

I

CC4

150 130 125 120 110

150 130 125 120 110 mA

I

CC5

I

2 mA

CC6

CAS Latency 3

mA

CAS Latency 2

t

RC

CKE≤0.2V

=0 mA,Page Burst

I

OL

All Band Activated

t

t

=

CCD

CCD

t

(min)

≥

RC

Note: 1. Measured with output open. Addresses are changed only one time during

2. Refresh period is 64ms. Addresses are changed only one time during

3.

t

: Clock cycle time.

CC

t

: Row cycle time.

RC

t

: Column address to column address delay time.

CCD

t

CC

(min)

t

CC

(min)

(min)

.

1,3

2,3

.

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AC OPERATING CONDITIONS

(VDD=3.3V ±0.3V ,TA= 0 to 70

Input levels (VIH/VIL) 2.4 / 0.4 V

Input timing measurement reference level 1.4 V

CH

Preliminary T4312816A

)

C

°

Parameter Value Unit

Input rise and fall time

Output timing measurement reference level 1.4 V

Output load condition See Fig.2

t

r / tf = 1 / 1

ns

3.3V

Output

870 ohm

1200 ohm

ZO=50 ohmOutput

VOH(DC)=2.4,IOH=-4mA

VOL(DC)=0.4,IOL=4mA

30pf

Vtt=1.4v

50 ohm

30pf

(Fig.1) DC Output Load Circuit (Fig.2)AC Output Load Circuit

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OPERATING AC PARAMETER

(AC opterating conditions unless otherwise noted)

Row active to row active delay

RAS to CAS delay

CH

Preliminary T4312816A

Parameter Symbol

t

(min)

RRD

t

(min)

RCD

Speed Version

Unit Note

-6 -7 -7.5 -8 -10

12 14 15 16 20 ns 1

15 15 18 20 20 ns 1

Row precharge time

Row active time

Row cycle time

Last data in to new col. Address delay

Last data in to row precharge

Last data in to burst stop

Col. Address to col. Address delay

Number of valid output data

t

(min)

RP

t

(min)

RAS

t

RAS

t

(min)

RC

t

CDL

t

RDL

t

BDL

t

CCD

CAS latency=3 1
CAS latency=2 1

(max)

(min)

(min)

(min)

(min)

15 15 20 20 20 ns 1

42 42 45 48 50 ns 1

120K ns

60 63 65 68 70 ns 1

1 CLK 2

2 CLK 2

1 CLK 2

1 CLK 3

ea 4

Note:

1. The minimum number of clock cycles is determined by dividing the minimum time required

with clock cycle time and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is
CL + BL-2 clocks.

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AC CHARACTERISTICS

(AC opterating conditions unless otherwise noted)

CLK cycle time

CH

Preliminary T4312816A

-6 -7 -7.5 -8 -10

t

Min Max Min Max Min Max Min Max Min Max

CC

8 9 9 10 10

Parameter

CAS Latency = 3 6 1K 7 1K 7.5 1K 8 1K 10 1K

CAS Latency = 2

Symbol

Unit Note

ns 1

CLK to valid
Output delay

Output data hold time
CLK high pulse width
CLK low pulse width

Input setup time
Input hold time
CLK to output in Low-Z

CLK to output in
Hi-Z

CAS Latency = 3 - 5.5 - 6 6 - 6 - 7 ns

t

SAC

CAS Latency = 2

t

OH

t

CH

t

CL

t

SS

t

SH

t

SLZ

CAS Latency = 3 - 5.5 - 6 6 - 6 - 7 ns

t

SHZ

CAS Latency = 2

- 6 - 6 6 - 7 - 9 ns
2 2.5 2.5 2.5 2.5 ns 2
2 2.5 2.5 3 3 ns 3
2 2.5 2.5 3 3 ns 3

1.5 1.75 1.75 2 2.5 ns 3
1 1 1 1 1 ns 3
1 1 1 1 1 ns 2

- 6 - 6 6 - 7 - 9 ns

Note:

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf)=1ns.

If tr & tf is longer than 1ns,transient time compensation should be considered,
i.e.,[(tr+tf)/2-1]ns should be added to the parameter.

1

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FREQUENCY vs. AC PARAMETER RELATIONAHIP TABLE

T4312816A-6S (Unit : number of clock)

Frequency

166MHz(6.0ns)
143MHz(7.0ns) 3 9 6 3 2 3 1 1 2
125MHz(8.0ns) 2 9 6 2 2 2 1 1 2

111MHz(9.0ns) 2 7 5 2 2 2 1 1 2

100MHz(10.0ns) 2 7 5 2 2 2 1 1 2

T4312816A-7S (Unit : number of clock)

Frequency

143MHz(7.0ns)
125MHz(8.0ns) 3 9 6 2 2 2 1 1 2
111MHz(9.0ns) 2 8 5 2 2 2 1 1 2

100MHz(10.0ns) 2 7 5 2 2 2 1 1 2

83MHz(12.0ns) 2 6 4 2 2 2 1 1 2

T4312816A-7.5S (Unit : number of clock)

Frequency

133MHz(7.5ns)
125MHz(8.0ns) 3 9 6 3 2 3 1 1 2
111MHz(9.0ns) 2 8 5 3 2 2 1 1 2

100MHz(10.0ns) 2 7 5 2 2 2 1 1 2

83MHz(12.0ns) 2 6 4 2 2 2 1 1 2

CH

Preliminary T4312816A

CAS

Latency

3 10 7 3 2 3 1 1 2

CAS

Latency

3 9 6 3 2 3 1 1 2

CAS

Latency

3 9 6 3 2 3 1 1 2

RC

t

60ns 42ns 15ns 12ns 15ns 6ns 6ns 12ns

RC

t

63ns 42ns 15ns 14ns 15ns 7ns 7ns 14ns

RC

t

65ns 45ns 20ns 15ns 18ns 7.5ns 7.5ns 15ns

RAS

t

RAS

t

RAS

t

RP

t

RP

t

RP

t

RRD

t

RRD

t

RRD

t

RCD

t

RCD

t

RCD

t

CCD

t

CCD

t

CCD

t

CDL

t

CDL

t

CDL

t

RDL

t

RDL

t

RDL

t

T4312816A-8S (Unit : number of clock)

Frequency

125MHz(8.0ns)
111MHz(9.0ns) 3 9 6 3 2 3 1 1 2

100MHz(10.0ns) 2 7 5 2 2 2 1 1 2

83MHz(12.0ns) 2 6 4 2 2 2 1 1 2
75MHz(13.0ns) 2 6 4 2 2 2 1 1 2

CAS

Latency

3 9 6 3 2 3 1 1 2

RC

t

68ns 48ns 20ns 16ns 20ns 8ns 8ns 16ns

RAS

t

RP

t

RRD

t

RCD

t

CCD

t

CDL

t

RDL

t

T4312816A-10S (Unit : number of clock)

Frequency

100MHz(10.0ns)

83MHz(12.0ns) 2 7 5 2 2 2 1 1 2
75MHz(13.0ns) 2 6 4 2 2 2 1 1 2
66MHz(15.0ns) 2 6 4 2 2 2 1 1 2
60MHz(16.7ns) 2 5 3 2 2 2 1 1 Note 1

Note : 1.

2. Clock count formula : clock ≥

RDL ≥

t

CAS

Latency

2 7 5 2 2 2 1 1 2

16.7ns is recommended for T4312816A

RC

t

70ns 50ns 20ns 20ns 20ns 10ns 10ns 20ns

RAS

t

RP

t

RRD

t

valuebase
periodclock

(round off whole number).

RCD

t

CCD

t

CDL

t

RDL

t

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MODE REGISTER

11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 1

11 10 9 8 7 6 5 4 3 2 1 0

x x 1 0 0 LTMODE WT BL

11 10 9 8 7 6 5 4 3 2 1 0

1 0

11 10 9 8 7 6 5 4 3 2 1 0

x x x 1 1 v v v v v v v

11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 LTMODE WT BL

Remark R : Reserved

Mode Register Write Timing

CH

Preliminary T4312816A

JEDEC Standard Test Set (refresh counter test)

Burst Read and Single Write (for Write Through Cache)

Use in future

Vender Specific

v = Valid

Mode Register Set

Burst length

Wrap type

Latency mode

Bit2-0 WT=0 WT=1

000 1 1
001 2 2

010 4 4
011 8 8
100 R R

101 R R
110 R R

111 Full page R

0 Sequential
1 Interleave

Bit6-4 CAS Latency

000 R
001 R

010 2
011 3
100 R

101 R
110 R

111 R

x = Don’t care

CLOCK

CKE

CS
RAS
CAS

WE

A0-A11

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Burst Length and Sequence

(Burst of Two)

(column address A0 binary)

(Burst of Four)

(column address A1-A0 binary)

(Burst of Eight)

(column address A2-A0 binary)

CH

Preliminary T4312816A

Starting Address

0 0,1 0,1
1 1,0 1,0

Starting Address

00 0,1,2,3 0,1,2,3
01 1,2,3,0 1,0,3,2
10 2,3,0,1 2,3,0,1
11 3,0,1,2 3,2,1,0

Starting Address

000 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7
001 1,2,3,4,5,6,7,0 1,0,3,2,5,4,7,6
010 2,3,4,5,6,7,0,1 2,3,0,1,6,7,4,5
011 3,4,5,6,7,0,1,2 3,2,1,0,7,6,5,4

Sequential Addressing

Sequence (decimal)

Sequential Addressing

Sequence (decimal)

Sequential Addressing

Sequence (decimal)

Interleave Addressing

Sequence (Decimal)

Interleave Addressing

Sequence (Decimal)

Interleave Addressing

Sequence (Decimal)

100 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3
101 5,6,7,0,1,2,3,4 5,4,7,6,1,0,3,2

110 6,7,0,1,2,3,4,5 6,7,4,5,2,3,0,1
111 7,0,1,2,3,4,5,6 7,6,5,4,3,2,1,0

Full page burst is an extension of the above tables of Sequential Addressing, with the length being 512 for
8Mx16 divice.

POWER UP SEQUENCE

1. Apply power and start clock, attempt to maintain CKE = ‘H’ , L(U)DQM = ‘H’ and the other pin are NOP
condition at the inputs.

2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue mode register set command to initalize the mode register.
Cf.) Sequence of 4 & 5 is regardless of the order.

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SIMPLIFIED TRUTH TABLE

Register Mode Register Set H X L L L L X X 1,2

Refresh

Bank Active & Row Address H X L L H H X V Row Address

CH

Preliminary T4312816A

BA

A

COMMAND CKEn-1 CKEn

Auto Refresh H

H

L H

L

Self
Refresh

Entry
Exit

CS

RAS

L L L H X X 3

L H H H
H X X X

CAS

WE

DQM

X X 3

0,1

10

/AP

A

9~A0,

A11

Note

X

X

X

Column
Address

(A0~A8)

Column
Address

(A0~A8)

4,5

4,5

4

7

Read Column
Address

Write & Column
Address

Burst Stop H X L H H L X X 6

Precharge

Clock Suspend or
Active Power Down

Precharge Power Down
Mode

DQM H X V

No Operation Command

(V=Valid , X=Don’t Care , H=Logic High , L=logic Low)
Notes :

1. OP Code : Operation Code. A

2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row

precharge command is meant by ‘Auto’. Auto / self refresh can be issued only at both banks precharge state.

4. BA0~BA1 : Bank select address.

If both BA0 and BA1 are ’Low’ : at read , write , row active and precharge , bank A is selected.
If both BA0 is ‘Low’ and BA1 is ‘High’ : at read , write , row active and precharge , bank B is selected.
If both BA0 is ‘High’ and BA1 is ‘Low’ : at read , write , row active and precharge , bank C is selected.
If both BA0 and BA1 are ’High’ : at read , write , row active and precharge , bank D is selected
If A

5. During burst read or write with auto precharge , new read/write command cannotbeissued.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),

10

/AP is ‘High’ : at row precharge , BA0 and BA1 ignored and all banks are selected.

Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at

but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

Auto Precharge Disable
Auto Precharge Enab le

Auto Precharge Disable
Auto Precharge Enab le

Bank Selection V L
Both Banks

Exit L H X X X X X

Exit

0~A11

H X L H L H X V

H X L H L L X V

H X L L H L X

H L

H L

L H

H H X X X
H

, BA0~BA1 : Program keys.(@MRS)

H X X X Entry
L V V V

H X X X Entry
L H H H
H X X X
L V V V

X

L H H H

RP

after the end of burst.

t

X H

X

X

X

X X

L
H
L
H

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Single Bit READ-Write Cycle (Same Page) @CAS Latency= 3,Burst Length=1

CH

CLOCK

Preliminary T4312816A

t

012345678910111213141516171819

CC

t

CH

tCL

CKE

CS

RAS

CAS

ADDR

BA

A10/AP

t

HIGH

RAS

t

RC

t

*Note1

RCD

t

S

H

t

t

SS

t

SH

t

SH

t

Ra

t

SS

*Note2

Bs Bs Bs Bs Bs Bs

SS

Ca

*Note2.
3

*Note3 *Note3 *Note3 *Note4

t

RAC

SH

SS

t

t

CCD

SS

t

RP

t

Cb Cc Rb

SH

t

*Note2.
3

*Note2.

*Note4 *Note2

3

RbRa

DQ

WE

DQM

t

t

SRC

SH

Qa Db Qc

t

t

SLZ

Row Active Read Write Read

t

OH

SS

t

SH

SS

t

t

SH

t

SS

Precharge

Row Active

:Don't care

TM Technology Inc. reserves the right P.13

Publication Date: APR. 2003

to change products or specifications without notice. Revision: 0.B

TE

tm

*note : 1. All input expect CKE & DQM can be don’t care when

2. Bank active & read/write are controlled by BA0 – BA1.

CH

Preliminary T4312816A

BA0 BA1 Active & Read/Write

0 0 Bank A
1 0 Bnak B
0 1 Bank C
1 1 Bnak D

is high at the CLK high going edge.

CS

3. Enable and disable auto precharge function are controlled by A

A10 Auto-Precharge

0 Disable (End of burst)
1 Enable (End of burst)

BA0 BA1 Operation

0 0 Enable read/write command for bank A .
1 0 Enable read/write command for bank B .
0 1 Enable read/write command for bank C .
1 1 Enable read/write command for bank D .

4. A

10

/AP and BA control bank precharge when precharge command is asserted.

A

10

/AP BA0 BA1 precharge

0 0 0 Bank A

10

/AP in read/wirte command.

0 1 0 Bank B
0 0 1 Bank C
0 1 1 Bank D
1 X X All Bamks

TMemory Technology Inc. reserves the right P.14
to change products or specifications without notice. Revision: 0.B

Publication Date: APR. 2003

TE

tm

Power Up Sequence

CLOCK

CH

Preliminary T4312816A

012345678910111213141516171819

C KE

C S

R AS

C AS

ADDR

B A

A10/AP

D Q

High level is necessary

t

RP

High-Z

t

SS
SS

SS

SS
SS

SS

SS
SS

SS

SS

SS

RC

t

CCD

t

SS

SS
SS

SS

SS
SS

SS
SS

SS

SS

RC

Key

Key

Key

RAa

RAa

WE

D QM

High level is necessary

Precharge
All B ank s

Auto

Refresh

SS

SS SS

Auto Refresh Mode R egister Set (A-Bank)

SS

Row

Ac tiv e

:Don't care

TM Technology Inc. reserves the right P.15

Publication Date: APR. 2003

to change products or specifications without notice. Revision: 0.B

TE

tm

Read & Write Cycle at Same Bank @Burst Length = 4

CLOCK

CH

Preliminary T4312816A

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

C K E

C S

R A S

C A S

ADDR

B A

A10/AP

C L = 2

D Q

C L = 3

W E

HIGH

*Note1

RC

t

tRC D

*Note2

Ra Ca0 Rb Cb0

RbRa

OH

t

tRA C

*Note3

*Note3 *Note4

Qa0 Qa1 Qa2 Qa3

tSA C

tOH

Qa0 Qa1 Qa2 Qa3

SAC

t

tSH Z

*Note4

tSH Z

Db0

Db0

Db1

Db1

Db2

Db2

Db3

Db3

RDL

t

RDL

t

D Q M

Row

A ctiv e (A -

Bank)

Read (A -

Bank)

Precharg

e (A-

Bank)

Row Active

(A-B n ak)

W rite (A -

Bnak)

Precharge

(a-Bn ak )

:Don't care

*Note : 1. Minimum row cycle times is requiqed to complete internal DRAM operation.

2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is

available after Row precharge. Last valid output will be Hi-Z(

3. Access time from Row active command.

CC

RCD

*(

t

+CAS latency-1)+

t

4. Output will be Hi-Z after the end of burst.(1,2,4,8 bit burst)

Burst can’t end in Full Page Mode.

TM Technology Inc. reserves the right P.16
to change products or specifications without notice. Revision: 0.B

SHZ

) after the clock.

t

SAC

t

Publication Date: APR. 2003

TE

tm

Page Read & Write Cycle at Same Bank @ Burst Length = 4

CLOCK

CH

Preliminary T4312816A

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

C K E

C S

R A S

C A S

ADDR

B A

A10/AP

C L = 2

D Q

C L = 3

RCD

t

Ra Ca0

Cb0

Qa0 Qa1

Qa0 Qa1

Qb0

HIGH

Qb1 Qb2

Qb0

tCCD

Qb1

Cc0 Cd0

Dc0 Dc1

Dc0 Dc1

Dd0

CDL

t

Dd0 Dd2

Dd1

*Note2

t

RDL

W E

D Q M

Row Active

(A -Bn ak )

Read (A -

Bnak)

Read (A -

Bnak)

*Note1

W rite (A -

Bnak)

W rite (A -

Bnak)

*Note3

Precharge
(A -Bn ak )

:Don't care

*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to
avoid bus contention.

2. Row precharge will interrupt writing. Last data input,

RDL

before Row precharge, will be written.

t

3. DQM should mask invalid input data on precharge command cycle when asserting precharge before

end of burst. Input data after Row precharge cycle will be masked internally.

TM Technology Inc. reserves the right P.17

Publication Date: APR. 2003

to change products or specifications without notice. Revision: 0.B

TE

tm

Page Read Cycle at Different Bank @ Burst Length = 4

CLOCK

CH

Preliminary T4312816A

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

C K E

C S

R A S

C A S

ADDR

B A

A10/AP

C L = 2

D Q

C L = 3

HIGH

*Note1

RAa CAa RBb CBb CAc CBd CAe

RAa RBb

QAa0 QAa1 QAa2 QAa3

QAa0 QAa1 QAa2 QAa3

QBb0

QBb1 QBb2 QBb3

QBb0

QAc0 QAc1

QBb1 QBb2 QBb3

QBd0

QAc0 QAc1

QBd1

QBd0

QAe0

QBd1

*Note2

QAe1

QAe0

QAe1

W E

D Q M

Row Active

(A-B a nk)

Read (A -

Bank)

Row Active

(B-B an k)

Read (B -

Bank)

Read (A -

Bank)

Read (B -

Bank)

Read (A -

Bank)

Precharge
(A-B a nk)

:Don't care

*Note : 1. CS can be don’t cared when RAS,

2. To interrupt a burst resd by row precharge, both the read and the precharge banks must be the same.

CAS

and WE are high at the clock high going edge.

TM Technology Inc. reserves the right P.18

Publication Date: APR. 2003

to change products or specifications without notice. Revision: 0.B

TE

tm

Page Write cycle at Different Bank @ Burst Length = 4

CLOCK

CH

Preliminary T4312816A

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

C K E

CS

R A S

C A S

ADDR

BA

A10/AP

DQ

HIGH

*Note2

RAa CAa RBb CBb CAc CBd

RAa RBb

DAa0 DA a1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 DBd1

tCDL tRDL

W E

DQM

Row Active

(A-B an k)

Write (A-

Bank)

Row Active

(B-B a nk )

Write (B-

Bank)

Write (A-

Bank)

Write (B-

Bank)

*Note1

Precharge
(A-B an k)

:Don't care

*Note : 1. To interrupt burst write by row precharge, DQM should be asserted to mask invalid input data.

2. To interrupt burst write by row precharge, both the write and the precharge banks must be the same.

TM Technology Inc. reserves the right P.19

Publication Date: APR. 2003

to change products or specifications without notice. Revision: 0.B

TE

tm

Read & Write Cycle at Different Bank @ Burst Length = 4

CLOCK

CH

Preliminary T4312816A

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

C K E

C S

R A S

C A S

ADDR

B A

A10/AP

C L = 2

D Q

C L = 3

HIGH

RAa CAa RBb CBb RAc CAc

RAa RBb RAc

CDL

t

QAa0

QAa1 QAa2 QAa3

QAa0 QAa1 QAa2 QAa3

DBb0 DBb1 DBb2 DBb3

DBb0 DBb1 DBb2 DBb3

*Note1

QAc0

QAc1 QAc2

QAc0

QAc1

W E

D Q M

*Note : 1.

Row Active

(A-B a nk)

CDL

should be met to complete write.

t

Read (A -

Bank)

Row Active

(B-B an k)

Precharge
(A-B a nk)

W rite (B -

Bank)

Row Active

(A-B a nk)

Read (A -

Bank)

:Don't care

TM Technology Inc. reserves the right P.20

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to change products or specifications without notice. Revision: 0.B

TE

tm

Read & Write Cycle with Auto Precharge @ Burst Length = 4

CLOCK

CH

Preliminary T4312816A

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

C K E

C S

R A S

C A S

ADDR

B A

A10/AP

C L = 2

D Q

C L = 3

HIGH

Ra Rb Ca Cb

Ra Rb

Qa0 Qa1 Qa2 Qa3

Qa0 Qa1 Qa2 Qa3

Db0

Db0

Db1

Db1

Db2

Db2

Db3

Db3

W E

D Q M

Row Active

(A -Ba nk )

Row Active

(B-B a nk )

R e ad w ith A uto

precharge (A-

Bank)

CL=2 Auto
Precharge Start
Po in t ( A -B an k )

CL=3 Auto

Precharge Start

Po in t ( A -B an k )

*Note : 1.

CDL

should be controlled to meet minimum

t

(In the case of Burst Length = 1 & 2 and BRSW mode)

RAS

before internal precharge start.

t

W rite w ith A u to

Precharge (B-

Bank)

Auto Precharge

Sta rt P o in t (A -

Bank)

:Don't care

TM Technology Inc. reserves the right P.21

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to change products or specifications without notice. Revision: 0.B

TE

tm

Clock suspension & DQM Operation Cycle @ CAS Latency = 2 ,Burst Length = 4

CLOCK

C K E

C S

R A S

C A S

CH

Preliminary T4312816A

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

ADDR

B A

A10/AP

D Q

W E

DQM

Ra Ca Cb Cc

Ra

Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Dc0 Dc2

SHZ

t

*Note3

Read QDM

Row Active Read Clock

Susp ension

SHZ

t

Read

Write

Write QDM

Clock

Suspension

Write QDM

:Don't care

*Note 1. DQM is needed to prevent bus contention.

TM Technology Inc. reserves the right P.22
to change products or specifications without notice. Revision: 0.B

Publication Date: APR. 2003

TE

tm

Read Interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length=Full Page

CLOCK

CH

Preliminary T4312816A

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

C K E

C S

R A S

C A S

ADDR

B A

A10/AP

C L = 2

D Q

C L = 3

HIGH

RAa CAa CAb

RAa

*Note2

QAa0 QAa1 QAa2 QAa3 QAa4

QAa0 QAa1 QAa2 QAa3 QAa4

1

QAb0

QAb1 QAb2 QAb3

2 2

QAb0 QAb1

QAb2

QAb4

QAb3

1

QAb5

QAb4 QAb5

W E

D Q M

Row Active

(A-B a nk)

Read (A -

Bank)

Burst Stop Precharge

Read (A -

Bank)

*Note : 1. Burst can’t end in full page mode, so auto precharge can’t issue.

2. About the valid DQs after burst stop, it is same as the case of
Both cases are illustrated above timing diagram. See the lable 1,2 on them.
But at burst write, burst stop and

RAS interrupt should be compared carefully.

Refer the timing diagram of ‘Full Page write burst stop cycle’.

3. Burst stop is valid at every burst length.

RAS interrupt.

(A-B a nk)

:Don't care

TM Technology Inc. reserves the right P.23

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to change products or specifications without notice. Revision: 0.B

TE

tm

Write Interrupted by Prechareg Command & Write Burst Stop Cycle @ Burst Length=Full Page

CLOCK

CH

Preliminary T4312816A

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

C K E

C S

R A S

C A S

ADDR

B A

A10/AP

D Q

HIGH

RAa CAa CAb

RAa

BDL

t

DAa0 DA a1 DAa2 DAa3 DAa4 DAb0 DA b1 DAb2 DAb3 DAb4 DAb5

RDL

t

*Note3

W E

DQM

Row Active

(A-B an k)

Write (A-

Bank)

Burst Stop W rite (A-

Bank)

Precharge
(A-B an k)

:Don't care

*Note : 1. Burst can’t end in full page mode, so auto precharge can’t issue.

2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell.
It is defined by AC parameter of

DQM at write interrupted by precharge command is needed to prevent invalid write.
Input data after Row precharge cycle will be masked internally.

3. Burst stop is valid at every burst length.

RDL

t

.

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to change products or specifications without notice. Revision: 0.B

TE

tm

Burst Read Single bit Write Cycle @ Burst Length = 2

CLOCK

CH

Preliminary T4312816A

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

C K E

C S

R A S

C A S

ADDR

B A

A10/AP

C L = 2

D Q

C L = 3

HIGH

*Note2

RAa CAa RBb CAb RAc CBc CAd

RAa RBb RAc

DAa0

DAa0

DAb0

DAb1

DAb0

DAb1

DBc0

DBc0

DAd0 DAd1

DAd0 DAd1

W E

D Q M

Row Active

(A-B a nk)

W rite (A -

Bank)

Row Active

(A-B a nk)

R ea d w ith A u to

Precharge (A -

Bank)

Row Active

(A-B a nk)

W rite w ith A uto

Precharge (A -

Bank)

Read (A -

Bank)

Precharge

(A-B a nk)

:Don't care

*Note : 1. BRSW modes is enabled by setting A9 ‘High’ at MRS (Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to ‘1’ regardless of programmed burst length.

2. When BRSW write command with auto precharge is executed, keep it in mind that
be violated.
Auto precharge is executed at the next cycle of burst-end, so in the case of BRSW write command,
the precharge command will be issued after two clock cycle.

RAS

should not

t

TM Technology Inc. reserves the right P.25

Publication Date: APR. 2003

to change products or specifications without notice. Revision: 0.B

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tm

Active/ Precharge Power Down Mode @ CAS latency = 2, Butsr length = 4

CLOCK

CK E

CH

Preliminary T4312816A

0 1 2 3 4 5 6 7 8 9 10111213141516171819

*Note1

SS

SS

*Note3

*Note2

SS

tsstsstss

SS

CS

RA S

CA S

ADDR

BA

A10/AP

D Q

W E

SS
SS

SS
SS

SS
SS

SS
SS

SS
SS

SS
SS

SS

SS
SS

SS
SS

SS
SS

SS
SS

Ra Ca

Ra

SS
SS

SS
SS

SS
SS

SS

SS
SS

Qa0 Qa1 Qa2

SHZ

t

D Q M

Precharge

Power-

Down Entry

SS
SS

Precharge

Power-

Down Exit

Row Active

Down Entry

Ac tive

Power-

SS
SS

Active

Power-

Down Exit

Read

Precharge

:D o n't c are

*Note : 1. Both banks should be in idle state prior to entering precharge power down mode.

2. CKE should be set high at least 1CLK+

SS

prior to Row active command.

t

3. Can not violate minimum refresh specification.(64ms)

TM Technology Inc. reserves the right P.26

Publication Date: APR. 2003

to change products or specifications without notice. Revision: 0.B

TE

tm

Self Refresh Entry & Exit Cycle

CLOCK

CKE

C S

CH

Preliminary T4312816A

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

*Note2

*Note1

SS

t

SS
SS

SS

SS
SS

*Note3

*Note4

*Note5

SS

t

SS

SS

RCmin

*Note6

RAS

CAS

ADDR

B A

A10/A P

D Q

W E

DQM

SS
SS

SS
SS

SS
SS

SS

SS

SS
SS

Hi-z

Se lf R e fr es h E n try Se lf R e fr es h E x it

SS

SS
SS

SS
SS

Hi-z

SS

SS
SS

SS
SS

SS
SS

SS
SS

SS
SS

SS

SS
SS

SS

*Note7

A u to R efre sh

:Don't care

*Note : TO ENTER SELF REFRESH MODE

1.

CS

, RAS &

CAS

with CKE should be low at the same clock cycle.

2. After 1 clock cycle, all the inputs inculding the system clock can be don’t care except for CKE.

3. The device remains in self refresh mode as long as CKE stays ‘Low’.

Cf.) Once the device enters self refresh mode, minimum

RAS

is required before exit from self refresh.

t

TO EXIT SELF REFRESH MODE

4. System clock restart and be stable before returning CKE high.

5.

CS

starts from high.

6. Minimum tRC is required after CKE going high to complete self refresh exit.

7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the
system uses burst refresh.

TM Technology Inc. reserves the right P.27

Publication Date: APR. 2003

to change products or specifications without notice. Revision: 0.B

TE

tm

Mode Register Set Cycle Auto Refresh Cycle

CLOCK

CH

Preliminary T4312816A

0123456 012345678910

SS

C K E

CS

R A S

C A S

ADDR

DQ

W E

DQM

HIGH

*Note2

*Note1

*Note3

Key Key

Hi-z

HIGH

Hi-z

SS

SS

t

RPC

SS
SS

SS
SS

SS
SS

SS

SS
SS

SS
SS

Auto Refresh New CommandMRS New Command

:Don't care

*Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.

MODE REGISTER SET CYCLE
*Note : 1.
mode register.

2. Minimum 2 clock cycles should be met before new

3. Please refer to Mode Register Set table.

TM Technology Inc. reserves the right P.28
to change products or specifications without notice. Revision: 0.B

CS

, RAS,

CAS

&

WE

activation at the same clock cycle with address key will set internal

RAS activation.

Publication Date: APR. 2003

TE

tm

PACKAGE DIMENSIONS
54 LEAD TSOP-II (400 mil)

CH

Preliminary T4312816A

D

A

A2

2854

E1

E

A1

1

B1

Symbol

A - - 1.2 - - 0.047
A1 0.4 0.5 0.6 0.016 0.020 0.024
A2 - 0.15 - 0.006

B 0.24 0.32 0.40 0.009 0.012 0.016
B1 - 0.8 - 0.0315

C 0.05 0.10 0.15 0.002 0.004 0.006

D 22.12 22.22 22.62 0.871 0.875 0.905

E 11.56 11.76 11.96 0.455 0.463 0.471

E1 10.06 10.16 10.26 0.396 0.400 0.404

θ

Dimension in mm Dimension in inch

Min Nom Max Min Nom Max

0 - 8 0 - 8

B

27

θ

C

TM Technology Inc. reserves the right P.29

Publication Date: APR. 2003

to change products or specifications without notice. Revision: 0.B