Taiwan Memory Technology T4312816A-8S, T4312816A-7.5S, T4312816A-7S, T4312816A-6S, T4312816A-10S Datasheet

TE

tm

SDRAM

FEATURES

3.3V power supply

•

Four banks operation

•

LVTTL compatible with multiplexed address

•

All inputs are sampled at the positive going

•

edge of system clock

Burst Read Single-bit Write operation

•

DQM for masking

•

Auto refresh and self refresh

•

64ms refresh period (4K cycle)

•

MRS cycle with address key programs

•

- CAS Latency ( 2 & 3 )

- Burst Length ( 1 , 2 , 4 , 8 & full page)

- Burst Type (Sequential & Interleave)

Available package type in 54 pin TSOP(II)

•

Operating temperature : 0 ~ +70 °C

•

ORDERING INFORMATION

PART NO.

T4312816A-6S 166 MHz
T4312816A-7S 143 MHz
T4312816A-7.5S 133 MHz
T4312816A-8S 125 MHz
T4312816A-10S 100 MHz

CH

Preliminary T4312816A

MAX

FREQUENCY

TEMPERATURE

0 ~ +70°C
0 ~ +70°C
0 ~ +70°C
0 ~ +70°C
0 ~ +70°C

8M x 16 SDRAM

2M x 16bit x 4Banks Synchronous DRAM

GRNERAL DESCRIPTION

The T4312816A is 134,217,728 bits
synchronous high data rate Dynamic RAM
organized as 4 x 2,097,152 words by 16 bits,
fabricated with high performance CMOS
technology .

Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clockcycle . Range of operating
frequencies , programmable burst length and
programmable latencies allow the same device to
be useful for a variety of high bandwidth , high
performance memory system applications.

PIN ARRANGEMENT (

V

DD

DD

CS

A0
A1
A2
A3

DD

1

2
3
4
5
6
7
8
9
10
11
12
13

14
15
16
17
18
19
20
21
22
23
24
25
26

(400mil x 875m il)

(0.8 mm PIN PITCH)

54 P IN T S O P( II)

DQ0

DDQ

V

DQ1

DQ2

SSQ

V

DQ3

DQ4

DDQ

V

DQ5

DQ6

SSQ

V

DQ7

V

LDQ M

W E
CAS

RAS

BA0
BA1

A10/AP

V

Top View)

Vss

54

DQ15

53

V SSQ

52

DQ14

51

DQ13

50

V

49
48
47
46
45
44
43
42
41
40
39
38
37

36
35
34
33
32
31
30
29
2827

DDQ

DQ12
DQ11
V SSQ

DQ1
0
DQ9

DDQ

V
DQ8
Vss
N.C/RFU
UDQM
CLK
CKE
N.C
A11
A9
A8
A7
A6
A5
A4
Vss

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Publication Date: APR. 2003

to change products or specifications without notice. Revision: 0.B

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tm

BLOCK DIAGRAM

CH

Preliminary T4312816A

I/O Control Output Buffer

CLK

ADD

Bank Select

Refresh Counter

Row Buffeer

Address Register

LCBR

LRA S

Timing Register

Row Decoder

Col. Buffer

Data Input Register

2M x 16
2M x 16

2M x 16
2M x 16

Column D ecoder

Laten c y & Burst Le n g th

Programming Register

Sense AMP

DQi

CAS WE

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L(U)DQ MRASCSCKECLK

Publication Date: APR. 2003

to change products or specifications without notice. Revision: 0.B

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PIN DESCRIPTION

CH

Preliminary T4312816A

PIN NAME

CLK System Clock

CS

CKE Clock Enable

A0 ~ A11 Address

BA0 ~ BA1 Bank Select Address

RAS

CAS

Chip Select

Row Address Strobe

Column Address Strobe

INPUT FUNCTION

Active on the positive going edge to sample all input.
Disables or enables device operation by masking or enabling all input
except CLK,CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11,column address : CA0 ~ CA8
Selects bank to be activated during row address latch time.
Select bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK

RAS

with
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK
with

CAS

low.

low.

WE

L(U)DQM

DQ0 ~ DQ15 Data Input/Output

VDD/VSS Power Supply/Ground

V

DDQ/VSSQ

N.C/RFU

Write Enable

Data Input/Output

Mask

Data Output

Power/Ground

No

Connection/Reserved

for Future Use

Enables column access .
Enables write operation and row precharge.
Latches data in starting from
Makes data output Hi-Z,
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
This pin is recommended to be left No Connection on the device.

CAS, WE

t

after the clock and masks the output.

SHZ

active.

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Publication Date: APR. 2003

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ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit

CH

Preliminary T4312816A

Voltage on Any Pin Relative To Vss VIN,V
Supply Voltage Relative To Vss VDD,V
Short circuit Output Current I
Power Dissipation PD 1 W
Operating Temperature T
Storage Temperature T

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Note :

Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

RECOMMENDED DC OPERATING CONDITIONS

(TA = 0 to +70

Parameter Symbol Min. Typ Max. Unit Notes

Supply Voltage VDD,V

Input High Voltage VIH 2.0 3.0 VDD+0.3V V

Input Low Voltage VIL -0.3 0 0.8 V

Output logic high voltage VOH 2.4 - - V IOH=-4mA

, Voltage referenced to VSS=0V)

°°°°C

3.0 3.3 3.6 V

DDQ

-1.0 to 4.6 V

OUT

-1.0 to 4.6 V

DDQ

50 mA

out

0 to +70

OPR

-55 to +150

stg

C

°

C

°

Output logic low voltage VOL - - 0.4 V IOL=4mA

Input leakage current IIL -1 - 1 uA 1

Output leakage current IOL -1.5 - 1.5 uA 2

Note :

1. Any input 0V

2. Dout = disable, 0V≤ V

VIN ≤ VDD+ 0.3V , all other pin are not under test = 0V.

≤

V

OUT

≤

DD .

CAPACITANCE

(TA =25

RAS,CAS,WE,CS,CKE,LDQM,

,VDD=3.3V, f = 1MHz)

C

°

Pin Symbol Min Max Unit

CLOCK C

ADDRESS C

DQ0 ~ DQ15 C

UDQM

2.5 4.0 pF

CLK

2.5 5.0 pF

ADD

4.0 6.5 pF

OUT

CIN 2.5 5.0 pF

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DC CHARACTERISTICS

CH

Preliminary T4312816A

TA = 0 to 70

, VIH(min)/VIL(max)=2.0V/0.8V

C

°

Parameter Symbol

Operating Current

I

CC1

( One Bank Active)

Precharge Standby

I

CC2

Current in power-

I

down mode

CC2

Precharge Standby

I

Current in non

CC2

power-down mode

I

CC2

Active Standby

I

CC3

Current in power-

I

down mode

CC3

Active Standby

I

Current in non

CC3

power-down mode

I

(One Bank Active)

CC3

Speed version

Unit Test Condition

-6 -7 -7.5 -8 -10

140 120 115 110 100 mA

P 2

mA

PS 2

N 20

mA

NS 8

P 5

mA

PS 4

N 30

mA

NS 20

Burst Length = 1

t

t

≥

RC

RC

CKE≤ VIL(max),

CKE≤ VIL(max),CLK ≤VIL(max),

CKE

≥

Input signals are changed one time during 30ns

CKE≥VIH(min),CLK≤VIL(min),

Input signals are stable

CKE≤ VIL(max),

CKE≤ VIL(max),CLK ≤VIL(max),

CKE≥VIH(min),

Input signals are changed one time during 30ns

CKE≥VIH(min),CLK≤VIL(min),

Input signals are stable

(min) ,

VIH(min),

t

CC

t

(min),IOL= 0 mA

≥

CC

t

=15ns

CC

VIH(min),

≥

CS

t

=15ns

CC

VIH(min),

≥

CS

t

t

CC

t

t

CC

CC

t

CC

=15ns

CC

=∞

t

CC

=15ns

=∞

=∞

=∞

Note

1,3

3

3

3

3

Operating Current

(Burst Mode)

Refresh Current

Self refresh
Current

150 130 125 120 110

I

CC4

150 130 125 120 110

150 130 125 120 110 mA

I

CC5

I

2 mA

CC6

CAS Latency 3

mA

CAS Latency 2

t

RC

CKE≤0.2V

=0 mA,Page Burst

I

OL

All Band Activated

t

t

=

CCD

CCD

t

(min)

≥

RC

Note: 1. Measured with output open. Addresses are changed only one time during

2. Refresh period is 64ms. Addresses are changed only one time during

3.

t

: Clock cycle time.

CC

t

: Row cycle time.

RC

t

: Column address to column address delay time.

CCD

t

CC

(min)

t

CC

(min)

(min)

.

1,3

2,3

.

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to change products or specifications without notice. Revision: 0.B

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AC OPERATING CONDITIONS

(VDD=3.3V ±0.3V ,TA= 0 to 70

Input levels (VIH/VIL) 2.4 / 0.4 V

Input timing measurement reference level 1.4 V

CH

Preliminary T4312816A

)

C

°

Parameter Value Unit

Input rise and fall time

Output timing measurement reference level 1.4 V

Output load condition See Fig.2

t

r / tf = 1 / 1

ns

3.3V

Output

870 ohm

1200 ohm

ZO=50 ohmOutput

VOH(DC)=2.4,IOH=-4mA

VOL(DC)=0.4,IOL=4mA

30pf

Vtt=1.4v

50 ohm

30pf

(Fig.1) DC Output Load Circuit (Fig.2)AC Output Load Circuit

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OPERATING AC PARAMETER

(AC opterating conditions unless otherwise noted)

Row active to row active delay

RAS to CAS delay

CH

Preliminary T4312816A

Parameter Symbol

t

(min)

RRD

t

(min)

RCD

Speed Version

Unit Note

-6 -7 -7.5 -8 -10

12 14 15 16 20 ns 1

15 15 18 20 20 ns 1

Row precharge time

Row active time

Row cycle time

Last data in to new col. Address delay

Last data in to row precharge

Last data in to burst stop

Col. Address to col. Address delay

Number of valid output data

t

(min)

RP

t

(min)

RAS

t

RAS

t

(min)

RC

t

CDL

t

RDL

t

BDL

t

CCD

CAS latency=3 1
CAS latency=2 1

(max)

(min)

(min)

(min)

(min)

15 15 20 20 20 ns 1

42 42 45 48 50 ns 1

120K ns

60 63 65 68 70 ns 1

1 CLK 2

2 CLK 2

1 CLK 2

1 CLK 3

ea 4

Note:

1. The minimum number of clock cycles is determined by dividing the minimum time required

with clock cycle time and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is
CL + BL-2 clocks.

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Publication Date: APR. 2003

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AC CHARACTERISTICS

(AC opterating conditions unless otherwise noted)

CLK cycle time

CH

Preliminary T4312816A

-6 -7 -7.5 -8 -10

t

Min Max Min Max Min Max Min Max Min Max

CC

8 9 9 10 10

Parameter

CAS Latency = 3 6 1K 7 1K 7.5 1K 8 1K 10 1K

CAS Latency = 2

Symbol

Unit Note

ns 1

CLK to valid
Output delay

Output data hold time
CLK high pulse width
CLK low pulse width

Input setup time
Input hold time
CLK to output in Low-Z

CLK to output in
Hi-Z

CAS Latency = 3 - 5.5 - 6 6 - 6 - 7 ns

t

SAC

CAS Latency = 2

t

OH

t

CH

t

CL

t

SS

t

SH

t

SLZ

CAS Latency = 3 - 5.5 - 6 6 - 6 - 7 ns

t

SHZ

CAS Latency = 2

- 6 - 6 6 - 7 - 9 ns
2 2.5 2.5 2.5 2.5 ns 2
2 2.5 2.5 3 3 ns 3
2 2.5 2.5 3 3 ns 3

1.5 1.75 1.75 2 2.5 ns 3
1 1 1 1 1 ns 3
1 1 1 1 1 ns 2

- 6 - 6 6 - 7 - 9 ns

Note:

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf)=1ns.

If tr & tf is longer than 1ns,transient time compensation should be considered,
i.e.,[(tr+tf)/2-1]ns should be added to the parameter.

1

TM Technology Inc. reserves the right P.8
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FREQUENCY vs. AC PARAMETER RELATIONAHIP TABLE

T4312816A-6S (Unit : number of clock)

Frequency

166MHz(6.0ns)
143MHz(7.0ns) 3 9 6 3 2 3 1 1 2
125MHz(8.0ns) 2 9 6 2 2 2 1 1 2

111MHz(9.0ns) 2 7 5 2 2 2 1 1 2

100MHz(10.0ns) 2 7 5 2 2 2 1 1 2

T4312816A-7S (Unit : number of clock)

Frequency

143MHz(7.0ns)
125MHz(8.0ns) 3 9 6 2 2 2 1 1 2
111MHz(9.0ns) 2 8 5 2 2 2 1 1 2

100MHz(10.0ns) 2 7 5 2 2 2 1 1 2

83MHz(12.0ns) 2 6 4 2 2 2 1 1 2

T4312816A-7.5S (Unit : number of clock)

Frequency

133MHz(7.5ns)
125MHz(8.0ns) 3 9 6 3 2 3 1 1 2
111MHz(9.0ns) 2 8 5 3 2 2 1 1 2

100MHz(10.0ns) 2 7 5 2 2 2 1 1 2

83MHz(12.0ns) 2 6 4 2 2 2 1 1 2

CH

Preliminary T4312816A

CAS

Latency

3 10 7 3 2 3 1 1 2

CAS

Latency

3 9 6 3 2 3 1 1 2

CAS

Latency

3 9 6 3 2 3 1 1 2

RC

t

60ns 42ns 15ns 12ns 15ns 6ns 6ns 12ns

RC

t

63ns 42ns 15ns 14ns 15ns 7ns 7ns 14ns

RC

t

65ns 45ns 20ns 15ns 18ns 7.5ns 7.5ns 15ns

RAS

t

RAS

t

RAS

t

RP

t

RP

t

RP

t

RRD

t

RRD

t

RRD

t

RCD

t

RCD

t

RCD

t

CCD

t

CCD

t

CCD

t

CDL

t

CDL

t

CDL

t

RDL

t

RDL

t

RDL

t

T4312816A-8S (Unit : number of clock)

Frequency

125MHz(8.0ns)
111MHz(9.0ns) 3 9 6 3 2 3 1 1 2

100MHz(10.0ns) 2 7 5 2 2 2 1 1 2

83MHz(12.0ns) 2 6 4 2 2 2 1 1 2
75MHz(13.0ns) 2 6 4 2 2 2 1 1 2

CAS

Latency

3 9 6 3 2 3 1 1 2

RC

t

68ns 48ns 20ns 16ns 20ns 8ns 8ns 16ns

RAS

t

RP

t

RRD

t

RCD

t

CCD

t

CDL

t

RDL

t

T4312816A-10S (Unit : number of clock)

Frequency

100MHz(10.0ns)

83MHz(12.0ns) 2 7 5 2 2 2 1 1 2
75MHz(13.0ns) 2 6 4 2 2 2 1 1 2
66MHz(15.0ns) 2 6 4 2 2 2 1 1 2
60MHz(16.7ns) 2 5 3 2 2 2 1 1 Note 1

Note : 1.

2. Clock count formula : clock ≥

RDL ≥

t

CAS

Latency

2 7 5 2 2 2 1 1 2

16.7ns is recommended for T4312816A

RC

t

70ns 50ns 20ns 20ns 20ns 10ns 10ns 20ns

RAS

t

RP

t

RRD

t

valuebase
periodclock

(round off whole number).

RCD

t

CCD

t

CDL

t

RDL

t

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