Taiwan Memory Technology T35L6464A-5L, T35L6464A-5Q Datasheet

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T35L6464A

SYNCHRONOUS
BURST SRAM

FEATURES

•

Fast Access times: 5, 6, 7, and 8ns

• Fast clock speed: 100, 83, 66, and 50 MHz

•

Provide high performance 3-1-1-1 access rate

•

•

•

OE

Fast
Single 3.3V +10% / -5V power supply
Common data inputs and data outputs

• BYTE WRITE ENABLE and GLOBAL

WRITE control

•

Five chip enables for depth expansion and

address pipelining

•

Address, control, input, and output pipelined

registers

• Internally self-timed WRITE cycle

•

WRITE pass-through capability

•

Burst control pins ( interleaved or linear burst

sequence)

•

High density, high speed packages

•

Low capacitive bus loading

• High 30pF output drive capability at rated access

time

•

SNOOZE MODE for reduced power standby

•

Single cycle disable ( PentiumTM BSRAM

compatible )

OPTIONS

TIMING MARKING
5ns access/10ns cycle -5
6ns access/12ns cycle -6
7ns access/15ns cycle -7
8ns access/20ns cycle -8

Package
128-pin QFP Q
128-pin LQFP L

Part Number Examples

PART NO. Pkg. BURST SEQUENCE
T35L6464A-5Q Q Interleaved

T35L6464A-5L L Linear (MODE=GND)

access times: 5 and 6ns

(MODE=NC or VCC)

64K x 64 SRAM

3.3V SUPPLY, FULLY REGISTERED AND OUTPUTS,
BURST COUNTER

PIN ASSIGNMENT

CE3

VCCQ

CE2

CE3

CE2

123124 116115114113112111110109118119120121122 117128127126125

VSSQ

DQ33

2

DQ34

3

DQ35

4

DQ36

5

DQ37

6

DQ38

7

DQ39

8

DQ40

9

DQ41

10

DQ42

11

DQ43

12

VCCQ

13

VSSQ

14

DQ44

15

DQ45

16

DQ46

17

DQ47

18

DQ48

19

DQ49

20

DQ50

21

DQ51

22

DQ52

23

DQ53

24

VCCQ

25

VSSQ

26

DQ54

27

DQ55

28

DQ56

29

DQ57 DQ8

30
DQ58 31
DQ59 32
DQ60 33
DQ61 34
DQ62 35
DQ63 36
DQ64 37

VCCQ 38

39 49484746454443424140 5756555453525150 58

NC

A14

A15

VSSQ

MODE

BW7

BW8

CE

VCC

VSS

128-pin QFP

128-pin LQFP

A11

A13

A12

VSS

VCC

GENERAL DESCRIPTION

The Taiwan Memory Technology Synchronous
Burst RAM family employs: high-speed, low power
CMOS design using advanced triple-layer
polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two
high valued resistors.

The T35L6464A SRAM integrates 65536 x 64
SRAM cells with advanced synchronous peripheral
circuitry and a 2-bit counter for internal burst
operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered
clock input (CLK). The synchronous inputs include
all addresses, all data inputs, three active LOW

chip enable (CE,
chip enables (CE2 and CE3) , burst control inputs

CE2

(Top View)

CLK

OE

BW5

BW6

BWE

or

A9

A8

NC

A10

and

BW3

BW4

GW

VCC

VSS

BW1

BW2

108107106105104103

A3

A4

A5A6A7

VSS

VCC

CE3

), two additional

ADSC

ADSP

6362616059 64

A0A1A2

ADV

ZZ

102
101
100

VSSQ

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73

71
70
69
68
67
66
65

VCCQ

VCCQ1
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
VSSQ
VCCQ
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
VSSQ
VCCQ
DQ11
DQ10
DQ9

DQ772
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
VSSQ

Taiwan Memory Technology, Inc. reserves the right P. 1 Publication Date: AUG. 1998
to change products or specifications without notice. Revision: E

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BW8

BWE

BW3

BW1

BW2

BW3

BW4, BW5

T35L6464A

GENERAL DESCRIPTION

ADSC, ADSP

(

BW2, BW3, BW4, BW5, BW6, BW7

and

Asynchronous inputs include the output enable
(OE) , Snooze enable (ZZ) and burst mode control
(MODE). The data outputs (Q), enabled by

are also asynchronous.

Addresses and chip enables are registered with
either address st atus processor (
status controller (
burst addresses can be internally generated as
controlled by the burst advance pin (

Address, data inputs, and write controls are
registered on-chip to initiate self-timed WRITE
cycle. WRITE cycles can be one to eight bytes
wide

ADV

,and

), write enables (

), and global write (GW).

ADSP

) or address

ADSC

) input pins. Subsequent

ADV

).

BW1

OE

FUNCTIONAL BLOCK DIAGRAM

14

A0-A15

MODE

ADV
CLK

ADSC

ADSP

16

ADDRESS

REGISTER

16

A0 A1

DO D1 Q1

BINARY

COUNTER

& LOGIC

LOAD Q0

CLR

A1'

A0'

(continued)

,
,

,

as controlled by the write control inputs.

Individual byte write allows individual byte to be
written.

BW1

controls DQ1-DQ8.

controls DQ9-DQ16.

BW4

controls DQ25-DQ32.

DQ33-DQ40.

BW7

controls DQ49-DQ56.

BW6

DQ57-DQ64.

BW6, BW7
BWE

being LOW.

and

BW8

controls DQ17 -DQ24.

BW5

controls DQ41-DQ48.

BW8

,

,

,

can be active only with

GW

being LOW causes all

BW2

controls

controls

,

bytes to be written. WRITE pass-through
capability allows written data available at the output
for the immediately next READ cycle. This
device also incorporates pipelined enable circuit for
easy depth expansion without penalizing system
performance.

16

8

8

8

8

8

8

8

8

BYTE 8

WRITE DRIVER

BYTE 7

WRITE DRIVER

BYTE 6

WRITE DRIVER

BYTE 5

WRITE DRIVER

BYTE 4

WRITE DRIVER

BYTE 3

WRITE DRIVER

BYTE 2

WRITE DRIVER

BYTE 1

WRITE DRIVER

8

8

8

8

8

8

8

8

64K x 8 x 8

MEMORY

ARRAY

64 64

8

SENSE

AMPS

OUTPUT

REGISTERS

OUTPUT

BUFFERS

64

INPUT

REGISTERS

DQ1

DQ64

.
.
.

BW4

BW3

BW2

BW1

BWE

BW8

BW7

BW6

BW5

GW

CE2
CE3
CE2
CE3

BYTE 8

WRITE REGISTER

BYTE 7

WRITE REGISTER

BYTE 6

WRITE REGISTER

BYTE 5

WRITE REGISTER

BYTE 4

WRITE REGISTER

BYTE 3

WRITE REGISTER

BYTE 2

WRITE REGISTER

BYTE 1

WRITE REGISTER

CE

OE

Chip

Enable

ENABLE

REGISTER

PIPELINED

ENABLE

Note: The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin

descriptions and timing diagrams for detailed information.

Taiwan Memory Technology, Inc. reserves the right P. 2 Publication Date: AUG. 1998
to change products or specifications without notice. Revision: E

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BW5

BW6

BW7

GW

ADSP

T35L6464A

PIN DESCRIPTIONS

QFP PINS SYM. TYPE DESCRIPTION

42-44, 47 -51, A0- Input- Addresses: These inputs are registered and must meet the setup and

53-57, 60-62 A15 Synchronous hold times around the rising edge of CLK. The burst counter

107, 108, 111,

112,117 -120 BW8 Synchronous a READ cycle. BW1 controls DQ1-DQ8.

114 BWE Input- Write Enable: This active LOW input gates byte write operations

Synchronous and must meet the setup and hold times around the rising edge of

113

Synchronous to occur independent of the BWE and BWn lines and must meet
the setup and hold times around the rising edge of CLK.

115 CLK Input- Clock: This signal registers the addresses, data, chip enables, write

Synchronous control and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock's rising

121 CE Input- Synchronous Chip Enable: This active LOW input is used to enable

Synchronous the device and conditions internal use of
sampled only when a new external address is loaded.

124 CE2 Input- Synchronous Chip Enable: This active LOW input is used to enable

Synchronous the device. This input is sampled only when a new external address
is loaded. This input can be used for memory depth expansion.

126 CE2 Input- Synchronous Chip Enable: This active HIGH input is used to enable

Synchronous the device. This input is sampled only when a new external address
is loaded. This input can be used for memory depth expansion.

125 CE3 Input- Synchronous Chip Enable: This active LOW input is used to enable

Synchronous the device. This input is sampled only when a new external address
is loaded. This input can be used for memory depth expansion.

127 CE3 Input- Synchronous Chip Enable: This active HIGH input is used to enable

Synchronous the device. This input is sampled only when a new external address
is loaded. This input can be used for memory depth expansion.

116 OE Input Output enable: This active LOW asynchronous input enables the

data output drivers.

BW1

-

Input- Byte Write: A byte write is LOW for a WRITE cyle and HIGH for

Input- Global Write: This active LOW input allows a full 64-bit WRITE

generates internal addresses associated with A0 and A1,during burst
cycle and wait cycle.

BW2 controls DQ9-

DQ16. BW3 controls DQ17 -DQ24. BW4 controls DQ25-DQ32.

controls DQ33 -DQ40.
controls DQ49-DQ56.
high impedance if either of these inputs are LOW ,conditioned by

BWE being LOW.

CLK.

edge.

BW8 controls DQ57 -DQ64. Data I/O are

controls DQ41-DQ48.

. This input is

Taiwan Memory Technology, Inc. reserves the right P. 3 Publication Date: AUG. 199 8
to change products or specifications without notice. Revision: E

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ADSP

T35L6464A

PIN DESCRIPTIONS (continued)

QFP PINS SYM. TYPE DESCRIPTION

104 ADV Input- Address Advance: This active LOW input is used to control the

Synchronous internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).

105

Synchronous being LOW, causes a new external address to be registered and a
READ cycle is initiated using the new address.

106 ADSC

Synchronous be de- selected or selected along with new external address to be

write control inputs.

41 MODE

Static selects LINEAR BURST. A NC or HIGH on this pin selects
INTERLEAVED BURST. Do not alter input state while device is

63 ZZ Input Snooze Enable: This active HIGH asynchronous input causes the

device to enter a low -power standby mode in which all data in the

2-12,15-24, DQ1 - Input/ Data Inputs/Outputs: First Byte is DQ1-DQ8. Second Byte is DQ9-

27-37,66-76, DQ64 Output DQ16. Third Byte is DQ17-DQ24. Fourth Byte is DQ25- DQ32.

79-88,91-101 Fifth Byte is DQ 33- DQ40. Sixth Byte is DQ41- DQ48. Seventh

Byte is DQ49- DQ56. Eighth Byte is DQ57- DQ64. Input data

must meet setup and hold times around the rising edge of CLK.
45,58,109,122 VCC Supply Power Supply: 3.3V +10%/-5%.
46,59,110,123 VSS Ground Ground: GND

13,25,38,64, VCCQ I/O Supply Isolated Output Buffer Supply: 3.3V +10%/-5%.

77,89,102,128

1,14,26,39,65,

78,90,103

40,52 NC - No Connect: These signals are not internally conntected.

VSSQ I/O Ground Output Buffer Ground: GND

Input- Address Status Processor: This active LOW input, along withCE

Input- Address Status Controller:This active LOW input causes device to

registered. A READ or WRITE cycle is initiated depending upon

Input- Mode: This input selects the burst sequence. A LOW on this pin

operating.

memory array is retained.

Taiwan Memory Technology, Inc. reserves the right P. 4 Publication Date: AUG. 199 8
to change products or specifications without notice. Revision: E

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T35L6464A

INTERLEAVED BURST ADDRESS TABLE (MODE = NC/Vcc)

First Address

(external)

A...A00 A...A01 A...A10 A...A11
A...A01 A...A00 A...A11 A...A10
A...A10 A...A11 A...A00 A...A01
A...A11 A...A10 A...A01 A...A00

Second Address

(internal)

Third Address

(internal)

Fourth Address

(internal)

LINEAR BURST ADDRESS TABLE (MODE = GND)

First Address

(external)

A...A00 A...A01 A...A10 A...A11
A...A01 A...A10 A...A11 A...A00
A...A10 A...A11 A...A00 A...A01
A...A11 A...A00 A...A01 A...A10

Second Address

(internal)

Third Address

(internal)

Fourth Address

(internal)

PARTIAL TRUTH TABLE FOR READ/WRITE

Function

READ H H X X X X X X X X
READ H L H H H H H H H H
WRITE byte 1 H L L H H H H H H H
WRITE byte 2 H L H L H H H H H H
WRITE byte 3 H L H H L H H H H H
WRITE byte 4 H L H H H L H H H H
WRITE byte 5 H L H H H H L H H H
WRITE byte 6 H L H H H H H L H H
WRITE byte 7 H L H H H H H H L H
WRITE byte 8 H L H H H H H H H L
WRITE all byte H L L L L L L L L L
WRITE all byte L X X X X X X X X X

GW BWE BW1 BW2 BW3

BW4 BW5 BW6 BW7 BW8

Taiwan Memory Technology, Inc. reserves the right P. 5 Publication Date: AUG. 199 8
to change products or specifications without notice. Revision: E