Taiwan Memory Technology T35L6432B-12T, T35L6432B-10Q Datasheet

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CH

T35L6432B

SYNCHRONOUS
BURST SRAM

Access

time

Cycle

time

9ns 10ns 11ns 12ns

10.5ns 15ns 15ns 15ns

FEATURES

• Fast Access times: 9 / 10 / 11 / 12 ns

• Single 3.3V (+0.3V/-0.165V) power supply

• Common data inputs and data outputs

• Individual BYTE WRITE ENABLE and

GLOBAL WRITE control

• Three chip enables for depth expansion and
address pipelining

• Clock-controlled and registered address, data
I/Os and control signals

• Internally self-timed WRITE CYCLE

• Burst control pins ( interleaved or linear burst

sequence)

• High 30pF output drive capability at rated access

time

• SNOOZE MODE for reduced power standby

• Burst Sequence :

- Interleaved (MODE=NC or VCC)

- Linear (MODE=GND)

OPTIONS

MARKING -9 -10 -11 -12

Flow-

through

2-1-1-1

PACKAGE package code

100-pin QFP Q
100-pin TQFP T

Part Number Examples

PART NO. speed Package
T35L6432B-10Q 10ns QFP
T35L6432B-12T 12ns TQFP

64K x 32 SRAM

Flow-Through Burst Mode

GENERAL DESCRIPTION

The Taiwan Memory Technology Synchronous
Burst RAM family employs high-speed, low power
CMOS design using advanced triple-layer polysilicon,
double-layer metal technology. Each memory cell
consists of four transistors a nd two high valued re sistors.

The T35L6432B SRAM integrates 65536 x 32
SRAM cells with advanced synchronous peripheral
circuitry and a 2-bit counter for internal burst operation.
All synchronous inputs are gated by registers controlled
by a positive-edge-triggered clock input (CLK). The
synchronous inputs include all addresses, all data inputs,

address-pipelining chip enable (
expansion chip enables (
inputs (
(
global write (

(
(MODE). The data outputs (Q), enabled by

also asynchronous.
Addresses and chip enables are registered with

either address status processor (
status controller (

addresses can be internally generated as controlled by
the burst advance pin (

to initiate self-timed WRITE cycle. WRITE cycles
can be one to four bytes wide as controlled by the write
control inputs. Individual byte write allows individual

byte to be written.

BW2

DQ 24.

BW2, BW3
BWE

bytes to be written. WRITE pass-through capability
allows written data available at the output for the
immediately next READ cycle. This device also
incorporates pipelined enable circuit for easy depth
expansion without penalizing system performance.

ADSC, ADSP

BW1, BW2, BW3, BW4

GW

Asynchronous inputs include the output enable

OE

), Snooze enable (ZZ) and burst mode control

Address and write controls are registered on-chip

controls DQ9-DQ16.

BW4

, and

being LOW.

CE2

and CE2), burst control

ADV

, and

).

ADSC

) input pins. Subsequent burst

ADV

).

BW1

controls DQ1-DQ8.

BW3

controls DQ25-DQ32.

BW4

can be active only with

GW

being LOW causes all

CE

), write enables

, and

ADSP

BWE

) or address

controls DQ17-

), depth-

), and

OE

, are

BW1

,

Taiwan Memory Technology, Inc. reserves the right P. 1 Publication Date: JUL. 2002
to change products or specifications without notice. Revision: A

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FUNCTIONAL BLOCK DIAGRAM

CH

T35L6432B

A0-A15

MODE

ADV

CLK

ADSC

ADSP

BWE

BW4

BW3

14

CLR

16

A0

BINARY

COUNTER

& LOGIC

A1

Q1

Q0

16

WRITE REGISTER

WRITE REGISTER

WRITE REGISTER

ADDRESS
REGISTER

BYTE 4

BYTE 3

BYTE 2

A1'

A0'

8

8

8

16

BYTE 4

W R IT E DRIVER

BYTE 3

W R IT E DRIVER

BYTE 2

W R IT E DRIVER

8

8

8

64K x 8 x 4
MEMORY

ARRAY

32 32

SENSE

AMPS

OUTPUT

BUFFERS

32

DQ1

.
.
.

DQ32

BW2

BW1

GW

CE2
CE2

8

BYTE 1

WRITE REGISTER

ENABLE

CE

OE

REGISTER

BYTE 1

WRITE DRIVER

8

INPUT

REGISTERS

4

Note: The Functional Block Diagram illustrates simplified device operation. See Truth Table,

pin descriptions and timing diagrams for detailed information.

Taiwan Memory Technology, Inc. reserves the right P. 2 Publication Date: JUL. 2002
to change products or specifications without notice. Revision: A

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PIN ASSIGNMENT

CH

T35L6432B

A7

A6

CE

CE2

(Top View)

CE2

BW1

BW2

BW3

BW4

9596 88 87 86 85 84 83 82 819091929394 89100 99 98 97

A9

OE

VSS

VCC

GW

CLK

BWE

ADSC

A8

ADV

ADSP

NC
DQ17
DQ18

VCCQ

VSSQ
DQ19
DQ20
DQ21
DQ22
VSSQ

VCCQ

DQ23
DQ24

NC

VCC

NC

VSS
DQ25
DQ26

VCCQ

VSSQ
DQ27
DQ28
DQ29
DQ30
VSSQ

VCCQ

DQ31
DQ32

NC NC

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31 41403938373635343332 4948474645444342 50

100-pin QF P

or

100-pin TQ FP

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

NC
DQ16
DQ15

VCCQ

VSSQ
DQ14
DQ13
DQ12
DQ11
VSSQ

VCCQ

DQ10

DQ9

VSS

NC

VCC

ZZ
DQ8
DQ7

VCCQ

VSSQ

DQ6
DQ5
DQ4
DQ3

VSSQ

VCCQ

DQ2
DQ1

A5

MODE

NC

NC

NC

NC

A10

A11

A12

VSS

VCC

A13

NC

A14

A15

A0

A1

A2

A3

A4

Taiwan Memory Technology, Inc. reserves the right P. 3 Publication Date: JUL. 2002
to change products or specifications without notice. Revision: A

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PIN DESCRIPTIONS

PINS SYM. TYPE DESCRIPTION

32-37, 44-49,

81, 82, 99,

100,

93-96

87

CH

T35L6432B

Addresses: These inputs are registered and must meet the setup and

A0-A15

BW1
BW2
BW3
BW4

BWE

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

hold times around the rising edge of CLK. The burst counter
generates internal addresses associated with A0 and A1, during
burst cycle and wait cycle.

Byte Writes: A byte write is LOW for a WRITE cyle and HIGH for
a READ cycle.
DQ16.
DQ32. Data I/O are high impedance if either of these inputs are
LOW , conditioned by

Write Enable: This active LOW input gates byte write operations
and must meet the setup and hold times around the rising edge o
CLK.

BW3

BW1

controls DQ1-DQ8.

controls DQ17-DQ24.

being LOW.

BWE

BW2

BW4

controls DQ9-

controls DQ25-

88

89 CLK

98

92

97 CE2

86

GW

CE

CE2

OE

Synchronous

Synchronous

Synchronous

Synchronous

Synchronous

Input-

Input-

Input-

Input-

Input-

Input

Global Write: This active LOW input allows a full 32-bit WRITE to
occur independent of the
the setup and hold times around the rising edge of CLK.

Clock: This signal registers the addresses, data, chip enables,
writecontrol and burst control inputs on its rising edge. All
synchronous inputs must meet setup and hold times around the
clock's rising edge.
Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions internal use of
sampled only when a new external address is loaded.

Synchronous Chip Enable: This active LOW input is used to enable
the device. This input is sampled only when a new external address
is loaded. This input can be used for memory depth expansion.

Synchronous Chip Enable: This active HIGH input is used to enable
the device. This input is sampled only when a new external address
is loaded. This input can be used for memory depth expansion.

Output enable: This active LOW asynchronous input enables the
data output drivers.

BWE

and

BWn

lines and must meet

ADSP

. This input is

83

84

Taiwan Memory Technology, Inc. reserves the right P. 4 Publication Date: JUL. 2002
to change products or specifications without notice. Revision: A

ADV

ADSP

Input-

Synchronous

Input-

Synchronous

Address Advance: This active LOW input is used to control the
internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).

Address Status Processor: This active LOW input, along with
being LOW, causes a new external address to be registered and a
READ cycle is initiated using the new address.

CE

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PIN DESCRIPTIONS

QFP PINS SYM. TYPE DESCRIPTION

2, 3, 6-9, 12, 13,

18, 19, 22-25,

28, 29, 52, 53,

56-59, 62, 63,
68, 69, 72-75,

78, 79,

CH

T35L6432B

(continued)

85

31 MODE

64 ZZ Input

ADSC

DQ1-

DQ32

Input-

Synchronous

Input-

Static

Input/

Output

Address Status Controller:This active LOW input causes
device to be deselected or selected along with new external
address to be registered. A READ or WRITE cycle is
initiated depending upon write control inputs.

Mode: This input selects the burst sequence. A LOW on this
pin selects LINEAR BURST. A NC or HIGH on this pin
selects INTERLEAVED BURST. Do not alter input state
while device is operating.

Snooze Enable: This active HIGH asynchronous input causes
the device to enter a low-power standby mode in which all
data in the memory arry is retained.

Data Inputs/Outputs: First Byte is DQ1-DQ8. Second Byte is
DQ9-DQ16. Third Byte is DQ17-DQ24. Fourth Byte is DQ25­DQ32. Input data must meet setup and hold times around the
rising edge of CLK.

15,41,65,91 VCC Supply Power Supply: 3.3V (+0.3V/-0.165V)
17,40,67,90 VSS Ground Ground: GND

4,11,20,27,54,

61,70,77

5,10,21,26,55,

60,71,76

1,14,16,30,38,

39,42,43,50,51,

66,80

VCCQ I/O Supply Output Buffer Supply: 3.3V (+0.3V/-0.165V)

VSSQ I/O Ground Output Buffer Ground: GND

NC - No Connect: These signals are not internally conntected.

Taiwan Memory Technology, Inc. reserves the right P. 5 Publication Date: JUL. 2002
to change products or specifications without notice. Revision: A