tm
TE
CH
T35L6432B
SYNCHRONOUS
BURST SRAM
Access
time
Cycle
time
9ns 10ns 11ns 12ns
10.5ns 15ns 15ns 15ns
FEATURES
• Fast Access times: 9 / 10 / 11 / 12 ns
• Single 3.3V (+0.3V/-0.165V) power supply
• Common data inputs and data outputs
• Individual BYTE WRITE ENABLE and
GLOBAL WRITE control
• Three chip enables for depth expansion and
address pipelining
• Clock-controlled and registered address, data
I/Os and control signals
• Internally self-timed WRITE CYCLE
• Burst control pins ( interleaved or linear burst
sequence)
• High 30pF output drive capability at rated access
time
• SNOOZE MODE for reduced power standby
• Burst Sequence :
- Interleaved (MODE=NC or VCC)
- Linear (MODE=GND)
OPTIONS
MARKING -9 -10 -11 -12
Flow-
through
2-1-1-1
PACKAGE package code
100-pin QFP Q
100-pin TQFP T
Part Number Examples
PART NO. speed Package
T35L6432B-10Q 10ns QFP
T35L6432B-12T 12ns TQFP
64K x 32 SRAM
Flow-Through Burst Mode
GENERAL DESCRIPTION
The Taiwan Memory Technology Synchronous
Burst RAM family employs high-speed, low power
CMOS design using advanced triple-layer polysilicon,
double-layer metal technology. Each memory cell
consists of four transistors a nd two high valued re sistors.
The T35L6432B SRAM integrates 65536 x 32
SRAM cells with advanced synchronous peripheral
circuitry and a 2-bit counter for internal burst operation.
All synchronous inputs are gated by registers controlled
by a positive-edge-triggered clock input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining chip enable (
expansion chip enables (
inputs (
(
global write (
(
(MODE). The data outputs (Q), enabled by
also asynchronous.
Addresses and chip enables are registered with
either address status processor (
status controller (
addresses can be internally generated as controlled by
the burst advance pin (
to initiate self-timed WRITE cycle. WRITE cycles
can be one to four bytes wide as controlled by the write
control inputs. Individual byte write allows individual
byte to be written.
BW2
DQ 24.
BW2, BW3
BWE
bytes to be written. WRITE pass-through capability
allows written data available at the output for the
immediately next READ cycle. This device also
incorporates pipelined enable circuit for easy depth
expansion without penalizing system performance.
ADSC, ADSP
BW1, BW2, BW3, BW4
GW
Asynchronous inputs include the output enable
OE
), Snooze enable (ZZ) and burst mode control
Address and write controls are registered on-chip
controls DQ9-DQ16.
BW4
, and
being LOW.
CE2
and CE2), burst control
ADV
, and
).
ADSC
) input pins. Subsequent burst
ADV
).
BW1
controls DQ1-DQ8.
BW3
controls DQ25-DQ32.
BW4
can be active only with
GW
being LOW causes all
CE
), write enables
, and
ADSP
BWE
) or address
controls DQ17-
), depth-
), and
OE
, are
BW1
,
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to change products or specifications without notice. Revision: A
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tm
FUNCTIONAL BLOCK DIAGRAM
CH
T35L6432B
A0-A15
MODE
ADV
CLK
ADSC
ADSP
BWE
BW4
BW3
14
CLR
16
A0
BINARY
COUNTER
& LOGIC
A1
Q1
Q0
16
WRITE REGISTER
WRITE REGISTER
WRITE REGISTER
ADDRESS
REGISTER
BYTE 4
BYTE 3
BYTE 2
A1'
A0'
8
8
8
16
BYTE 4
W R IT E DRIVER
BYTE 3
W R IT E DRIVER
BYTE 2
W R IT E DRIVER
8
8
8
64K x 8 x 4
MEMORY
ARRAY
32 32
SENSE
AMPS
OUTPUT
BUFFERS
32
DQ1
.
.
.
DQ32
BW2
BW1
GW
CE2
CE2
8
BYTE 1
WRITE REGISTER
ENABLE
CE
OE
REGISTER
BYTE 1
WRITE DRIVER
8
INPUT
REGISTERS
4
Note: The Functional Block Diagram illustrates simplified device operation. See Truth Table,
pin descriptions and timing diagrams for detailed information.
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to change products or specifications without notice. Revision: A
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tm
PIN ASSIGNMENT
CH
T35L6432B
A7
A6
CE
CE2
(Top View)
CE2
BW1
BW2
BW3
BW4
9596 88 87 86 85 84 83 82 819091929394 89100 99 98 97
A9
OE
VSS
VCC
GW
CLK
BWE
ADSC
A8
ADV
ADSP
NC
DQ17
DQ18
VCCQ
VSSQ
DQ19
DQ20
DQ21
DQ22
VSSQ
VCCQ
DQ23
DQ24
NC
VCC
NC
VSS
DQ25
DQ26
VCCQ
VSSQ
DQ27
DQ28
DQ29
DQ30
VSSQ
VCCQ
DQ31
DQ32
NC NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 41403938373635343332 4948474645444342 50
100-pin QF P
or
100-pin TQ FP
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQ16
DQ15
VCCQ
VSSQ
DQ14
DQ13
DQ12
DQ11
VSSQ
VCCQ
DQ10
DQ9
VSS
NC
VCC
ZZ
DQ8
DQ7
VCCQ
VSSQ
DQ6
DQ5
DQ4
DQ3
VSSQ
VCCQ
DQ2
DQ1
A5
MODE
NC
NC
NC
NC
A10
A11
A12
VSS
VCC
A13
NC
A14
A15
A0
A1
A2
A3
A4
Taiwan Memory Technology, Inc. reserves the right P. 3 Publication Date: JUL. 2002
to change products or specifications without notice. Revision: A
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f
tm
PIN DESCRIPTIONS
PINS SYM. TYPE DESCRIPTION
32-37, 44-49,
81, 82, 99,
100,
93-96
87
CH
T35L6432B
Addresses: These inputs are registered and must meet the setup and
A0-A15
BW1
BW2
BW3
BW4
BWE
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
hold times around the rising edge of CLK. The burst counter
generates internal addresses associated with A0 and A1, during
burst cycle and wait cycle.
Byte Writes: A byte write is LOW for a WRITE cyle and HIGH for
a READ cycle.
DQ16.
DQ32. Data I/O are high impedance if either of these inputs are
LOW , conditioned by
Write Enable: This active LOW input gates byte write operations
and must meet the setup and hold times around the rising edge o
CLK.
BW3
BW1
controls DQ1-DQ8.
controls DQ17-DQ24.
being LOW.
BWE
BW2
BW4
controls DQ9-
controls DQ25-
88
89 CLK
98
92
97 CE2
86
GW
CE
CE2
OE
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input-
Input-
Input-
Input-
Input-
Input
Global Write: This active LOW input allows a full 32-bit WRITE to
occur independent of the
the setup and hold times around the rising edge of CLK.
Clock: This signal registers the addresses, data, chip enables,
writecontrol and burst control inputs on its rising edge. All
synchronous inputs must meet setup and hold times around the
clock's rising edge.
Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions internal use of
sampled only when a new external address is loaded.
Synchronous Chip Enable: This active LOW input is used to enable
the device. This input is sampled only when a new external address
is loaded. This input can be used for memory depth expansion.
Synchronous Chip Enable: This active HIGH input is used to enable
the device. This input is sampled only when a new external address
is loaded. This input can be used for memory depth expansion.
Output enable: This active LOW asynchronous input enables the
data output drivers.
BWE
and
BWn
lines and must meet
ADSP
. This input is
83
84
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to change products or specifications without notice. Revision: A
ADV
ADSP
Input-
Synchronous
Input-
Synchronous
Address Advance: This active LOW input is used to control the
internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).
Address Status Processor: This active LOW input, along with
being LOW, causes a new external address to be registered and a
READ cycle is initiated using the new address.
CE
TE
tm
PIN DESCRIPTIONS
QFP PINS SYM. TYPE DESCRIPTION
2, 3, 6-9, 12, 13,
18, 19, 22-25,
28, 29, 52, 53,
56-59, 62, 63,
68, 69, 72-75,
78, 79,
CH
T35L6432B
(continued)
85
31 MODE
64 ZZ Input
ADSC
DQ1-
DQ32
Input-
Synchronous
Input-
Static
Input/
Output
Address Status Controller:This active LOW input causes
device to be deselected or selected along with new external
address to be registered. A READ or WRITE cycle is
initiated depending upon write control inputs.
Mode: This input selects the burst sequence. A LOW on this
pin selects LINEAR BURST. A NC or HIGH on this pin
selects INTERLEAVED BURST. Do not alter input state
while device is operating.
Snooze Enable: This active HIGH asynchronous input causes
the device to enter a low-power standby mode in which all
data in the memory arry is retained.
Data Inputs/Outputs: First Byte is DQ1-DQ8. Second Byte is
DQ9-DQ16. Third Byte is DQ17-DQ24. Fourth Byte is DQ25DQ32. Input data must meet setup and hold times around the
rising edge of CLK.
15,41,65,91 VCC Supply Power Supply: 3.3V (+0.3V/-0.165V)
17,40,67,90 VSS Ground Ground: GND
4,11,20,27,54,
61,70,77
5,10,21,26,55,
60,71,76
1,14,16,30,38,
39,42,43,50,51,
66,80
VCCQ I/O Supply Output Buffer Supply: 3.3V (+0.3V/-0.165V)
VSSQ I/O Ground Output Buffer Ground: GND
NC - No Connect: These signals are not internally conntected.
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to change products or specifications without notice. Revision: A
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INTERLEAVED BURST ADDRESS TABLE (MODE = NC/VCC)
CH
T35L6432B
First Address
(external)
A...A00 A...A01 A...A10 A...A11
A...A01 A...A00 A...A11 A...A10
A...A10 A...A11 A...A00 A...A01
A...A11 A...A10 A...A01 A...A00
Second Address
(internal)
Third Address
(internal)
Fourth Address
(internal)
LINEAR BURST ADDRESS TABLE (MODE = GND)
First Address
(external)
A...A00 A...A01 A...A10 A...A11
A...A01 A...A10 A...A11 A...A00
A...A10 A...A11 A...A00 A...A01
A...A11 A...A00 A...A01 A...A10
Second Address
(internal)
Third Address
(internal)
Fourth Address
(internal)
PARTIAL TRUTH TABLE FOR READ/WRITE
Function
READ H H X X X X
READ H L H H H H
WRITE one byte H L L H H H
WRITE all byte H L L L L L
WRITE all byte L X X X X X
GW
BWE
BW1
BW2
BW3
BW4
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to change products or specifications without notice. Revision: A
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TRUTH TABLE
CH
T35L6432B
OPERATION
eselected Cycle, Power Down None H X X L X L X X X L-H High-Z
eselected Cycle, Power Down None L X L L L X X X X L-H High-Z
eselected Cycle, Power Down None L H X L L X X X X L-H High-Z
eselected Cycle, Power Down None L X L L H L X X X L-H High-Z
eselected Cycle, Power Down None L H X L H L X X X L-H High-Z
Snooze Cycle, Power Down None X X X H X X X X X X High-Z
READ Cycle, Begin Burst External L L H L L X X X L L-H Q
READ Cycle, Begin Bur st External L L H L L X X X H L-H High-Z
WRITE Cycle, Begin Bur st Ext ernal L L H L H L X L X L-H D
READ Cycle, Begin Burst External L L H L H L X H L L-H Q
READ Cycle, Begin Burst External L L H L H L X H H L-H High-Z
READ Cycle, Continue Burst Next X X X L H H L H L L-H Q
READ Cycle, Continue Burst Next X X X L H H L H H L-H High-Z
READ Cycle, Continue Burst Next H X X L X H L H L L-H Q
READ Cycle, Continue Burst Next H X X L X H L H H L-H High-Z
WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D
WRITE Cycle, Continue Burst Next H X X L X H L L X L-H D
READ Cycle, Suspend Burst Current X X X L H H H H L L-H Q
READ Cycle, Suspend Burst Current X X X L H H H H H L-H High-Z
READ Cycle, Suspend Burst Current H X X L X H H H L L-H Q
READ Cycle, Suspend Burst Current H X X L X H H H H L-H High-Z
WRITE Cycle, Suspend Burst Current X X X L H H H L X L-H D
WRITE Cycle, Suspend Burst Current H X X L X H H L X L-H D
Note: 1. X means "don't care." H means logic HIGH. L means logic LOW.
or more byte write enable signals (
equals LOW. WRITE = H means all byte write signal are HIGH.
GW
2.
3. All inputs except
4. Suspending burst generates wait cycle.
5. For a write operation following a read operation.
6. This device contains circuitry that will ensure the outputs will be High-Z during power-up.
7.
= enables write to DQ1-DQ8.
BW1
write to DQ17-DQ24.
to HIGH) of CLK.
required setup time plus High-Z time for
hold time.
= LOW along with chip being selected always initiates an internal READ cycle at the L-H
ADSP
edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for the CLK L-H
edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
ADDRESS
USED
OE
CE CE2
=enables write to DQ25-DQ32.
BW4
and ZZ must meet setup and hold times around the rising edge ( LOW
CE2 ZZ
ADSP ADSC ADV WRITE OE
BW1, BW2, BW3
= enables write to DQ9-DQ16.
BW2
OE
and staying HIGH throughout the input data
OE
or
BW4
WRITE
) and
= L means any one
are LOW, or
BWE
BW3
must be HIGH before the input data
CLK DQ
= enables
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to change products or specifications without notice. Revision: A
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tm
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Supply Relative to VSS.
I/O Supply Voltage VccQ ........... Vss -0.5V to
Vcc
V
......................................... -0.5V to Vcc +0.5V
IN
Storage Temperature (plastic)...... -55°C to +150°C
Junction Temperature ..........….................. +150°C
Power Dissipation ........................................ 1.0W
Short Circuit Output Current...................... 100mA
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED
OPERATING CONDITIONS
(0°C ≤ Ta ≤ 70°C; VCC = 3.3V (+0.3V/-0.165V) unless otherwise noted)
DESCRIPTION CONDITIONS SYM. MIN MAX UNITS NOTES
Input High (Logic)
voltage
Input Low (Logic)
voltage
Input Leakage Current
Output Leakage Current Output(s) disabled, 0V
Output High Voltage IOH = -4.0 mA VOH 2.4 V 1, 11
Output Low Voltage IOL = 8.0 mA VOL 0.4 V 1, 11
Supply Voltage Vcc 3.1 3.6 V 1
CH
T35L6432B
*Stresses greater than those listed under
…………-0.5V to +4.6V
0V ≤ VIN ≤ VCC
≤ V
OUT
≤ VCC
"Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress
rating only and functional operation of the device
at these or any other conditions above those
indicated in the operational sections of this
specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect reliability.
VIH 2 VCCQ + 0.3 V 1, 2
VIL -0.3 0.8 V 1, 2
ILI -2 2 uA 14
ILO -2 2 uA
MAX.
DESCRIPTION CONDITIONS SYM. TYP -9 -10 -11 -12 UNITS NOTES
Device selected; all inputs ≤VIL or
Power Supply
Current : Operating
Power Supply
Current: Idle
CMOS Standby
TTL Standby
Clock Running
≥ VIH; cycle time ≥tKC MIN; VCC
= MAX; outputs open
Device selected;
ADSC
ADV, GW,BWE
inputs≤VIL or≥VIH; VCC = MAX;
cycle time ≥ tKC MIN: outputs open
Device deselected; VCC = MAX; all
inputs ≤ VSS + 0.2 or ≥ VCC - 0.2;
all inputs static; CLK frequency =0
Device deselected; all inputs ≤ VIL
or ≥ VIH; all inputs static; VCC =
MAX;CLK frequency = 0
Device deselected; all inputs ≤ VIL
or ≥ VIH; VCC =MAX; CLK cycle
time ≥ tKCMIN
ADSP
,
≥ VIH; all other
,
ICC
I
SB1
I
SB2
I
SB3
I
SB4
TBD 250 200 150 120 mA 3, 12, 13
TBD 60 60 60 60 mA 12, 13
TBD 10 10 10 10 mA 12, 13
TBD 25 25 25 25 mA 12, 13
TBD 60 60 60 60 mA 12, 13
Taiwan Memory Technology, Inc. reserves the right P.8 Publication Date: JUL. 2002
to change products or specifications without notice. Revision: A
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tm
AC ELECTRICAL CHARACTERISTICS
CH
T35L6432B
(Note 5)
(0°C≤TA≤70°C;VCC=3.3V +0.3V/-0.165V)
DESCRIPTION
Clock
Clock cycle time t
Clock to output valid tKQ
Clock to output invalid t
Clock to output in Low-Z t
Output Times
Clock HIGH time t
Clock LOW time t
Clock to output in High-Z t
OE to output valid t
OE to output in Low-Z t
OE to output in High-Z t
Setup Times
Address t
ddress Status(
Address Advance (
Byte Write Enables
(
BW1~ BW4 , BWE , GW)
Data-in t
Chip Enables(CE ,CE2 ,CE2)
Hold Times
Address t
ddress Status(ADSC ,ADSP )
Address Advance (ADV)
Byte Write Enables
(
BW1~ BW4 , BWE , GW)
Data-in t
Chip Enables(CE ,CE2 ,CE2)
ADSC,ADSP
ADV
)
)
SYM. MIN MAX MIN MAX MIN MAX MIN MAX
KC
KQX
KQLZ
KH
KL
KQHZ
OEQ
OELZ
OEHZ
AS
t
ADSS
t
AAS
t
WS
DS
t
CES
AH
t
ADSH
t
AAH
t
WH
DH
t
CEH
-9 -10 -11 -12
10.5 15 15 15 ns
9.0 10 11 12 ns
3 3 3 3 ns
3 3 3 3 ns
1.8 1.9 2.0 2.0 ns
1.8 1.9 2.0 2.0 ns
5 5 5 5 ns
5 5 5 5 ns
0 0 0 0 ns
5 5 5 5 ns
1.7
1.7
1.7
1.7
1.7
1.7
0.5 0.5 0.5 0.5 ns
0.5 0.5 0.5 0.5 ns
0.5 0.5 0.5 0.5 ns
0.5 0.5 0.5 0.5 ns
0.5 0.5 0.5 0.5 ns
0.5 0.5 0.5 0.5 ns
2.0
2.0
2.0
2.0
2.0
2.0
2.0 2.0 ns
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
UNITS
ns
ns
ns
ns
ns
NOTES
6, 7
6, 7
9
6, 7
6, 7
8, 10
8, 10
8, 10
8, 10
8, 10
8, 10
8, 10
8, 10
8, 10
8, 10
8, 10
8, 10
Taiwan Memory Technology, Inc. reserves the right P.9 Publication Date: JUL. 2002
to change products or specifications without notice. Revision: A
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CAPACITANCE
DESCRIPTION CONDITIONS SYM. TYP MAX UNITS NOTES
THERMAL CONSIDERATION
Thermal Resistance - Junction to
Thermal Resistance - Junction to Case
AC TEST CONDITIONS
Input pulse levels 0V to 3.0V
Input rise and fall times 1.5ns
Input timing reference levels 1.5V
Output reference levels 1.5V
Output load See Figures 1 and
Notes:
1. All voltages referenced to VSS (GND).
2. Overshoot: VIH ≤ +3.6 V for t ≤ tKC/2.
Undershoot: VIL ≤ -1.0 V for t ≤ tKC/2.
3. Icc is given with no output current. Icc increases with
greater output loading and faster cycle times.
4. This parameter is sampled.
5. T est conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. Output loading is specified with CL = 5 pF as in Fig.
2.
OUTPUT LOADS
DQ
CH
T35L6432B
Input Capacitance
Input/ Output
Capacitance(DQ)
TA = 25°C; f = 1 MHz
VCC = 3.3V
CI
CO
3 4 pF 4
6 7 pF 4
DESCRIPTION CONDITIONS SYM. QFP TYP UNITS NOTES
Ambient
Z0 = 50 ohm
Fig. 1 output load equivalent
Vt = 1.5V
Still air, soldered on
4.25x1.125 inch 4-layer
PCB
7. At any given temperature and voltage condition,
t
KQHZ is less than tKQLZ and tOEHZ is less than
t
OELZ.
8. A READ cycle is defined by byte write enables all
HIGH or
2
50
ohm
being active for the required setup and hold times. A
WRITE cycle is defined by at one byte or all byte
WRITE per READ/WRITE TRUTH TABLE.
9.
OE
sampled LOW.
10.This is a synchronous device. All synchronous inputs
must meet specified setup and hold time, except for
"don't care" as defined in the truth table.
11.AC I/O curves are available upon request.
12."Device Deselected means the device is in
POWER-DOWN mode as defined in the truth table.
"Device Selected" means the device is active.
13.Typical values are measured at 3.3V, 25°C and 20ns
cycle time.
14.MODE pin has an internal pull-up and exhibits an
input leakage current of ± 10µA.
DQ
ΘJA
ΘJB
ADSP
is a "don't care" when a byte write enable is
351
ohm
Fig. 2 output load equivalent
(for tKQHZ,tKQLZ,tOEHZ,tOELZ)
20
1
LOW along with chip enables
°C/W
°C/W
3.3V
5 pF
317
ohm
Taiwan Memory Technology, Inc. reserves the right P.10 Publication Date: JUL. 2002
to change products or specifications without notice. Revision: A
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TE
CH
T35L6432B
SNOOZE MODE
SNOOZE MODE is a low current, “power
down” mode in which the device is deselected and
current is reduced to I
SNOOZE MODE is dictated by the length of ti me
the ZZ pin is in a HIGH state. After entering
SNOOZE MODE, the clock and all other inputs
are ignored. The ZZ pin (pin 64) is an
The duration of
ZZ.
device to enter SNOOZE MODE. Wh en the ZZ
pin becomes a logic HIGH, I
is guaranteed after
ZZ
the setup time tZZ is met. Any access pending
when entering SNOOZE MODE is not guara nteed
to successfully complete. Therefore, SNOOZE
MODE must not be initiated until valid pending
operations are completed.
asynchronous, active HIGH input that causes the
SNOOZE MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES
Current during
SNOOZE MODE
ZZ HIGH to
SNOOZE MODE time
SNOOZE MODE
Operation Recovery Time
ZZ ≥ V
IH
I
ZZ
t
ZZ
t
RZZ
5
2(tKC)
2(tKC)
mA
ns
ns
SNOOZE MODE WAVEFORM
4
4
CLK
CE
t
RZZ
ZZ
t
ZZ
I
SUPPL Y
I
ZZ
Note: 1. The
2. All other inputs held to static CMOS levels (VIN ≤ Vss + 0.2 V or ≥ Vcc -0.2 V).
signal shown above refers to a TRUE state on all chip selects for the device.
CE
I
SUPPL Y
:Don't care
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to change products or specifications without notice. Revision: A
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READ TIMING
CH
T35L6432B
t
KC
CLK
ADSP
ADSC
ADDRESS
GW,BWE
BW1-BW 4
CE
(NOTE2)
ADV
t
ADSS
tASt
t
CES
A1
t
t
t
AH
CEH
KH
ADSH
t
KL
t
t
ADSH
ADSS
Deselect C ycle
(N ote4 )
A2
t
t
WH
WS
t
AAStAAH
ADV suspends burst
OE
t
OEZ
t
KQLZ
Q
t
KQ
t
OEHZtOELZ
Q(A1) Q(A2)
Single READ BURST READ
t
t
KQ
KQX
Q(A2+1)
Q(A2+2)
Q(A2+3) Q(A2+1) Q(A2+2)Q(A2)
Burst wraps around to
its in ita l s ta te
t
KQHZ
:D o n 't c ar e
:UNDEFINED
Note: 1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst
address following A2.
2.
CE2
and CE2 have timing identical to CE. On this diagram, when CE is LOW,
and CE2 is HIGH. When
CE is HIGH, CE2 is HIGH and CE2 is LOW.
CE2
is LOW
3. Timing is shown assuming that the device was not enabled before entering into this sequence.
OE
does not cause Q to be driven until after the following clock rising edge.
4. Output are disabled tKQHZ after diselect.
Taiwan Memory Technology, Inc. reserves the right P. 12 Publication Date: JUL. 2002
to change products or specifications without notice. Revision: A
TE
tm
WRITE TIMING
CLK
ADSP
ADSC
CH
T35L6432B
t
KH
t
t
ADSH
ADSS
tASt
AH
t
KC
t
ADSS
t
KL
t
ADSH
AD SC extends burst
t
ADSS
t
ADSH
ADDRESS
BWE
BW1-BW 4
GW
CE
(N ote2 )
ADV
OE
D
Q
High-Z
A1
BY TE W R ITE signals are
ignored for first cycle when
A D S P in itia lte s b u r st
t
t
CEH
CES
(N ote3 )
t
DS
D(A1) D(A2) D(A2+1) D(A2+1) D(A2+2) D(A2+3) D(A3) D(A3+1) D(A3+2)
t
OEHS
A2
tWSt
WH
(N ote5 )
(N ote4 )
t
DH
(N ote1 )
ADV suspnds burst
A3
tWSt
WH
t
AAStAAH
BURST READ BURST W RITE
Single W R ITE Extend BUR ST W RITE
:Don 't care
:UNDEFINED
Note: 1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst
address following A2.
2.
3.
CE2
and CE2 have timing identical to CE. On this diagram, when CE is LOW ,
LOW and CE2 is HIGH. When
CE is HIGH , CE2 is HIGH and CE2 is LOW.
CE2
is
OE must be HIGH before the input data setup and hold HIGH throughout the data hold time.
This prevents input/output data contention for the time period to the byte write enable inputs being
sampled.
4.
5. Full width WRITE can be initiated by
must be HIGH to permit a WRITE to the loaded address.
ADV
GW LOW or GW HIGH and BWE , BW1- BW4
LOW.
Taiwan Memory Technology, Inc. reserves the right P. 13 Publication Date: JUL. 2002
to change products or specifications without notice. Revision: A
TE
tm
READ/WRITE TIMING
CH
T35L6432B
t
KC
CLK
ADSP
ADSC
ADDRESS
BWE
BW1-BW 4
CE
(NOTE2)
ADV
A1
t
KH
t
KL
t
t
ADSH
ADSS
t
t
AS
AH
A2 A3 A4 A5 A6
tWSt
WH
t
t
CES
CEH
OE
t
t
DS
DH
D
Q
High-Z
t
OEHZ
Q(A1) Q(A2) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3)
Back-to-Back READs
Single W RITE
t
OELZ
t
KQ
(N OTE1)
BURST READ
Back-to-Back
:Don 't care
:UNDEFINED
D(A6)D(A5)D(A3)
WRITEs
Note: 1. Q(A4) refers to output from address A4. Q (A4 + 1) refers to output from the next internal burst
address following A4.
2.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an
4.
5. Back-to-back READs may be controlled by either
CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW, CE2 is
LOW and CE2 is HIGH. When
CE is HIGH, CE2 is HIGH and CE2 is LOW.
ADSP, ADSC or
ADV
cycle is performed.
GW
is HIGH.
ADSP
or
ADSC
.
Taiwan Memory Technology, Inc. reserves the right P. 14 Publication Date: JUL. 2002
to change products or specifications without notice. Revision: A
TE
tm
PACKAGE DIMENSIONS
100-LEAD QFP SSRAM (14 x 20 mm)
CH
T35L6432B
HD'
D
81100
1
eb
30
31
t
Seating Plane
y
80
E
HE'
51
50
A
£
c
A2A1
L'
L1
'
SYMBOL DIMENSIONS IN INCHES DIMENTION IN MM
A 0.130(MAX) 3.302(MAX)
A1 0.112±0.005 2.845±0.127
A2 0.004(MIN) 0.102(MIN)
b 0.012+0.004-0.002 0.300+0.102-0.051
D 0.551±0.005 14.000±0.127
E 0.787±0.005 20.000±0.127
e 0.026±0.006 0.650±0.152
HD' 0.677±0.008 17.200±0.203
HE' 0.913±0.008 23.200±0.203
L' 0.032±0.008 0.800±0.203
L1' 0.063±0.008 1.600±0.203
t 0.006+0.004-0.002 0.150+0.102-0.051
y 0.004(MAX) 0.102(MAX)
θ
0°~12° 0°~12°
Taiwan Memory Technology, Inc. reserves the right P.15 Publication Date: JUL. 2002
to change products or specifications without notice. Revision: A
TE
tm
PACKAGE DIMENSIONS
100-LEAD TQFP SSRAM (14 x 20 mm)
CH
T35L6432B
HD'
D
81100
1
eb
30
31
t
Seating Plane
y
80
E
HE'
51
50
A
£
c
A2A1
L'
L1
'
SYMBOL DIMENSIONS IN INCHES DIMENTION IN MM
A 0.063(MAX) 1.600(MAX)
A1 0.055±0.005 1.400±0.050
A2 0.002(MIN) 0.050(MIN)
b 0.013+0.002-0.004 0.320+0.060-0.100
D 0.551±0.004 14.000±0.100
E 0.787±0.004 20.000±0.100
e 0.026±0.006 0.650±0.152
HD' 0.630±0.004 16.000±0.100
HE' 0.866±0.004 22.000±0.100
L' 0.024±0.006 0.600±0.150
L1' 0.039±0.006 1.000±0.150
t 0.006±0.002 0.150+0.050-0.060
y 0.003(MAX) 0.080(MAX)
θ
0°~7° 0°~7°
Taiwan Memory Technology, Inc. reserves the right P.16 Publication Date: JUL. 2002
to change products or specifications without notice. Revision: A
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