Taiwan Memory Technology T35L3232B-4T, T35L3232B-3.8Q Datasheet
TE
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FT
CE
CE2
ADSC
ADSP
ADV
BW1
BW2
BW3
BW4
BWE
GW
OE
ADSP
ADSC
ADV
BW1
BW2
BW3
BW4
BW1
BW2
BW3
BW4
BWE
GW
Preliminary T35L3232B
SYNCHRONOUS
BURST SRAM
FEATURES
¡E
¡E Fast Access times:
¡ESingle 3.3V +0.3V/-0.165V power supply
¡ECommon data inputs and data outputs
¡EIndividual BYTE WRITE ENABLE and
¡E Three chip enables for depth expansion and
¡E Clock-controlled and registered address, data
¡EInternally self-timed WRITE CYCLE
¡EBurst control pins ( interleaved or linear burst
¡EHigh 30pF output drive capability at rated
¡ESNOOZE MODE for reduced power standby
¡E Burst Sequence :
OPTIONS
through
Part Number Examples
pin for user configurable pipeline or
flow-through operation.
- Pipeline – 3.8 / 4 / 4.5 ns
- Flow-through – 9 / 10 / 11ns
GLOBAL WRITE control
address pipelining
I/Os and control signals
sequence)
access time
- Interleaved (MODE=NC or VCC)
- Linear (MODE=GND)
MARKING -3.8 -4 -4.5
Access
3-1-1-1
2-1-1-1
Package
PART NO. Pkg.
T35L3232B-3.8Q Q
T35L3232B-4T T
time
Cycle
time
Access
time
Cycle
time
100-pin QFP Q
100-pin TQFP T
3.8ns 4ns 4.5nsPipeline
6.6ns 7.5ns 8.5ns
9ns 10ns 11nsFlow-
10.5ns 15ns 15ns
32K x 32 SRAM
Pipeline and Flow-Through Burst Mode
GENERAL DESCRIPTION
The Taiwan Memory Technology Synchronous
Burst RAM family employs high-speed, low power
CMOS design using advanced triple-layer polysilicon,
double-layer metal technology. Each memory cell
consists of four transistors and two high valued resistors.
The T35L3232B SRAM integrates 32,768 x 32
bits SRAM cells with advanced synchronous peripheral
circuitry and a 2-bit counter for internal burst operation.
All synchronous inputs are gated by registers controlled
by a positive-edge-triggered clock input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining chip enable (
expansion chip enables (
inputs (
(
global write (
(OE), Snooze enable (ZZ) and burst mode control
(MODE). The data outputs (Q), enabled by
also asynchronous.
either address status processor (
status controller (
addresses can be internally generated as controlled by
the burst advance pin (
to initiate self-timed WRITE cycle. WRITE cycles
can be one to four bytes wide as controlled by the write
control inputs. Individual byte write
allows individual byte to be written.
DQ1-DQ8.
controls DQ17-DQ 24.
with
all bytes to be written. WRITE pass-through
capability allows written data available at the output for
the immediately next READ cycle. This device also
incorporates pipelined enable circuit for easy depth
expansion without penalizing system performance.
,
Asynchronous inputs include the output enable
Addresses and chip enables are registered with
Address and write controls are registered on-chip
,
,
,
).
controls DQ9-DQ16.
,
being LOW.
, and
and CE2), burst control
, and
,
) input pins. Subsequent burst
, and
).
controls DQ25-DQ32.
can be active only
being LOW causes
), depth-
), write enables
), and
, are
) or address
controls
Taiwan Memory Technology, Inc. reserves the right P. 1 Publication Date: FEB. 2000
to change products or specifications without notice. Revision:0.A
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Preliminary T35L3232B
FUNCTIONAL BLOCK DIAGRAM
COUNTER
CLR
15
A0
BINARY
& LOGIC
A0-A14
MODE
ADV
CLK
ADSC
ADSP
15
ADDRESS
REGISTER
A1
Q1
Q0
13
15
A1'
A0'
BWE
BW4
BW3
BW2
BW1
GW
FT
CE
CE2
CE2
OE
BYTE 4
WRITE REGISTER
BYTE 3
WRITE REGISTER
BYTE 2
WRITE REGISTER
BYTE 1
WRITE REGISTER
ENABLE
REGISTER
8
BYTE 4
WRITE DRIVER
8
BYTE 3
WRITE DRIVER
8
BYTE 2
WRITE DRIVER
8
BYTE 1
WRITE DRIVER
8
8
8
8
32K x 8 x 4
MEMORY
ARRAY
32 32
SENSE
AMPS
OUTPUT
BUFFERS
4
32
INPUT
REGISTERS
DQ1
¡E
¡E
¡E
DQ32
Note: The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin
descriptions and timing diagrams for detailed information.
Taiwan Memory Technology, Inc. reserves the right P. 2 Publication Date: FEB. 2000
to change products or specifications without notice. Revision:0.A
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NC
VCC
NC
NC
A10
NC
VSS
A11
A12
A13
A14
NC
NC
MODE
Preliminary T35L3232B
PIN ASSIGNMENT (Top View)
A7
A6
CE
CE2
BW4
9596 88 87 86 85 84 83 82 819091929394 89100 99 98 97
BW3
BW2
BW1
CE2
VCC
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
NC
DQ17
DQ18
VCCQ
VSSQ
DQ19
DQ20
DQ21
DQ22
VSSQ
VCCQ
DQ23
DQ24
FT
VCC
NC
VSS
DQ25
DQ26
VCCQ
VSSQ
DQ27
DQ28
DQ29
DQ30
VSSQ
VCCQ
DQ31
DQ32
NC NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 41403938373635343332 4948474645444342 50
100-pin QFP
or
100-pin TQFP
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQ16
DQ15
VCCQ
VSSQ
DQ14
DQ13
DQ12
DQ11
VSSQ
VCCQ
DQ10
DQ9
VSS
NC
VCC
ZZ
DQ8
DQ7
VCCQ
VSSQ
DQ6
DQ5
DQ4
DQ3
VSSQ
VCCQ
DQ2
DQ1
A0
A1
A2
A3
A4
A5
Taiwan Memory Technology, Inc. reserves the right P. 3 Publication Date: FEB. 2000
to change products or specifications without notice. Revision:0.A
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t
CE2
CE
CE2
CE
CE2
OE
PIPELINE READ TIMING
KC
C LK
tKHt
KL
t
ADS StADSH
AD S P
t
ADS StADSH
AD SC
tASt
AH
Preliminary T35L3232B
AD D R E S S
G W, B W E ,
B W 1 - B W 4
CE
( N O T E 2 )
AD V
O E
Q Q(A3)
t
CEStCEH
tWSt
(NOTE3)
High -Z
WH
t
KQLZ
t
KQ
Sing le READ
t
AAStAAH
ADV susp ends bur st.
t
t
OEQ
KQ
t
OEHZ
t
OELZ
KQX
(NOTE1)
BUR ST R EAD
t
Q(A1) Q(A2) Q(A2+1) Q(A2+2) Q(A2+3) Q(A2+1)
A3A2A1
Burst c ontinued wi th
new b ase add ress.
Q(A2)
Burst wra ps a round
to it s ini tal st ate.
Deselect cy cle.
t
KQHZ
t
KQX
DON'T CARE
UNDEFINED
Note: 1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst
address following A2.
2.
and CE2 have timing identical to CE. On this diagram, when
and CE2 is HIGH. When
is HIGH,
is HIGH and CE2 is LOW.
is LOW,
is LOW
3. Timing is shown assuming that the device was not enabled before entering into this sequence.
does not cause Q to be driven until after the following clock rising edge.
Taiwan Memory Technology, Inc. reserves the right P. 12 Publication Date: FEB. 2000
to change products or specifications without notice. Revision:0.A
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CE2
CE
CE2
CE
CE2
OE
t
FLOW-THROUGH READ TIMING
KC
CLK
tKHt
KL
t
AD S StAD SH
ADS P
t
AD S StAD SH
AD SC
tASt
AH
AD DRES S
GW , BWE ,
BW 1-B W4
CE
(NO TE 2)
A 1
t
CE StCE H
t
W StW H
A2
t
AAStAAH
Preliminary T35L3232B
De s ele c t C y c le
(NOTE 4)
ADV
AD V s uspe n ds burst.
O E
t
OEQ
t
t
KQ LZ
Q
High-Z
t
KQ
OEHZ
Q(A1) Q(A2) Q(A2+1) Q(A2+2) Q(A2+3) Q(A2+1)
Si ngle RE AD
t
OELZ
t
t
KQX
KQ
Q(A2)
(NOTE1 )
BU R ST R EA D
Burst w raps around to
it s init a l s ta te .
t
KQHZ
Q(A2+2)
DON'T CARE
UNDEFINED
Note: 1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst
address following A2.
2.
and CE2 have timing identical to CE. On this diagram, when
and CE2 is HIGH. When
is HIGH,
is HIGH and CE2 is LOW.
is LOW,
is LOW
3. Timing is shown assuming that the device was not enabled before entering into this sequence.
does not cause Q to be driven until after the following clock rising edge.
4. Output are disabled tKQHZ after diselect.
Taiwan Memory Technology, Inc. reserves the right P. 13 Publication Date: FEB. 2000
to change products or specifications without notice. Revision:0.A
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CE2
CE
CE2
CE
CE2
OE
ADV
GW
GW
BWE
BW1
BW4
WRITE TIMING
C L K
t
ADS StADSH
tKHt
Preliminary T35L3232B
KC
KL
AD S P
AD SC
AD D R E SS
B WE ,
B W 1 - B W 4
G W
CE
( N O T E 2 )
AD V
O E
t
ADS StADSH
tASt
AH
BYT E W RITE si gnal s a re
igno red fo r firs t cyc le wh en
ADS P in itial tes bu rst.
t
CEStCEH
(NOTE3)
tDSt
DH
tWSt
WH
(NOTE5)
ADSC exte nds bur st.
ADV s uspn ds b urst.(NOTE4)
t
ADSStADSH
A3A2A1
tWSt
t
AAStAAH
WH
D
Q
High -Z
BUR ST R EAD Exte nde d BU RST W RIT E
D(A1) D(A2) D(A2+1) D(A2+2) D(A2+3) D(A3+1)D(A3)
t
OEHZ
Sin gle WRI TE
(NOTE1)
D(A2+1) D(A3+2)
BUR ST W RIT E
DON'T CARE
UNDEFINED
Note: 1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst
address following A2.
2.
3.
and CE2 have timing identical to CE. On this diagram, when
LOW and CE2 is HIGH. When
is HIGH ,
is HIGH and CE2 is LOW.
is LOW ,
must be HIGH before the input data setup and hold HIGH throughout the data hold time.
is
This prevents input/output data contention for the time period to the byte write enable inputs being
sampled.
4.
5. Full width WRITE can be initiated by
must be HIGH to permit a WRITE to the loaded address.
LOW or
HIGH and
,
-
LOW.
Taiwan Memory Technology, Inc. reserves the right P. 14 Publication Date: FEB. 2000
to change products or specifications without notice. Revision:0.A
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