Taiwan Memory Technology T2316405A, T2316407A Datasheet
TE
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WE
CAS
CAS
CAS
Preliminary T2316407A
T2316405A
DRAM
FEATURES
•
Industry-standard x 4 pinouts and timing
functions
•
power supply : T2316405A 2.6V(±0.2V)
T2316407A 3.3V(±0.3V)
•
All device pins are TTL- compatible.
• 2048-cycle refresh in 32 ms.
•
Refresh modes:
RAS
(CBR) and HIDDEN.
•
Extended data-out (EDO) PAGE MODE
access cycle.
OPTION
TIMING MARKING
50ns (For T2316407A only) -50
60ns (For T2316407A only) -60
70ns (For T2316407A only) -70
10 0ns (For T2316405A only) -10
PACKAGE
26/24 -pin SOJ J
26/24 -pin TSOP-II S
PIN ARRANGEMENT (
Vcc
I/O1
I/O2
WE
RAS
NC
A10
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
9
10
11
12
13
RAS
only,
CAS
BEFORE
Top View)
26
Vss
25
I/O4
24
I/O3
23
CAS
22
OE
SOJ
&
TSOP-II
21
198
18
17
16
15
14
A9
A8
A7
A6
A5
A4
Vss
4M x 4 DYNAMIC RAM
EDO PAGE MODE
GRNERAL DESCRIPTION
The T2316405A and T2316407A is a randomly
accessed solid state memory containing 16,777,216
bits organized in a x 4 configuration. It offers Fast
Page mode with Extended Data Output (EDO).
During READ or WRITE cycles, each of the 4
memory bits (1 bit per I/O) is uniquely addressed
through the 22 address bits, which are entered 11
bits (A0-A10) at a time.
bits and
A READ or WRITE cycle is selected with
the
READ mode while a logic LOW on
WRITE mode. During a WRITE cycle, data -in is
latched by the falling edge of
whichever occurs last. When
to
output pins remain open (High-Z) until the next
CAS
When WE falls after
Write cycle). OE must be taken HIGH to disable
the data-outputs prior to applying input data.
The four data inputs and four data outputs are
routed through four pins using common I/O, and pin
direction is controlled by
CAS
latches the latter 11 bits.
WE
input. A logic HIGH on
going LOW ( EARLY WRITE cycle), the
cycle.
A Late Write or Read-Modify -Write occurs.
RAS
latches the first 11
WE
goes Low prior
was taken LOW (Late
WE
and OE.
WE
WE
or
dictates
dictates
,
Taiwan Memory Technology, Inc. reserves the right P. 1 Publication Date: APR 2001
to change products or specifications without notice. Revision:0.B
TE
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CAS
BLOCK DIAGRAM
WE
CAS
NO.2 CLOCK
GENERATOR
COLUMNADDRESS
11
BUFFER(11)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
RAS
PIN DESCRIPTION
11
BUFFERS (11)
REFRESH
CONTROLLER
REFRESH
COUNTER
11
ROW-
ADDRESS
NO.1 CLOCK
GENERATOR
T2316405A
Preliminary T2316407A
11
CONTROL
LOGIC
ROW
DECODER
1
2048
10
2048
2048
2048
2048
SELECT
COMPLEMENT
DATA-IN
BUFFER
DATA-OUT
BUFFER
COLUMN
DECODER
1024
SENSE AMPLIFIERS
I/O GATING
4096 x 1024 x 4
MEMORY
(2 of 4096)
ROW SELECT
1024
ARRAY
4
4
4
4
(1 of 2)
ROW TRANSFER
(1 of 2)
Vcc
Vss
IO1
IO2
IO3
IO4
OE
PIN NO. SYM. TYPE DESCRIPTION
8~12,15~19,21 A0-A10 Input Address In put
5 RAS
23
4 WE
22 OE
Input Row Address Strobe
Input Column Address Strobe
Input Write Enable
Input Output Enable
2,3,24,25 I/O1 -I/O4 Input/ Output Data Input/ Output
1,13 Vcc Supply Power
14,26 Vss Ground Ground
6 NC No Connect
Taiwan Memory Technology, Inc. reserves the right P. 2 Publication Date: APR 2001
to change products or specifications without notice. Revision:0.B
TE
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ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Value Unit
Voltage on Any Pin Relative To Vss VT -0.5 to 4.6 V
Supply Voltage Relative To Vss Vcc -0.5 to 4.6 V
Preliminary T2316407A
T2316405A
Short circuit Output Current I
Power Dissipation PT 1 W
Operating Temperature T
Storage Temperature T
RECOMMENDED DC OPERATING CONDITIONS
(Ta = 0 to +70°°C) For T2316405A-10 only
Parameter Symbol Min. Typ Max. Unit Notes
Vss 0 0 0 V
Supply Voltage
Vcc 2.4 2.6 2.8 V 1
Input High Voltage VIH 2.0 - Vcc+0.3V V 1
Input Low Voltage VIL -0.3 - 0.8 V 1
(Ta = 0 to +70°°C) For T2316407A-50/60/70 only
Parameter Symbol Min. Typ Max. Unit Notes
Vss 0 0 0 V
Supply Voltage
Vcc 3.0 3.3 3.6 V 1
50 mA
out
0 to 70
OPR
-55 to 125
stg
°
°
C
C
Input High Voltage VIH 2.0 - Vcc+0.3V V 1
Input Low Voltage VIL -0.3 - 0.8 V 1
Notes : 1. All voltages referenced to Vss
Taiwan Memory Technology, Inc. reserves the right P. 3 Publication Date: APR 2001
to change products or specifications without notice. Revision:0.B
TE
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T2316405A
RAS
CAS
RAS
CAS
DC CHARACTERISTICS
(Ta = 0 to 70
) T2316405A -10 Vcc = 2.6V ±0.2V, Vss = 0V
°°
C
Preliminary T2316407A
T2316407A-50/60/70 Vcc = 3.3V ±0.3V, Vss = 0V
-50 -60 -70 -10
Parameter Symbol
Input Leakage Current ILI -5 5 -5 5 -5 5 -5 5 uA
Output Leakage
Current
Output High Voltage VOH 2.0 - 2.0 - 2.0 - 2.0 - V
Min Max Min Max Min Max Min Ma
ILO -5 5 -5 5 -5 5 -5 5 uA
x
Unit
Test Condition
0V≤ Vin ≤ Vcc+ 0.3V
Other pins = 0V
0V≤ Vout≤ Vcc
Dout = disable
High Iout= -2.0mA
Output Low Voltage VOL - 0.8 - 0.8 - 0.8 - 0.8 V
Operating Current Icc1 - 95 - 90 - 80 - 50 mA
Standby Current Icc2 - 2 - 2 - 2 - 2 mA
Standby Current Icc3 - 0.5 - 0.5 - 0.5 - 0.5 mA
EDO Page Mode
Current
RAS
-only refresh
Current
CAS
Before
Refresh Current
RAS
Icc4 - 95 - 90 - 80 - 50 mA
Icc5 - 95 - 90 - 80 - 50 mA
Icc6 - 95 - 90 - 80 - 50 mA
Low Iout=2.0mA
,
cycling
tRC=min
TTL interface,
RAS,CAS
D
OUT
CMOS interface,
RAS, CAS
RAS
cycling, tPC= min
CAS
cycling, tRC = min
tRC= min
=High-Z
=VIL,
=VIH,
,
=VIH,
> Vcc-0.2V
CAS
cycling,
Note: Icc depends on output load condition when the device is selected.
Icc max is specified at the output open condition, Icc is specified as an average current.
CAPACITANCE
(Ta =25°C, f = 1M HZ, T2316405A -10 Vcc = 2.6V, T2316407A-50/60/70 Vcc = 3.3V)
RAS
Parameter Symbol Typ Max Unit
Input Capacitance
(address)
Input Capacitance
RAS,CAS,WE,OE
(
Output Capacitance
(data-in/out)
Taiwan Memory Technology, Inc. reserves the right P. 4 Publication Date: APR. 2001
to change products or specifications without notice. Revision:0.B
)
CI1 - 5 pF
CI2 - 7 pF
C
- 7 pF
I/O
TE
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T2316405A
CAS
CAS
CAS
CAS
CAS
RAS
10,16
AC CHARACTERISTICS
TEST CONDITIONS:
T2316405A-10 Vcc = 2.6V ±0.2V , T2316407A-50/60/70 Vcc = 3.3V ±0.3V
VIH/VIL=2.0/0.8V,VOH/VOL=2.0/0.8V
Input rise and fall times: 2ns , Output Load: 2TTL gate + CL (100pF)
(note 1,2,3) (Ta = 0 to 70°C)
Preliminary T2316407A
-50 -60 -70 -10 AC CHARACTERISTICS
Min Max Min Max Min Max Min Max
84 104 124 180 ns
108 135 160 240 ns
20 25 30 40 ns
56 68 78 120 ns
50 60 70 100 ns
13 15 20 25 ns
13 15 20 25 ns
25 30 35 50 ns 8
30 35 40 55 ns
50 10K 60 10K 70 10K 100 10K ns
100
50
K
8 10 13 25 ns
30 40 50 70 ns
8 10K 10 10K 13 10K 25 10K ns
38 40 45 100 ns
10 10 10 10 ns
12 37 14 45 14 50 25 75 ns
5 5 5 5 ns
0 0 0 0 ns
8 10 10 15 ns
10 25 12 30 12 35 20 50 ns
0 0 0 0 ns
8 10 13 20 ns
21 24 27 45 ns
25 30 35 50 ns
0 0 0 0 ns 14
0 0 0 0 ns
0 0 0 0 ns
0 0 0 0 ns
0 12 0 15 0 20 0 25 ns
60
100
K
70
100
K
100
or
SYM
RC
RWC
PC
PCM
t
RAC
t
CAC
t
OAC
AA
t
ACP
t
RAS
t
RASC
t
RSH
tRP
t
CAS
t
CSH
tCP
t
RCD
t
CRP
ASR
RAH
t
RAD
ASC
CAH
tAR
t
RAL
RCS
t
RCH
t
RRH
t
CLZ
t
OFF1
PARAMETER
Read or Write Cycle Time t
Read Write Cycle Time t
EDO-Page-Mode Read or Write Cycle Time t
EDO-Page-Mode Read-Write Cycle Time t
Access Time From
Access Time From
Access Time From OE
Access Time From Column Address t
Access Time From
RAS
Pulse Width
RAS
Pulse Width (EDO Page Mode)
RAS
Hold Time
RAS
Precharge Time
Pulse Width
CAS
Hold Time
Precharge Time (EDO Page Mode)
RAS
CAS
Row Address Setup Time t
Row Address Hold Time t
RAS
Column Address Setup Time t
Column Address Hold Time t
Column Address Hold Time (Reference to
RAS
Column Address to
Read Command Setup Time t
Read Command Hold Time Reference to
Read Command Hold Time Reference to
RAS
Output Buffer Turn-off Delay From
Taiwan Memory Technology, Inc. reserves the right P. 5 Publication Date: APR. 2001
to change products or specifications without notice. Revision:0.B
CAS
to
RAS
to
to Column Address Delay Time
)
to Output in Low -Z
RAS
CAS
Precharge
Delay Time
Precharge Time
RAS
Lead Time
CAS
100
K
UNIT Notes
4
5
13
ns
7
8
9,14
9
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