Taiwan Memory Technology T2316162A Datasheet
tm
TE
CH
T2316162A
DRAM
FEATURES
Industry-standard x 16 pinouts and timing
•
functions.
Single 5V (±10%) power supply.
•
All device pins are TTL- compatible.
•
1K-cycle refresh in 16ms.
•
Refresh modes:
•
RAS
(CBR) and HIDDEN.
Extended data-out (EDO) PAGE MODE access
•
RAS
only,
CAS
BEFORE
cycle.
BYTE WRITE and BYTE READ access cycles.
•
OPTION
TIMING MARKING
45ns -45
50ns -50
60ns -60
PACKAGE
42-pin SOJ J
44/50-pin TSOPII S
1024K x 16 DYNAMIC RAM
EDO PAGE MODE
GENERAL DESCRIPTION
The T2316162A is a randomly accessed solid state
memory containing 16,777,216 bits organized in a
x16 configuration. The T2316162A has both
BYTE WRITE and WORD WRITE access cycles
CAS
via two
Extended Data Output.
The T2316162A
determined by the first
by the last to transition back high. Use only one of
the two
during WRITE will result in a BYTE WRITE.
CASL
data into the lower byte (DQ0~DQ7), and
transiting low will write data into the upper byte
(DQ8~DQ15).
pins. It offers Fast Page mode with
CAS
function and timing are
CAS
to transition low and
CAS
and leave the other staying high
transiting low in a WRITE cycle will write
CASH
PIN ASSIGNMENT ( Top View )
V
DD
1
DQ0
V
DQ0
DQ1
DQ2
DQ3
V
DQ4
DQ5
DQ6
DQ7
NC
NC
WE
RAS
NC
NC
V
DD
1
2
3
4
5
DD
6
7
8
9
10
11
12
13
14
15
16
A0
17
A1
18
A2
19
A3
20
DD
21
Vss
42
DQ15
41
DQ14
40
DQ13
39
DQ12
38
Vss
37
DQ11
36
DQ10
35
DQ9
34
DQ8
33
NC
32
CASL
31
CASH
30
OE
29
A9
28
A8
27
A7
26
A6
25
A5
24
A4
23
Vss
22
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
WE
RAS
V
2
3
4
5
6
7
8
9
10
NC
11
NC
15
NC
16
17
18
NC
19
NC
20
A0
21
A1
22
A2
23
A3
24
DD
25
TM Technology Inc. reserves the right P. 1 Publication Date: APR. 2002
to change products or specifications without notice. Revision:E
Vss
50
DQ15
49
DQ14
48
DQ13
47
DQ12
46
Vss
45
DQ11
44
DQ10
43
DQ9
42
DQ8
41
NC
40
NC
36
CASL
35
CASH
34
OE
33
A9
32
A8
31
A7
30
A6
29
A5
28
A4
27
Vss
26
TE
tm
FUNCTIONAL BLOCK DIAGRAM
CH
T2316162A
WE
RAS
CASL
CASH
NO.2 CLOCK
GENERATOR
COLUMN.
ADDRESS
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
CONTROLLER
10
REFRESH
REFRESH
COUNTER
ADDRESS
BUFFERS(10)
NO.1 CLOCK
GENERATOR
CAS
BUFFER
10
ROW.
CONTROL
LOGIC
10
ROW
DECODER
10
1024
DATA-IN BUFFER
COLUMN
DECODER
1024
SENSE AMPLIFIERS
I/O GATING
1024x 16
1024x 1024 x 16
MEMORY
ARRAY
DQ0
16
DATA-OUT
BUFFER
1
6
16
.
.
DQ15
OE
Vcc
Vss
PIN DESCRIPTIONS
SYM. TYPE DESCRIPTION
A0-A9 Input Address Input
RAS
CASH
CASL
WE
OE
DQ0 – DQ15 Input/ Output Data Input/ Output
Vcc Supply Power, 5V
Vss Ground Ground
NC - No Connect
TM Technology Inc. reserves the right P. 2 Publication Date: APR. 2002
to change products or specifications without notice. Revision:E
Input Row Address Strobe
Input Column Address Strobe /Upper Byte Control
Input Column Address Strobe /Lower Byte Control
Input Write Enable
Input Output Enable
TE
tm
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any pin Relative to VSS.... -1V to +7V
Operating Temperature, Ta (ambient).....
Storage Temperature (plastic)...... -55°C to +150°C
Power Dissipation ........................................ 1.2W
Short Circuit Output Current........................ 50mA
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED
OPERATING CONDITIONS
(0°C ≤ Ta ≤ 70°C; VCC = 5V ± 10 % unless otherwise noted)
DESCRIPTION CONDITIONS SYM. MIN MAX UNITS NOTES
Supply Voltage Vcc 4.5 5.5 V 1
Supply Voltage Vss 0 0 V
Input High (Logic) voltage VIH 2.4 Vcc+1 V 1
Input Low (Logic) voltage VIL -1.0 0.8 V 1
Input Leakage Current
Output Leakage Current
Output High Voltage IOH = -5 mA VOH 2.4 Vcc V
Output Low Voltage IOL = 4.2 mA VOL 0 0.4 V
CH
T2316162A
*Stresses greater than those listed under "Absolute
Maxi mum Rat ings" ma y caus e per manent damag e
to the device. This is a stress rating only and
………0°C to +70°C
0V ≤ VIN ≤ 7V
0V ≤ V
Output(s) disabled
OUT
≤ 7V
functional operation of the device at these or any
other conditions above those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
reliability.
ILI -10 10 uA
ILO -10 10 uA
Note: 1.All Voltages referenced to Vss
DESCRIPTION CONDITIONS SYM. -45 -50 -60 UNITS NOTES
Operating Current
TTL Standby Current
RAS-only refresh Current
EDO Page Mode Current tPC = min I
CAS Before RAS Refresh
Current
CMOS Standby Current
1. Icc depends on output load condition when the device is selected.
Note:
Icc max is specified at the output open condition.
2. Address can be changed twice or less while
3. Address can be changed once or less while
RAS,CAS cycling , tRC = min
TTL interface,
CAS=VIH, D
t
RC = min I
t
RC = min Icc5 190 180 170 mA
CMOS interface,
0.2V
RAS,
=High-Z
OUT
RAS,CAS>Vcc-
RAS
CAS
= VIL.
= VIH.
Icc1 190 180 170 mA 1,2
I
2 2 2 mA
cc2
190 180 170 mA 2
cc3
150 140 130 mA 1,3
cc4
I
1.0 1.0 1.0 mA 1
cc6
MAX
TM Technology Inc. reserves the right P. 3 Publication Date: APR. 2002
to change products or specifications without notice. Revision:E
TE
tm
CAPACITANCE
(Ta =25°C, Vcc =5V ±10 %)
Input Capacitance (address) CI1 - 5 pF 1
Input Capacitance (clocks) CI2 - 7 pF 1
Output Capacitance (data-in, data-out) CDQ - 10 pF 1
1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
Note:
AC ELECTRICAL CHARACTERISTICS
(Ta =0 to 70°C, Vcc=5V ±10 %, Vss=0V)
Test Conditions
CH
T2316162A
Parameter Symbol Typ Max Unit Notes
(note 14)
(note 29)
AC CHARACTERISTICS
PARAMETER
Read or Write Cycle Time tRC 80 84 110 ns
Read Write Cycle Time t
EDO-Page-Mode Read or Write Cycle Time tPC 16 20 25 ns 22
EDO-Page-Mode Read-Write Cycle Time t
RAS
CAS
OE
CAS
RAS
Precharge
Lead Time
Access Time From
Access Time From
Access Time From
Access Time From Column Address tAA 19 25 30 ns
Access Time From
RAS
Pulse Width
RAS
Pulse Width (EDO Page Mode)
RAS
Hold Time
RAS
Precharge Time
CAS
Pulse Width
CAS
Hold Time
CAS
Precharge Time (EDO Page Mode)
RAS
CAS
Row Address Setup Time t
Row Address Hold Time t
RAS
Column Address Setup Time t
Column Address Hold Time t
Column Address Hold Time (Reference to
RAS
Column Address to
CAS
to
to
to Column Address Delay Time
)
Delay Time
RAS
Precharge Time
SYM
RWC
PCM
t
RAC
t
CAC
t
OAC
t
ACP
t
RAS
t
RASC
t
RSH
tRP 28 30 40 ns
t
CAS
t
CSH
tCP 5 6 10 ns 23
t
RCD
t
CRP
ASR
RAH
t
RAD
ASC
CAH
tAR 35 38 45 ns
t
RAL
MIN MAX MIN MAX MIN MAX
105 113 140 ns
46 58 70 ns 22
45 50 60 ns 4
11 13 15 ns 5,20
11 13 15 ns 13,20
22 27 35 ns 20
45 10K 50 10K 60 10K ns
45 100K 50 100K 60 100K ns
11 13 15 ns 27
6 10K 8 10K 15 10K ns 26
40 40 60 ns 19
10 34 12 37 20 45 ns 7,18
5 5 5 ns 19
0 0 0 ns
5 8 10 ns
8 26 10 28 12 30 ns 8
0 0 0 ns 18
6 8 10 ns 18
19 23 30 ns
-45
-50 -60
UNIT Notes
TM Technology Inc. reserves the right P. 4 Publication Date:APR. 2002
to change products or specifications without notice. Revision:E
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