Taiwan Memory Technology T224162B Datasheet

TE

C

H

tm

RAS

CAS

CASL

T224162B

DRAM

FEATURES

•

Industry-standard x 16 pinouts and timing

functions.

•

Single 5V (±10%) power supply.

•

All device pins are TTL- compatible.

•

512-cycle refresh in 8ms.

•

Refresh modes:

RAS

only,

CAS

BEFORE

(CBR) and HIDDEN.

•

Extended data-out (EDO) PAGE MODE

access cycle.

•

BYTE WRITE and BYTE READ access

cycles.

OPTION

TIMING EDO MARKING

22ns 125 MHz -22
25ns 100 MHz -25
28ns 100 MHz -28
35ns 83 MHz -35
45ns 60 MHz -45
50ns 50 MHz -50

PACKAGE MARKING

SOJ J
TSOP(II) S

GENERAL DESCRIPTION

The T224162B is a randomly accessed solid state
memory containing 4,194,304 bits organized in a x16
configuration. The T224162B has both BYTE
WRITE and WORD WRITE access cycles via two

CAS

pins. It offers Fast Page mode with Extended
Data Output.
The T224162B
determined by the first
by the last to transition back high. Use only one of
the two

CAS

and leave the other staying high during
WRITE will result in a BYTE WRITE.
transiting low in a WRITE cycle will write data into
the lower byte (IO1~IO8), and
will write data into the upper byte (IO9~16).

function and timing are

CAS

to transition low and

CASH

transiting low

256K x 16 DYNAMIC

EDO PAGE MODE

PIN ASSIGNMENT ( Top View )

Vcc
I/01
I/02
I/03
I/04
Vcc
I/05
I/06
I/07
I/08

NC
NC

WE

RAS

NC

A0
A1
A2
A3

Vcc

Vcc
I/01
I/02
I/03
I/04

Vcc
I/05
I/06
I/07
I/08

NC
NC

WE

RAS

NC

A0
A1
A2
A3

Vcc

10
11
12
13
14
15
16
17
18
19
20

1
2
3
4
5
6
7
8
9

10

TSOP(II)

11
12
13
14
15
16
17
18
19
20

1
2
3
4
5
6
7
8
9

SOJ

40
39
38
37
36
35
34
33
32
31

30
29
28
27
26
25
24
23
22
21

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

RAM

Vss
I/016
I/015
I/014
I/013
Vss
I/012
I/011
I/010
I/09

NC
CASL
CASH
OE
A8
A7
A6
A5
A4
VSS

Vss
I/016
I/015
I/014
I/013
Vss
I/012
I/011
I/010
I/09
NC
CASL
CASH
OE
A8
A7
A6
A5
A4
VSS

Taiwan Memory Technology, Inc. reserves the right P. 1 Publication Date: AUG. 2000
to change products or specifications without notice. Revision:L

TE

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CASH

FUNCTIONAL BLOCK DIAGRAM

WE

T224162B

RAS

CASL

CASH

NO.2 CLOCK

GENERATOR

COLUMN.

ADDRESS

9

A0
A1
A2

A3
A4

A5
A6
A7
A8

REFRESH

CONTROLLER

REFRESH
COUNTER

ADDRESS

9

BUFFERS(9)

NO.1 CLOCK

GENERATOR

CAS

BUFFER

9

ROW.

CONTROL

LOGIC

9

ROW

DECODER

9

512

COLUMN

DECODER

DATA-IN BUFFER

512

SENSE AMPLIFIERS

VO GATING

512 x 16

512 x 512 x 16

MEMORY

ARRAY

8

8

DATA-OUT

BUFFER

16

16

OE

Vcc

Vss

DQ01

.
.

DQ16

PIN DESCRIPTIONS

PIN NO. SYM. TYPE DESCRIPTION

16~19,22~26 A0-A8 Input Address Input

14 RAS
28
29 CASL
13 WE
27 OE

2~5,6~10,31~34,36~39 I/O1 - I/O16 Input/ Output Data Input/ Output

1,6,20 Vcc Supply Power, 5V

21,35,40 Vss Ground Ground

11,12,15,30 NC - No Connect

Taiwan Memory Technology, Inc. reserves the right P. 2 Publication Date:AUG. 2000
to change products or specifications without notice. Revision:L

Input Row Address Strobe
Input Column Address Strobe /Upper Byte Control
Input Column Address Strobe /Lower Byte Control
Input Write Enable
Input Output Enable

TE

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RAS

RAS

CAS

>

CAS

RAS

CAS

T224162B

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any pin Relative to VSS..... -1V to +7V

Operating Temperature, Ta (ambient) ..0°C to +70°C

Storage Temperature (plastic)........ -55°C to +150°C

Power Dissipation ............................…...........

1.0W

Short Circuit Output Current.......…............... 50mA

*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other
conditions above those indicated in the operational
sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED
OPERATING CONDITIONS

(0°C ≤ Ta ≤ 70°C; VCC = 5V ± 10 % unless otherwise noted)

DESCRIPTION CONDITIONS SYM. MIN MAX UNITS NOTES

Supply Voltage
Supply Voltage
Input High (Logic) voltage
Input Low (Logic) voltage
Input Leakage Current 0V ≤ VIN ≤ 7V ILI -10 10 uA

Output Leakage Current
Output High Voltage IOH = -5 mA VOH 2.4 Vcc V

Output Low Voltage IOL = 4.2 mA VOL 0 0.4 V

0V ≤ V
Output(s) disabled

OUT

≤

7V

Vcc 4.5 5.5 V 1

Vss 0 0 V

VIH 2.4 Vcc+1 V 1

VIL -1.0 0.8 V 1

ILO -10 10 uA

Note: 1.All Voltages referenced to Vss

MAX

DESCRIPTION CONDITIONS

Operating Current

Standby Current

RAS

-only refresh

Current
Standby Current

Before

Refresh Current
EDO Page Mode Current tPC = min Icc7 190 180 170 150 130 110 mA 1,3

1. Icc depends on output load condition when the device is selected.

Note:

Icc max is specified at the output open condition.

2. Address can be changed twice or less while

3. Address can be changed once or less while

RAS,CAS

TTL interface,

CAS

CMOS interface,
Vcc-0.2V

t

RC = min I

RAS

t

RC = min Icc6 190 180 170 150 130 110 mA

cycling , tRC = min

=VIH, D

=V

IH,

OUT

CAS

,

=High-Z

,

=VIL

RAS

= VIH.

-22 -25 -28 -35 -45 -50

Icc1 190 180 170 150 130 110 mA

4 4 4 4 4 4 mA

I

cc2

2 2 2 2 2 2 mA

190 180 170 150 130 110 mA

cc3

I

5 5 5 5 5 5 mA

cc5

= VIL.

1,2

2

1

Taiwan Memory Technology, Inc. reserves the right P. 3 Publication Date: AUG. 2000
to change products or specifications without notice. Revision:L

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MAX

MAX

CAS

Access Time From Column

RAS

K

RAS

CAS

TE

RAS

- 10 pF 1

I/O

(note 14)

Output Load: 2TTL gate + CL (50pF)

SYM

tRC 42 45 48 65 85 100

RWC

tPC 8 10 10 12 16 20 ns 22

t

PCM

t

RAC

t

CAC

t

OAC

-22 -25 -28 -35 -45 -50

MIN MAX MIN MAX MIN MAX MIN MAX MIN

62 65 70 95 115 135 ns

30 32 34 40 46 57 ns 22

22 25 28 35 45 50 ns 4
7 7 7 9 11 13 ns 5,20

8 8 8 9 11 13 ns 13,20

CAPACITANCE

(Ta =25°C, Vcc =5V ±10 %)

Parameter Symbol Typ Max Unit Notes

Input Capacitance (address) CI1 - 5 pF 1
Input Capacitance (clocks) CI2 - 7 pF 1
Output Capacitance (data-in, data-out) C

1. Capacitance measured with Boonton Meter or effective capacitance measuring method.

Note:

AC ELECTRICAL CHARACTERISTICS

(Ta =0 to 70°C, Vcc=5V ±10 %, Vss=0V) Input timing reference levels: 0.8V, 2.4V
Test Conditions

AC CHARACTERISTICS

PARAMETER

Read or Write Cycle Time
Read Write Cycle Time t
EDO-Page -Mode Read or

Write Cycle Time
EDO-Page -Mode Read-

Write Cycle Time
Access Time From
Access Time From
Access Time From OE

(note 29)

T224162B

MIN

UNIT

ns

Notes

Address
Access Time From

Precharge

Pulse Width

RAS

Pulse Width

(EDO Page Mode)

RAS

Hold Time

RAS

Precharge Time

CAS

Pulse Width

CAS

Hold Time

CAS

Precharge Time

(EDO Page Mode)

to

CAS

to

Time

Taiwan Memory Technology, Inc. reserves the right P. 4 Publication Date:AUG. 2000
to change products or specifications without notice. Revision:L

Delay Time

RAS

Precharge

CAS

tAA 11 12 13 15 19 23 ns

t

13 14 15 18 22 26 ns 20

ACP

t

22 10K 25 10K 28 10K 35 10K 45 10K 50 10K ns

RAS

t

t
tRP 15 15 17 25 35 37 ns
t
t

tCP 3 3 3 3 5 6

t

t

22 100K 25 100K 28 100K 35 100K 45 100K 50 100

RASC

7 7 7 9 11 13 ns 27

RSH

4 10K 4 10K 4 10K 4 10K 6 10K 8 10K ns 26

CAS

19 20 22 30 40 50 ns 19

CSH

9 15 10 17 10 19 10 26 10 34 19 37 ns 7,18

RCD

3 3 3 3 5 5 ns 19

CRP

ns

ns 23

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RAS

CAS

RAS

AC ELECTRICAL CHARACTERISTICS

(continued)

T224162B

AC CHARACTERISTICS

SYM

PARAMETER

Row Address Setup Time
Row Address Hold Time

to Column Address

Delay Time
Column Address Setup Time
Column Address Hold Time
Column Address Hold Time
(Reference to
Column Address to

RAS

)

RAS

Lead Time
Read Command Setup Time

t

ASR

t

RAH

t

RAD

t

ASC

t

CAH

tAR 17 19 21 30 40 45 ns

t

RAL

t

RCS

Read Command Hold Time

t

Reference to

CAS

Read Command Hold Time
Reference to

RAS

to Output in Low -Z
Output Buffer Turn-off
Delay From

CAS

or

RAS

Output Buffer Turn-off to

OE
Write Command Setup Time
Write Command Hold Time

Write Command Hold Time
(Reference to

RAS

)

Write Command Pulse
Width

Write Command to

RAS

Lead Time
Write Command to

CAS
Lead Time
Data -in Setup Time
Data -in Hold Time
Data -in Hold Time

(Reference to

RAS

to

WE

)

Delay Time

RCH

t

RRH

t

CLZ

t

OFF1

t

OFF2

t

WCS

t

WCH

t

WCR

tWP 4 4 4 4 6 8 ns

t

RWL

t

CWL

tDS 0 0 0 0 0 0 ns
tDH 4 4 4 4 6 7 ns

t

DHR

t

RWD

AC ELECTRICAL CHARACTERISTICS

-22 -25 -28 -35 -45 - 50

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

0 0 0 0 0 0 ns

5 5 5 5 5 5 ns

8 11 8 12 8 13 8 20 8 26 10 29 ns

0 0 0 0 0 0 ns

4 4 4 4 6 7 ns

11 12 13 15 19 23 ns

0 0 0 0 0 0 ns

0 0 0 0 0 0 ns

0 0 0 0 0 0 ns

3 3 3 3 3 3 ns

3 3 3 3 15 3 15 3 15 ns

8 8 8 8 8 8 ns

0 0 0 0 0 0 ns

4 4 4 4 6 7 ns

19 19 21 30 46 51 ns

6 6 6 7 9 10 ns

5 5 5 7 9 11 ns

19 19 21 30 40 45 ns

31 34 37 51 61 70 ns

continued

(

)

UNIT

Notes

8

18
18

15,18
9,15,
19

9

20
10,17,

20
17,28

11,15,
18

15,27
15

15

15

15,19

12,20
12,20

11

Taiwan Memory Technology, Inc. reserves the right

P. 5

Publication Date:AUG. 2000

to change products or specifications without notice. Revision:L