Taiwan Memory Technology T221160A-30J, T221160A-35S, T221160A-35J, T221160A-30S Datasheet

tm

TE

CH

T221160A

DRAM

FEATURES

High speed access time : 25/30/35/40 ns

•

Industry-standard x 16 pinouts and tim ing

•

functions.

Single 5V (±10%) power supply.

•

All device pins are TTL- compatible.

•

256-cycle refresh in 4ms.

•

Refresh modes:

•

RAS

(CBR) and HIDDEN.

Conventional FAST PAGE MODE access cycle.

•

BYTE WRITE and BYTE READ access cycles.

•

RAS

only,

CAS

BEFORE

PART NUMBER EXAMPLES

PART NUMBER

T221160A-30J T221160A-30S

T221160A-35J T221160A-35S

ACCESS TIME PACKAGE

30ns SOJ 30ns TSOP-II

35ns SOJ 35ns TSOP-II

64K x 16 DYNAMIC RAM

FAST PAGE MODE

PIN ASSIGNMENT ( Top View )

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

Vss I/016 I/015 I/014 I/013 Vss I/012 I/011 I/010 I/09 NC CASL CASH OE NC A7 A6 A5 A4 VSS

Vc c I/01 I/02 I/03 I/04 Vc c I/05 I/06 I/07 I/08

NC NC

W E

R A S

NC

A0 A1 A2 A3

Vc c

10 11 12 13 14 15 16 17 18 19 20

1 2 3 4 5 6 7 8 9

SOJ

GENERAL DESCRIPTION

The T221160A is a randomly accessed solid state memory containing 1,048,551 bits organized in a x16 configuration. The T221160A has both BYTE WRITE and WORD WRITE access cycles via two

CAS

pins. It offers Fast Page mode operation

CAS

The T221160A determined by the first by the last to transition back high. Use only one of

CAS

the two

and leave the other staying high

during WRITE will result in a BYTE WRITE.

CASL

transiting low in a WRITE cycle will write data into the lower byte (IO1~IO8), and transiting low will write data into the upper byte (IO9~16).

function and timing are

CAS

to transition low and

CASH

Vcc I/01 I/02 I/03 I/04 Vcc I/05 I/06 I/07 I/08

NC NC

W E

RA S

NC A0 A1 A2 A3

Vcc

1 2 3 4 5 6 7 8 9

10

TSO P (II)

11 12 13 14 15 16 17 18 19 20

40

Vss

39

I/016

38

I/015

37

I/014

36

I/013

35

Vss

34

I/012

33

I/011

32

I/010

31

I/09

30

NC

29

CASL CASH

28

OE

27 26

NC

25

A7

24

A6

23

A5

22

A4

21

VSS

Taiwan Memory Technology, Inc. reserves the right P. 1 Publication Date: FEB. 2002 to change products or specifications without notice. Revision:A

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FUNCTIONAL BLOCK DIAGRAM

CH

T221160A

WE

RAS

A0 A1 A2 A3 A4 A5 A6 A7

CASL CASH

NO.2 CLOCK

GENERATOR

COLUMN.

ADDRESS

8

REFRESH

CONTROLLER

REFRESH

COUNTER

ADDRESS

8

BUFFERS(8)

NO.1 CLOCK

GENERATOR

BUFFER

8

ROW.

CAS

CONTROL

LOGIC

8

DATA-IN BUFFER

DQ01

OE

Vcc

Vss

. .

DQ16

16

DATA-

OUT

BUFFER

COLUMN

8

DECODER

256

SENSE AMPLIFIERS

256

ROW

DECODER

8

VO GATING

256 x 16

256 x 256 x 16

MEMORY

ARRA

Y

8

16

PIN DESCRIPTIONS

PIN NO. SYM. TYPE DESCRIPTION

16~19,22~25 A0-A7 Input Address Input

14 28 29 13 27

2~5,6~10,31~34,36~39 I/O1 - I/O16 Input/ Output Data Input/ Output

1,6,20 Vcc Supply Power, 5V

21,35,40 Vss Ground Ground

11,12,15,30 NC - No Connect

Taiwan Memory Technology, Inc. reserves the right P. 2 Publication Date: FEB. 2002 to change products or specifications without notice. Revision:A

RAS CASH CASL

WE

OE

Input Row Address Strobe Input Column Address Strobe /Upper Byte Control Input Column Address Strobe /Lower Byte Control Input Write Enable Input Output Enable

TE

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ABSOLUTE MAXIMUM RATINGS*

Voltage on Any pin Relative to VSS… … -1V to 7V Operating Temperature, Ta (ambient)..0°C to +70°C

Storage Temperature (plastic)….... -55°C to +150°C

Power Dissipation ...............................…......... 1.0W

Short Circuit Output Current...................….... 50mA

*Stresses greater than those listed under "Absolute Maxi mum Rat ings" ma y caus e per manent damag e

DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS

(0°C ≤ Ta ≤ 70°C; VCC = 5V ± 10 % unless otherwise noted)

DESCRIPTION CONDITIONS SYM. MIN MAX UNITS NOTES

Supply Voltage Vcc 4.5 5.5 V 1 Supply Voltage Vss 0 0 V Input High (Logic) voltage VIH 2.4 Vcc+1 V 1 Input Low (Logic) voltage VIL -1.0 0.8 V 1 Input Leakage Current

Output Leakage Current Output High Voltage IOH = -5 mA VOH 2.4 - V

Output Low Voltage IOL = 4.2 mA VOL - 0.4 V

CH

T221160A

to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

0V ≤ VIN ≤ 7V 0V ≤ V

Output(s) disabled

OUT

≤ 7V

ILI -10 10 uA

ILO -10 10 uA

Note: 1.All Voltages referenced to Vss

Taiwan Memory Technology, Inc. reserves the right P. 3 Publication Date: FEB. 2002 to change products or specifications without notice. Revision:A

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DC CHARACTERISTICS

(Ta = 0 to 70°C, Vcc = 5V ±10%, Vss = 0V)

CH

T221160A

Parameter

Operating Current

Standby Current

Fast Page Mode Current

RAS

-only refresh

Current

CAS

Before

Refresh Current

RAS

-25 -30 -35 -40

Symbol

Min Max Min Max Min Max Min Max

Icc1 - 170 - 150 - 130 - 120 mA

Icc2 - 4 - 4 - 4 - 4 mA

Icc3 - 2 - 2 - 2 - 2 mA

Icc4 -

Icc5 -

Icc6 -

170

-

150

-

150

-

150

-

130

-

130

-

130

-

120

Unit

mA

Test Condition

RAS, CAS

tRC=min TTL interface,

RAS,CAS

D

OUT

CMOS interface,

RAS, CAS RAS

=VIL,

cycling, tPC= min

CAS

=VIH,

cycling, tRC= min

RAS,CAS

tRC= min

cycling

=VIH,

=High-Z

> Vcc-0.2V

CAS

RAS

cycling,

Note: Icc depends on output load condition when the device is selected. Icc max is specified at the output open condition, Icc is specified as an average current.

CAPACITANCE

(Ta =25°C, Vcc =5V, f = 1M HZ)

Parameter Symbol Typ Max Unit

Input Capacitance

(address)

Input Capacitance

RAS,CAS,WE,OE

(

Output Capacitance

(data-in/out)

)

CI1 - 5 pF

CI2 - 7 pF

C

- 10 pF

I/O

Taiwan Memory Technology, Inc. reserves the right P. 4 to change products or specifications without notice. Revision:A

Publication Date: FEB. 2002

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T221160A

AC CHARACTERISTICS

(note 1,2,3) (Ta = 0 to 70°C)

AC TEST CONDITIONS: Vcc=5V ±10%, input pulse level = 0 to 3V Input rise and fall times: 2ns Output Load: 2TTL gate + CL (50pF)

PARAMETER

SYM

-25 -30 -35 -40 AC CHARACTERISTICS

MIN MAX MIN MAX MIN MAX MIN MAX

Read or Write Cycle Time tRC 43 55 65 75 ns Read-Modify-Write Cycle Time t

65 85 95 105 ns

RWC

Fast-Page-Mode Read or Write Cycle Time tPC 15 20 23 25 ns Fast-Page-Mode Read-Write Cycle Time t

Access Time From Access Time From Access Time From

RAS CAS OE

37 42 49 52 ns

PCM

t

25 30 35 40

RAC

t

7 8 9 10

CAC

t

7 8 9 10

OAC

Access Time From Column Address tAA 12 16 18 20 ns

t

CAS

Access Time From

RAS

Pulse Width

RAS

Pulse Width

RAS

Hold Time

RAS

Precharge Time

CAS

Pulse Width

CAS

Hold Time

CAS

Precharge Time RAS CAS

to

CAS

Delay Time

RAS

Precharge Time

Precharge

Row Address Setup Time t Row Address Hold Time t

RAS

to Column Address Delay Time

Column Address Setup Time t Column Address Hold Time t Column Address Hold Time (Reference to

RAS

)

RAS

Column Address to

Lead Time

Read Command Setup Time t

CAS RAS

or

Read Command Hold Time Reference to Read Command Hold Time Reference to

CAS

to Output in Low-Z

Output Buffer Turn-off Delay From

RAS

CAS

14 18 20 22

ACP

t

25 10K 30 10K 35 10K 40 10K

RAS

t

RASC

t

7 8 9 10

RSH

25

100K

30

100K

35

100K

40

tRP 15 20 23 25 t

4 10K 6 10K 8 10K 10 10K

CAS

t

21 26 30 35

CSH

3 3 4 5

tCP t

10 17 10 21 10 25 10 29

RCD

t

3 3 3 5

CRP

0 0 0 0 ns

ASR

5 5 5 5 ns

RAH

t

8 13 8 14 8 16 8 18

RAD

0 0 0 0 ns

ASC

4 4 4 5 ns

CAH

tAR 22 26 30 34 t

12 14 16 18

RAL

0 0 0 0 ns

RCS

t

0 0 0 0

RCH

t

0 0 0 0

RRH

t

3 3 3 3

CLZ

t

3 15 3 15 3 15 3 15

OFF1

100K

UNIT

ns ns ns

ns ns ns ns ns ns ns ns ns ns

ns

ns ns

Notes

4 5 13 8

7

8

14 9,14

9

10,16

Taiwan Memory Technology, Inc. reserves the right P. 5

Publication Date: FEB. 2002

to change products or specifications without notice. Revision:A

Taiwan Memory Technology T221160A-30J, T221160A-35S, T221160A-35J, T221160A-30S Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

DRAM

FAST PAGE MODE

GENERAL DESCRIPTION

ABSOLUTE MAXIMUM RATINGS*

DC CHARACTERISTICS