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@='.'IUNEFI

CORPORATION

ITARRAlITY

Systron-Donner originol

opply to vocuum

Seller under

thereof which is returned by Buyer

subiected to misuse, neglect,

shotl

evenf sholl

of ony other worronty,

it willbe

purchoser

hou.

instruments

to be

tubes,

this worronty

the

right of

Seller be lioble for

binding

upon Seller

ore

wqrronted during

free from defects

except

express, implied

os they

is limited to replocing or

improper instollotions, repoir,

finol

determinqtion os to the

colloterol or

unless

RECEr Vt lrG

Every

Systron Donner instrument

time domoged portotion

shipment.

of

in ony woy compony.

Eoch instrument should

or

foils to operote, o

is corefully inspected

period

o

in moteriol ond

worronted by tube monufocturers. The

ore

repoiring ony

ot

his expense

or stotutory,

in writing ond signed

during

consequenfiol

ond

|l{SPICTt0}l

be checked

should

cloim

REPAIRS

yeor

of

one

workmonship.

period

such

olterotion,

existence

no

by o duly

ond

os soon os

immediotely

ond

domoges.

ogreement

perfect

is in

from dqte of

Thisworronty

instrument or

ond

which hos

or occident.

couse of o defect.

This

extending

outhorized

working order ot

received.

filed

be

shipment

liobility

component

worronty

or modifying

officer.

the

lf

with the trons-

to

does

not

of

not been

Seller

no

In

is in lieu

the

is

unit

Whenever o

totive should foctory

Pleose

instruments.Address totive

Colifornio.

Systron-Donner instrument

be contocted; oll representotives

refurns when

specify

or

both model ond

Soles

Monoger, Instrumenti,

requires

necessory.

seriol number in

oll inquiries on operotion or

Systron-Donner Corporotion,

GONCORDI

qll

GALIFORNIA

service, fhe

will

correspondence

opplicotions to

neorest Systron-Donner repreSon-

provide

immediote

your

SSS

service

concerning Systron-Donner

neorest soles

GolindoStreet,

or

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0F

C0NTENTS

(

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Page

CHAPTER 5 CALIBRATI0N-MAINTENANCE

5.4.2

Oscillator

5.4.3 200 Ir{Hz Input

(Schematic

5.4.4 Acto

Adjustment

Amp

D3909

5.5 Board Repair

CHAPTER 6 - DRA|'lINGS

t'lodel Final

C39082C

6053/3 Block Diagram

Assembly Parts

C39448R2

AND PARTS

Power

AI, A1, Power Parts

List

A2, Shield

LIST

List

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Supply

Board

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and Decade

5)

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Parts List

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D39095E

C39087D

C27 988L

CHAPTER

7 STANDARD

7

.L

Option

A4, 200MHz

D39098F

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A4 , 20 D390958 Parts List

A5,

Acto P.C A5, Acto Parts

A6, It{ixer A6,

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OPTIONS

Introduction

10

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TABLE

l.l

SPECIFICATI0NS

(Cont'd)

Itigh-Frequency

Ittaximurn Without Damage:

Input

Accuracy:

Resolution:

Reads In:

Range Input Frequency

Type

Sensitivity:

Irlaximun Without Damage :

Input

Impedance:

Connectori Type BNC.

of Signal:

Input 2.33V

Range:

5 0 0V dc , 20 0V rms

1M0.

tI

count

accuracy.

100kHz to 0.1H2 in

decade stepE.

MHz or GHz.

.2cldz

Cw.

50mV

to

rms

ttine

3GHz"

(-7

(+20

base

dBm) .

aIBm)

itins

steps.

at

of 60H2.

.

(+7

.

modulation

Maxinun

Input:

Input Impedance: 500 noninal

Input Connector: Type N.

Accuracy:

Resolution: 100kHz to o.lHz

Reads

Acquisiti.on Time:

FM Tolerance:

Uaable

Ins

500mV rmg

tl

count

accuracy.

decade

MIIZ or GHz.

200ms

Maximum of o.It viation

frequency Permissible deviation is reduced 50t eacnof modulation quency

typical

increasing octave

tlBm)

bAfe

in

de-

for

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Options

TABLE l.l SPECIFICATI0NS

B3 Aging

Long-Term

30 days. Short-Term rms/Is average.

Rate:

(Cont'd)

<+3

Aging Rate:

parts

in LOa t3 parts

tl- part

/24

hours.

in

L08/

in I0r0

B

B4

E

D3

& EE

Aging Long-Term

30 days. Short-Term rms/ls

Aging

hours Long-Term

LOs Short-Term Aging I0t

Additional decade indicator to

crease

9

L-2-4-8

formation at rear

I' f I'

state level

command

positive

ative

column

of

Rate:

.

/30

1

/Ls

(EE

)

state

reference

digits.

Aging

average.

Aging

clays.

average.

count

digits

BCD Output:

of

panel

level

at 0V

the

at

reference

capacity

part

<+1

Rate:

Rate: tI

<t5 parts

Rate3

Rate:

capacity

.

at

end

level

equal

panel

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tI5V

vided

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power

secondary

obtained:

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dc

with

Supply

arrives

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at the

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primary

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power

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tubes)

dc and

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line

the following voltages

,

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provides

dc

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dc

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are

transfor-

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three

and

,

pro-

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830.

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tif dc ulator,

the

current at

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tapped

regulated

fed

plifier

and

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same.

R9 will track.

Supply

ier, potential

series

Supply

through

R9

supply voltage

to the

CRI--CR4,

UI.

secondary

Q2

at

R7

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indicator

(

regulated)

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which is

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suppty.

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and

potential.

0

R9 are equal,

and

if R2 adjusts

5V rms

supply is based on 35V

winding, 10-11-12. A

and

regulated

transistor

-82L.

819

supply

winding, 10-LL-L?t

The pass

Q3.

This amplifier keeps

300mA

is

f rom the T1

tube

f ilter

applied to the integrated

is based on

-22 transistor

is available

produced

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circuitry on

capacitor C2

+15V Ql,

volt dc

the voltage

the

output

permitting

+15V

in

secondary

resultant

and

potential,

Q4

supply,

at

following

the

windi.nrg,

voltage

Readout Board via

the

rms from the

fulf-wave bridge

produce

is then controlled

about 300mA

rms from

35V

referenced

fLltered

the differential

to

junction

the

drop

pins

across each the

826-E28.

is distri-

+22

a

.circuit

the centerto

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volts

manner:

5-6

maximum

the

of

is

center-

rec-

vo1t

reg-

by

+15V

by C3,

am-

R7

is the

across

is

+

5L. Supp

From CR6-CR9 resulting regulated

1.35A of

-

2V

5

.

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-9V

a the differential sulting

ACTO

This ferential transistor

ACTO

grounded, turning

ly ( regu l ated

secondary winding

potential

+9V

a

,

current

(

Supp]y

secondary

potential

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(regulated)

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supply

enable

regulated

winding

is

is referenced

pair

Q1l

line

contained allows

4-2

)

+5vis 824-E'25,

at

)

to buf f er

f ed

amplifier

regulated

the

2.0A maximum

which

on

enables

U3.

7-8-9

is fed

7-8-9 of

in U3

of

then

and

Q5

to the

T1 and

to IC regulator lJ2.

passed

T1 and

amplif

Q6

+5V

+15

and adjusted

at

when

Q10

the full-wave

by

the

ier

which

supply.

volt

E.22-F.23. I.29

the

providing about

Q9

,

fulI-wave

and

Q7 references

supply

by

ACTO

by the

R17.

QB;

line

bridge'

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bridge, tiren,

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the

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is the

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TII,IE BASE

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Ul5

8

9

8

STOP Ul6

EFFECTIVE

TRANSTER

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4-4

LENGTH

9

FIGURE

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Internal

P ins

E4

TABLE

4. I LOGIC

E8

STATES

E9

Remote

P ins

Remote

100

kEz

10 kllz

I kHz

I00

Hz

t0 Hz

lHz

0.1 Hz

The logic level at J5 if and 4 to the I state. Pin 3 goes

Q6 current to the

to a L state. Pin 6

off, extinguishing the GHz lamp and

E37

0

'l

o

f"",

,J

r1,,""

IJ

MHz

lamp.

839

1

0

I

0

I

it is in the 1 state,

of U15

of U14 then

841

I

0

t

0

I

0

I

Decimal

Pos ition

goes

turning

Point

4

5

6

4

5

6

7

drives U14

to 0 and

to a

0 state

Q7

Binary Number

3

0

1

2

4

5

6

7

pins

5 of U15

turning

on; thus, supplying

1,

2

0

A

pin current to the GHz lamp, turning lanp.

Decimal Point

There are three decimal points

tions 4, 5t the points a 4 to U29 are

,J5

at 4, U14

same in the MHz range

has the opposite effect. By the

6 is driven to a l-

points

in

the MHz range.

They

6, and

are

located

1O-line converter.

3

Tube

4

5

6

7

7.

in the

A

0

I

0

I

As

and

display

The

B

0

I

seen from the

arerwith

state

Q7

in the

in

the

logic levels

c

I

1

I

1

off, extinguishing the

GHz range and

the GHz

tubes

D

0

presence

turning

chart exception range.

are

and

at the

of a 0 at UI4

on, supplying

Q6

MHz

four

they are

of

The

switched by U29,

inputs of

decimal

posi-

number

decimal

7,

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down in the negative

The

dual- JK 9 in pin

13

(pin

driven.

the

7

)

reset

logical

(0)

to

state.

0

pulse

flip-flop

is

irt

be

in the

at

U16

0 state.

the l

state

0 state

12 had

is

been

6 and

initially

(Low

and preventing

voltage

is

set to

2.

reset

state.

inverted

the

with

by

I

I state

The

)

Ut7 to

(O)

voltage

f rom

by the

12

and

cauie being

pin at J

Upon L2 to

being

The the

state

The pin

further

gate

Transfer

When the right-hand to

which

and Q10

decades to

The stored line information

Reset

receipt

is

driven

open. At

inverted

and

time

(0)

8

inputs

and the

the

I state. This

it. is differentiated

turns

which

of one to the the same

by

time base

flip-flop because pin

inhibits

base

Pulse

does drive

to be in

will be

6053 count

off

Q10.

transfers the BCD

the

SN7

BCD now contained

of the

I

state time

UI7

47

and

brings

,

pulse

the

the O state.

f lip-f

A

5 storage

arriving

flip-flop.

the right

accepted.

chain no

is inverted

positive

drives

time

lop

by

base

which

13

in

C4

pulse

information

packs.

in

the

gas

the

pulses permits goes 7

at

Pin 8 now

longer

UI6 is driven,

by

and

to the

(A

input)

pins

(K)

3

hand

l0

the

R24.

appears

SN7475ts is

display

at

the

I and is held

flip-ftop

(J)

is inhibits

has an

gate

ft

at

contained

tubes Vl

pins

6053 signal 0 state to the

grounaea

input.

Q

function

passes

I and

and

I state.

5

cannot

in

the

(pin

the collector

in

converted

5)

the

9 ) is

UIl after

through

the

thru V9.

5,

gate

after

d.rive

0

causing

so no

signal

count

to 10

d,riven

CR2

of

Pin 8 of the count charging to

junction positive to the base of 8 of U16

ground.

4.

The count chain consists U56. U35 is a first but instead, is decade is and signal Decade assembly.

The output of Et8 the U38, and

of U16 is coupled thru

period

+15V transistor pulse

positive, Now

Count Chain

decade in the

capable

and

819. The signal is

input

(pin

so

is developed Q14.

the

SN7490, the

gating

the

f4) of U35. Pin

on.

QL2

thru

whole

a

separate

R33.

Q13

A reset

causing

count chain

of counting circuits are inctuded

first

cycle

P.27

turns

When it

fires,

across pulse

QL2

repeats.

of

U35, U38,

remainder

assembly.

decade

amplified

to the base

off. C5 is

reaches

discharging

R29 and coupled

generated

is

to

turn

are

is not

up

comes into

H

200MHz.

to

of U35 couples to

then

on

U4I

r

SN7090 decades.

the

on

In the

on

the

by

Q4

of

QJ-z.

permitted

about

c5 to ground.

which drives

and clamp

tJ44,

the

and

U47,

read-out board, 6053 the first The input amplifier

separate

Readout Board at

Q5;

At

the end

+7V

the uni-

through R30

C5 to

U50,

Annp and

then, drives

t4 of

to

A

U53,

The

begin

and

4-B

6053/3-t

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'

-:e66r-:1

6-t

zero This UI6 which the stop JK flip-fIop. state and inhibits U20 and

During the time line the counting decades

If frequency is 6053 readout

state. This is inverted.

permits

no

V2L

the time

baseruls

are both near

=

N

100. and the ACTO

longer count

1900.0MH2 or I.9GHz tubes.

occurs

by u17

the leading

U15. The

that the

ground

the

on

4,

5, and

edge

Pin I

+16

Srthe

are counting

VCO

of

preset

the time

preset-reset

start

in the

frequency

trailing

of

U16 is driven

divide-by-sixteen

line, and U15

zero state. During

the

and

edge

and enables

6 the

time base

base.

counters

ACTO VCO =

19MHz,

will

be displayed

of a timing

to the zero

frequency.

then

pulse.

are counting

7 of

to drive

counters

grthe

this

the input

stop time

by the

4,3,4

The following

The input the input and has

The output of the attenuator is transistor and is controlled

An emitLer follower

amplifier

The Q9-Q12.

age trigger cause

200MHz AMP

200MHz

1. X100 Input Attenuator.

2.

3. Two

4.

5.

6. 2Q1MHz MECL

output of

at the input

the

Amp

sections:

High input impedance,

stages

follower

Schmitt trigger.

Signal Gate.

TTL

BCD logic level

to

the

attenuator. This

an attenuation factor

Q2.

Q5, Q6 , Q7

The

operational amplifier

level

two voltages to become

AND DECADE

Decade

and

grounded

of

amplifier.

decade counts with translator to

200MHz

This transistor

by the bias

is applied to

QB

to the

pot

(R47

Amp and Decade

dc

Q3

and

,

Schmitt triggerr

)

,

(Schematic

circuit

output.

att,enuator

couples Q8.

adjusts

D39095)

description consists

gain-controlled

emitter and two stages of emitter

is capacitor-coupled is controlled by

Xl

of

applied

has

gate

on

this

the input

the equal.

X100.

or

to

a voltage

2.

stage to

of

Ul, by

bias at the base of

comparing the

dnd

input

gate

I

of the

gain

the wide-band

the Schmitt

voltage at the

the

of

of the

stage

provide

a relay

MOS

2

or 0

trigger,

dc

QI

.

to

.2

volt-

to

Two other inputs are on J2-4 The

ACTO. Wherr

by

reverse

The Schmitt trigger

high-speed eircuit. The input

transistor

Q10. by

emitter

I

0

4-

accepts the lMHz test

otherr J4 accepts the

either of

biasing

which

Q9

The

output from

follower

provided

20MHz

these

gate

drives

QLz.

2,

Q9 , QIO,

Q10

thus disabling

emitter

is

coupled.

for the amplifier

frequency

oscillator

two inputs are used

QII,

and

is applied

follower

provided

frequency from

the normal input.

is a conventional

QLz

to the

to

the signal

QIl;

circuit. One

in

the 6053.

the

is turned

Q2

base of

then,

transistor

gate

U2

6053/3-r r

off

4

-70

Systron Donner 6053 Service manual

Specifications and Main Features

Frequently Asked Questions

User Manual