Information in this document is subject to change without notice.
Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. For a list
of Synopsys trademarks, refer to this web page:
http://www.synopsys.com/copyright.html
All company and product names are trademarks or registered trademarks of their
respective owners.
This application note describes the features and use of the ModelSource 640-pin
Generic Device Adapter (hereafter referred to as the “Adapter”), which allows you to
model a 640-pin device using ModelSource modeling systems.
This application note assumes that you are familiar with model-building procedures as
described in these Synopsys documents:
●
Logic Model Development Manual
●
Shell Software Reference Manual
●
ModelSource User’s Manual
●
LM-family Modeler Manual
Related Documents
To see a complete listing, refer to the Guide to Hardware Modeling Documents.
Manual Overview
This manual contains the following chapters and appendixes:
PrefaceDescribes the application note and lists the
typographical conventions and symbols used in it; tells
how to get technical assistance.
Chapter 1
Describing a 640-pin Logic
Model
November 2001Synopsys, Inc.5
Describes the hardware and software needed to create a
Logic Model using the 640-pin Generic Device Adapter.
PrefaceThe ModelSource 640-pin Adapter
Chapter 2
Building the Daughterboard
Chapter 3
Connecting the Daughterboard
Chapter 4
Developing the Shell Software
Chapter 5
Completing the Model
Provides specifications for building the 640-pin Adapter
Daughterboard.
Describes the Adapter and provides a procedure for
connecting it and the Daughterboard.
Briefly outlines software development tasks and
provides references.
Describes mounting the Adapter onto the Modeling
Systems; labeling the Daughterboard; verifying the
model; and unmounting the Adapter.
Appendix A
Provides a pinout listing for J1-J6 connectors.
J1–J6 Connector Pinouts
Typographical and Symbol Conventions
● Default UNIX prompt
Represented by a percent sign (
● User input (text entered by the user)
%).
Shown in
bold type, as in the following command line example:
% cd $LMC_HOME/hdl
● System-generated text (prompts, messages, files, reports)
Shown as in the following system message:
No Mismatches: 66 Vectors processed: 66 Possible
● Variables for which you supply a specific value
Shown in italic type, as in the following command line example:
% setenv LMC_HOMEprod_dir
In this example, you substitute a specific name for prod_dir when you enter the
command.
● Command syntax
Choice among alternatives is shown with a vertical bar ( | ) as in the following
syntax example:
-effort_level low | medium | high
In this example, you must choose one of the three possibilities: low, medium, or
high.
6Synopsys, Inc.November 2001
The ModelSource 640-pin AdapterPreface
Optional parameters are enclosed in square brackets ( [ ] ) as in the following
syntax example:
pin1 [pin2 ... pinN]
In this example, you must enter at least one pin name (pin1), but others are optional
( [pin2 ... pinN]).
Getting Help
If you have a question while using Synopsys products, use the following resources:
1. Start with the available product documentation installed on your network or located
at the root level of your Synopsys CD-ROM. Every documentation set contains
overview information in the intro.pdf file.
Additional Synopsys documentation is available at this URL:
http://www.synopsys.com/products/lm/docs
Datasheets for models are available using the Model Directory:
http://www.synopsys.com/products/lm/modelDir.html
2. Visit the online Support Center at this URL:
http://www.synopsys.com/support/lm/support.html
This site gives you access to the following resources:
❍ SOLV-IT!, the Synopsys automated problem resolution system
❍ product-specific FAQs (frequently asked questions)
❍ lists of supported simulators and platforms
❍ the ability to open a support help call
❍ the ability to submit a delivery request for some product lines
3. If you still have questions, you can call the Support Center:
North American customers:
Call the Synopsys Eaglei and Logic Modeling Products Support Center hotline at
1-800-445-1888 (or 1-503-748-6920) from 6:30 AM to 5 PM Pacific Time, Monday
through Friday.
International customers:
Call your local sales office.
November 2001Synopsys, Inc.7
PrefaceThe ModelSource 640-pin Adapter
The Synopsys Website
General information about Synopsys and its products is available at this URL:
http://www.synopsys.com
Comments?
To report errors or make suggestions, please send e-mail to:
doc@synopsys.com
To report an error that occurs on a specific page, select the entire page (including
headers and footers), and copy to the buffer. Then paste the buffer to the body of your
e-mail message. This will provide us with information to identify the source of the
problem.
8Synopsys, Inc.November 2001
The ModelSource 640-pin AdapterChapter 1: Describing a 640-pin Logic Model
1
Describing a 640-pin Logic Model
This chapter describes the necessary components and provides a procedural summary
for building a 640-pin Logic Model.
Hardware Requirements
To build a complete 640-pin Logic Model using the 640-pin Adapter, you need the
following hardware:
● The device you want to model, henceforth referred to as the device under test
(DUT). The DUT can have up to 640 input, output, and I/O signals, exclusive of
supply voltage and auxiliary signals. The DUT can include more than one physical
package, as long as the components fit within an area approximately 6” x 6”.
● One 640-pin Generic Device Adapter Daughterboard, henceforth referred to as the
“Daughterboard”, to which you attach the DUT.
● Four ModelSource modeling systems, either 4 MS3200 units or 4 MS3400 units.
You cannot mix these two types of units.
● One 640-pin Adapter, which provides the interface between the modeling systems
and the Daughterboard.
November 2001Synopsys, Inc.9
Chapter 1: Describing a 640-pin Logic ModelThe ModelSource 640-pin Adapter
Software Requirements
To support the 640-pin Logic Model, you need the following software:
● User-created Shell Software files, described in the Shell Software Reference
Manual.
● The product-specific Shell Software files GEN640.ADP and GEN640.PKG,
provided by Synopsys and described in later text.
● R3.3b or later of the Runtime Modeler Software.
● The lm utility, R3.3b or later, for labeling the Daughterboard.
Procedural Summary
The steps in building a 640-pin Logic Model are as follows:
1. Build the Daughterboard and attach the DUT to it.
2. Connect the Daughterboard to the Adapter.
3. Develop the model Shell Software.
4. Mount the Adapter onto the ModelSource modeling systems.
5. Label the Daughterboard.
6. Verify the model.
Steps 1, 2 and 4 are described in detail in this application note. Steps 3, 5, and 6 are
summarized here; for more details, refer to the Logic Model Development Manual.
10Synopsys, Inc.November 2001
The ModelSource 640-pin AdapterChapter 2: Building the Daughterboard
2
Building the Daughterboard
This chapter describes the specifications you must meet when building the
Daughterboard.
Daughterboard Description
Figure 1 shows the physical specifications of the Daughterboard from the component
side. The Daughterboard is designed to have a footprint area in excess of 10” by 14”,
allowing for a multi-chip DUT.
Following are descriptions of some of the items shown on the drawing. All connectors
are to be installed from the far side.
● Guide pin holes: These are designed to mate with the guide pins on the Adapter to
ensure correct orientation when attaching the Daughterboard to the Adapter.
● Board stiffeners: Four (two long and two short) are required around the perimeter of
the Daughterboard to reinforce it. Fabrication drawings for compatible long and
short stiffeners are provided in Figure 3 on page 15.
● Connectors J1-J6: These are to be installed from the far side, and are designed to
mate with corresponding connectors on the Adapter. The location of Pin A1 of each
connector is indicated on the drawing. Details of the connector pins are provided in
text that follows.
November 2001Synopsys, Inc.11
Chapter 2: Building the DaughterboardThe ModelSource 640-pin Adapter
Figure 1: 640-pin Adapter Daughterboard
12Synopsys, Inc.November 2001
The ModelSource 640-pin AdapterChapter 2: Building the Daughterboard
Connector Pin Detail
Connectors J1–J6 include the connections (DUT1–DUT640) between the DUT and the
Adapter through the Daughterboard and, in addition, supply voltage, ground
connections, and various auxiliary signals. Figure 2 shows details of J1–J6 connector
pins, from the component side. Pinouts are listed in “J1–J6 Connector Pinouts” on
page 29.
Connectors J1 and J3
These connectors include two each of Teradyne signal modules, and have 6 rows of 48
pins each. You will notice in Appendix A that no connections are listed for Rows B and
E; these are exclusively ground.
Connectors J2, J4, J5 and J6
These connectors include one each of Teradyne signal modules (A1–F24, at the left of
the figure) and two each of Teradyne power modules (AP1–FP4 and AP5–FP8, at the
right of the figure). As with connectors J1 and J3, the left (signal module) side has rows
B and E exclusively connected to ground. The right (power module) side has no rows B,
C, or E.
November 2001Synopsys, Inc.13
Chapter 2: Building the DaughterboardThe ModelSource 640-pin Adapter
Connectors J1 and J3
One Teradyne
Signal Module
1242448
A
B
C
D
E
F
Rows B and E are connected to ground
Connectors J2, J4, J5 and J6
One Teradyne
Signal Module
1
A
B
C
D
E
F
Rows B and E are
connected to grounddo not exist
One Teradyne
Signal Module
Two Teradyne
Power Modules
AP1AP8
DP1DP8
FP1FP8
Rows B, C, and E
Figure 2: Connector Pin Detail, Shown from Component Side
Parts List
The required parts are as follows:
● Eight Teradyne HDM signal modules, 488-5324-XXX. These are available either as
press fit or solder tail, in a variety of tail lengths. The last three digits (XXX) of the
part number depend on which type you choose; for specific part numbers, see the
Teradyne product documentation.
● Eight Teradyne HDM power modules, 437-5034-500. These are currently available
The above does not include the package type designation; that is up to the
model designer.
● Two Synopsys board stiffeners (short), 600-00193 (or build according to
specifications).
● Two Synopsys board stiffeners (long), 600-00XXX (or build according to
specifications).
Figure 3 shows a drawing of the short and long board stiffeners.
Short Stiffener
Long Stiffener
Figure 3: Fabrication Drawing of Board Stiffeners
Requirements
● You must locate the connectors and guide pin holes exactly as shown in Figure 1 on
page 12, so that the Daughterboard will fit onto the Adapter.
● The height of the DUT above the Daughterboard must not exceed 2.25 inches.
November 2001Synopsys, Inc.15
Chapter 2: Building the DaughterboardThe ModelSource 640-pin Adapter
● The DUT signal traces (DUT1 through DUT640) are controlled impedance, and
must be 93 ohms ± 10%. (All other signals are uncontrolled but will function
correctly at 93 ohms.)
● You must make the following specific connections:
❍ J1-A1 to J1-F48 (SEAT1)
❍ J2-A1 to J2-F24 (SEAT2)
❍ J3-A1 to J3-F48 (SEAT3)
❍ J4-A1 to J4-F24 (SEAT4)
❍ J5-A1 to J5-F24 (SEAT5)
❍ J6-A1 to J6-F24 (SEAT6)
(These connections pass a daisychain signal through all four J connectors to allow
the ModelSource system to detect whether or not the Adapter is seated correctly.)
● You must provide a series termination of 4.7 ohms within 1 inch of the DUT’s signal
pins. Use as small a surface mount package as can practically be mounted.
Routing Guidelines
Provide connections for your DUT device(s) on the Daughterboard. Route the DUT
signals (DUT1 through DUT640) and other appropriate signals to the J connector pins
according to the pinout listing in “J1–J6 Connector Pinouts” on page 29.
The following are some guidelines:
● For optimal pattern clock rates, ensure that all DUT signals are the same length, or
nearly so (within 0.5 inch).
● Use either microstrip (preferred) or stripline for the signal layers, but do not mix
them, because their propagation velocities are different. Use microstrip if the signal
routing fits on two layers; use stripline if the signal routing requires more than two
layers.
● For ease of testing, create test points for the following signals:
❍ J1-D17 (KEEPALIVE)
❍ J1-A15 (TRIGGER)
❍ J1-A19 (PLAY)
❍ J1-A17 (SAMPLE)
❍ Any voltages used by the DUT
16Synopsys, Inc.November 2001
The ModelSource 640-pin AdapterChapter 2: Building the Daughterboard
❍ J4-FP5–J4-FP8 (FANP12V), if used
❍ DUT signal used for DUT clock
● You can connect to any of the available power supplies listed in Table 1. Do not
interconnect different power supplies.
Table 1: Available Power Supplies
PinsSignalPower Supply
J2-AP5–J2-AP8
P5V+5V DC, 6A max
J4-AP5–J4-AP8
J2-AP1–J2-AP4ADJVCC1+3-5V DC, 6A max
J4-AP1–J4-AP4ADJVCC2+3-5V DC, 6A max
J4-FP1–J4-FP4M5V-5.2V DC, 400mA max
J2-FP5–J2-FP8P12V+12V DC, 400mA max
J4-FP5–J4-FP8FANP12V+12V DC, 400mA max (for
fan/heat sink only)
● For bypass/decoupling capacitors, follow the DUT manufacturer’s
recommendations, if provided; otherwise, use the following guidelines:
❍ For each supply of P5V, ADJVCC1 or ADJVCC2, provide 47µF, 16V tantalum
(use two of these, if space permits).
❍ For each supply of P12V, M5V, provide 10µF, 16V tantalum.
❍ For bypass, for every 25 signal pins, place a pair of 0.1µF and 0.01µF high
frequency X7R or NPO capacitors directly underneath the device, if possible, or
around the perimeter of the device.
November 2001Synopsys, Inc.17
Chapter 2: Building the DaughterboardThe ModelSource 640-pin Adapter
18Synopsys, Inc.November 2001
The ModelSource 640-pin AdapterChapter 3: Connecting the Daughterboard
3
Connecting the Daughterboard
This section describes the Adapter and gives instructions for interconnecting it and the
Daughterboard.
Adapter Description
Figure 4 shows a drawing of the Adapter. The items of interest to the user are as follows:
● Connectors that mate with Daughterboard connectors J1–J6
● Ejectors for disconnecting the Daughterboard from the Adapter
● Guide pins that fit the Daughterboard guide pin holes to ensure correct orientation
● Test points for the signals TRIGGER, KEEPALIVE, PLAY, FEEDBACK,
SAMPLE, ADJVCC1, +5V, -5V, and GND
November 2001Synopsys, Inc.19
Chapter 3: Connecting the DaughterboardThe ModelSource 640-pin Adapter
2
6
3
Ejector
Guide
Pin
Mates
with J4
Test
Points
Mates
with J5
Mates
with J1
Mates
with J
Mates
with J
Mates
with J
Test
Points
Ejector
Test
Points
Figure 4: The 640-pin Generic Device Adapter
20Synopsys, Inc.November 2001
The ModelSource 640-pin AdapterChapter 3: Connecting the Daughterboard
Procedures
Caution
Do not connect or disconnect the Daughterboard to or from the Adapter
while the Adapter is mounted on the ModelSource modeling systems.
To connect the Daughterboard to the Adapter, follow these steps:
1. Remove the lid from the Adapter.
2. Set the Daughterboard on the Adapter, engaging the guide pins through the guide
pin holes.
3. Push firmly to seat.
4. Hand-tighten each of the Southco retractable screw fasteners.
5. Replace the Adapter lid.
To disconnect the Daughterboard from the Adapter, follow these steps:
1. Remove the lid from the Adapter.
2. Loosen the Southco retractable screw fasteners.
3. Push the ejectors on the Adapter.
4. Carefully lift the Daughterboard from the Adapter.
5. Replace the Adapter lid.
November 2001Synopsys, Inc.21
Chapter 3: Connecting the DaughterboardThe ModelSource 640-pin Adapter
22Synopsys, Inc.November 2001
The ModelSource 640-pin AdapterChapter 4: Developing the Shell Software
4
Developing the Shell Software
The Shell Software file requirements for a 640-pin Logic model are similar to those for
standard Logic Models, and are summarized here. For more information, see the Shell
Software Reference Manual.
User-Generated Files
As for all Generic Device Adapters, you must create one or more Shell Software files
that contain DUT-specific information, such as pinouts, device names, propagation
delays, timing checks.
Files Provided by Synopsys
● The Adapter Mapping (.ADP) file, GEN640.ADP: This file provides signal
mapping between the Adapter and the ModelSource modeling system. You should
be able to use this file without modification.
● A template Package Mapping (.PKG) file, GEN640.PKG: The .PKG file provides
signal mapping between the Daughterboard and the DUT; the template file contains
Daughterboard pin names mapped to duplicate pin names, for those pins used for
DUT signals. You create the custom .PKG file by editing the template and replacing
the duplicate pin names with your DUT pin names.
November 2001Synopsys, Inc.23
Chapter 4: Developing the Shell SoftwareThe ModelSource 640-pin Adapter
Figure 5 shows part of the template GEN640.PKG file provided by Synopsys.
T o customize this file for your DUT, you replace the first name on each line with the
name of the appropriate signal on your DUT.
For example, you change the first line
J1A2 = J1A2
to
DUTpname = J1A2
24Synopsys, Inc.November 2001
The ModelSource 640-pin AdapterChapter 5: Completing the Model
5
Completing the Model
This chapter describes the tasks needed to complete the model: mounting the Adapter
onto the Modeling Systems, labeling the Daughterboard, and verifying the model. It also
describes how to unmount the Adapter from the Modeling Systems.
Mounting the Adapter onto the ModelSource
Modeling Systems
To mount the Adapter onto the ModelSource modeling systems, follow these steps:
1. Make a stack of four MS3200 or four MS3400 modeling systems (do not mix these
two modeling systems). Connect the modeling systems together as described in
“Chapter 2: Installation” in the ModelSource User’s Manual.
Note
Do not stack the modelings systems more than four high. Ensure that the
surface on which the modelers are stacked is flat and rigid.
2. Place the base of the Adapter against the front of the sets of four connected
modeling systems, hanging the Adapter’ s hook receptacles on the positioning hooks
of the modeling systems. Pull the Adapter gently towards you to make sure that it is
securely balanced on the hooks.
3. Seat the modeling boards in the ModelSource modeling systems onto the Adapter as
described in the following paragraph.
Each modeling system has a knob on the right and on the left side for moving the
top and bottom modeling boards, respectively, backwards and forwards. Turn each
knob individually counterclockwise to bring each modeling board forward to
connect with the Adapter.
November 2001Synopsys, Inc.25
Chapter 5: Completing the ModelThe ModelSource 640-pin Adapter
Labeling the Daughterboard
After you have completed the Shell Software and mounted the Adapter and
Daughterboard onto the ModelSource modeling systems, you must verify the
Daughterboard’s label and update it if necessary.
Note
Ensure that the Daughterboard is seated on the Adapter before you verify
and update the label. If the daughterboard is not seated, the software will
report the label as “GEN640”, the label of the Adapter itself.
If it is necessary to update the Daughterboard’s label, use the lm Label Device Adapter
utility to change the adapter’s label to the device_name used in the model’s Shell
Software. For more details, refer to “Label Device Adapter“ in the ModelSource User’s
Manual.
Verifying the Model
After you have developed the model, you must verify it. For more information, see the
ModelSource User’s Manualand the Logic Model Development Manual.
Note
The pattern memory available for simulation is limited to the smallest
amount of available memory on any one of the eight modeling boards in the
four modelers.
26Synopsys, Inc.November 2001
The ModelSource 640-pin AdapterChapter 5: Completing the Model
Unmounting the Adapter from the
ModelSource Modeling Systems
To remove the Adapter from the ModelSource modeling systems, follow these steps:
1. Ensure that the Adapter is not currently in use (that is, the In Use LEDs are not
illuminated).
2. Turn each knob individually clockwise, to unseat each modeling board connector
from the Adapter.
3. Verify that the “Seated LED” on each modeling board is no longer illuminated.
4. Push the Adapter so that it is flush against the front panel of the modeling system
assembly, and slide it up as far as you can.
5. Pull the Adapter straight out and away from the modeling system assembly.
November 2001Synopsys, Inc.27
Chapter 5: Completing the ModelThe ModelSource 640-pin Adapter
28Synopsys, Inc.November 2001
The ModelSource 640-pin AdapterAppendix A: J1–J6 Connector Pinouts
A
J1–J6 Connector Pinouts
The pinouts for connectors J1 through J6 of the 640-pin Adapter and the Daughterboard
are listed in Table 2. Do not use pins that are labeled RESERVED.