SyncMOS SM8954A Technical data
SyncMOS Technologies Inc. SM8954A
October 2003
Product List
SM8954AL25, 25MHz 16KB internal flash MCU
SM8954AC25, 25MHz 16KB internal flash MCU
SM8954AC40, 40MHz 16KB internal flash MCU
Description
The SM8954A series product is an 8 - bit single chip micro
controller with 16KB on-chip flash and 1K byte RAM
embedded. It is a derivative of the 8052 micro controller
family. It has 5-channel SPWM build-in. User can access
on-chip expanded RAM with easier and faster way by its
‘bank mapping direct addressing mode’ scheme. With its
hardware features and powerful instruction set, it’s
straight forward to make it a versatile and cost effective
controller for those applications which demand up to 16 I/
O pins for PDIP package or up to 36
I/O pins for PLCC/QFP package, or applications which
need up to 16K byte flash memory for program data.
To program the on-chip flash memory, a commercial writer
is available to do it in parallel programming method.
Ordering Information
yywwv
SM8954Aihhk
yy: year, ww:week
v: version identifier {, A, B,...}
i: process identifier {L=3.0V ~ 3.6V, C=4.5V ~ 5.5V}
hh: working clock in MHz {25, 40}
k: package type postfix {as below table}
v: version identifier
8 - Bit Micro-controller
with 16KB flash & 1KB RAM embedded
Features
Working voltage: 3.0V ~ 3.6V For L Version
4.5V ~ 5.5V For C Version
General 8052 family compatible
12 clocks per machine cycle
16K byte on chip program flash
1024 byte on-chip data RAM
Three 16 bit Timers/Counters
One Watch Dog Timer
Four 8-bit I/O ports for PDIP package
Four 8-bit I/O ports + one 4-bit I/O ports for PLCC or QFP package
Full duplex serial channel
Bit operation instruction
Industrial Level
8-bit Unsigned Division
8-bit Unsigned Multiply
BCD arithmetic
Direct Addressing
Indirect Addressing
Nested Interrupt
Two priority level interrupt
A serial I/O port
Power save modes: Idle mode and Power down mode
Code protection function
Low EMI (inhibit ALE)
Bank mapping direct addressing mode for access on-chip RAM
5 channel SPWM function with P1.3 ~ P1.7
Postfix Package
P 40L PDIP page 2 page 21
J 44L PLCC page 2 page 22
Q 44L QFP page 2 page 23
Web site: http://www.syncmos.com.tw
Specifications subject to change without notice,contact your sales representatives for the most recent information.
1/25 Ver 1.0 SM8954A 10/03
Pin/Pad
Configuration Dimension
Taiwan
4F, No. 1 Creation Road 1,
Science-based Industrial Park,
Hsinchu, Taiwan 30077
TEL: 886-3-578-3344 #2667
886-3-579-2987
FAX: 886-3-5792960
886-3-5780493
Pin Configurations
SPWM2/P1.5
SPWM3/P1.6
SPWM4/P1.7
RES
RXD/P3.0
P4.3
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
T0/P3.4
T1/P3.5
SyncMOS Technologies Inc. SM8954A
October 2003
#PSEN
P1.2
P1.3/SPWM0
P1.4/SPWM1
6
7
8
9
10
11
12
13
14
15
16
17
19
18
P1.1/T2EX
3
5
4
SM8954A
ihhJ
44L PLCC
(Top View)
22
20
21
VDD
P0.0/AD0
P4.2
P1.0/T2
144434241 40
2
26
25
23
24
P0.1/AD1
P0.2/AD2
P0.6/AD6
#EA
P4.1
P0.5/AD5
P0.4/AD4
P0.3/AD3
39
P0.4/AD4
38
P0.5/AD5
37
P0.6/AD6
36
P0.7/AD7
35
#EA
P4.1
34
33
ALE
32
#PSEN
31
P2.7/A15
30
P2.6/A14
29
P2.5/A13
2827
AD3/P0.3
AD2/P0.2
AD1/P0.1
AD0/P0.0
VDD
P4.2
T2/P1.0
T2EX/P1.1
P1.2
SPWM0/P1.3
SPWM1/P1.4
34
35
36
37
38
39
40
41
42
43
44
P0.6/AD6
33 32 31 30 27 26 25 24 2329 28
SM8954A
ihhQ
44L QFP
(Top View)
1
P2.7/A15
P2.6/A14
ALE
765432
8
P2.5/A13
22
P2.4/A12
21
P2.3/A11
20
P2.2/A10
19
P2.2/A9
18
P2.1/A8
17
P4.0
VSS
16
15
XTAL1
14
XTAL2
13
P3.7/#RD
12
11
109
P3.6/#WR
T2/P1.0
T2EX/P1.1
P1.2
SPWM0/P1.3
SPWM1/P1.4
SPWM2/P1.5
SPWM3/P1.6
SPWM4/P1.7
RES
RXD/P3.0
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
T0/P3.4
T1/P3.5
#WR/P3.6
#RD/P3.7
XTAL2
XTAL1
VSS
VSS
RES
XTAL1
XTAL2
#RD/P3.7
#WR/P3.6
1
2
3
4
5
6
(Top View)
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A9/P2.1
A8/P2.0
P4.0
40L PDIP
A11/P2.3
A10/P2.2
40
39
38
37
36
35
SM8954A ihhP
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A12/P2.4
SPWM2/P1.5
VDD
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
#EA
ALE
#PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
RXD/P3.0
SPWM4/P1.7
SPWM3/P1.6
P4.3
TXD/P3.1
#INT0/P3.2
T1/P3.5
#INT1/P3.3
T0/P3.4
Specifications subject to change without notice,contact your sales representatives for the most recent information.
2/25 Ver 1.0 SM8954A 10/03
SyncMOS Technologies Inc. SM8954A
October 2003
Block Diagram
XTAL2
XTAL1
#EA
ALE
#PSEN
RES
Vdd
Vss
Timer 2
Timer 1
WDT
Reset
Circuit
Power
Circuit
Interrupt
Circuit
Timing
Generator
Instruction
Register
Timer 0
to pertinent blocks
to whole chip
to pertinent blocks
to whole system
Stack
Pointer
Buffer2
PSW
ALU
Decoder &
Register
Acc
Buffer1
1024 bytes
RAM
Buffer
DPTR
PC
Incrementer
Program
Counter
Register
3FFFH
16K
bytes
Port 0
Latch
5
SPWM
Port 0
Driver & Mux
8
Specifications subject to change without notice,contact your sales representatives for the most recent information.
3/25 Ver 1.0 SM8954A 10/03
Port 1
Latch
Port 1
Driver & Mux
8
Port 2
Latch
Port 2
Driver & Mux
8
Port 3
Latch
Port 3
Driver & Mux
8
Port 4
Latch
Port 4
Driver & Mux
4
Flash
Memory
0000H
SyncMOS Technologies Inc. SM8954A
October 2003
Pin Descriptions
40L
44L
44L
PDIP
QFP
PLCC
Pin#
Pin#
Pin#
1 40 2 P1.0/T2 i/o bit 0 of port 1 & timer 2 clock out
2 41 3 P1.1/T2EX i/o bit 1 of port 1 & timer 2 control
3 42 4 P1.2 i/o bit 2 of port 1
4 43 5 P1.3/SPWM0 i/o bit 3 of port 1 & SPWM channel 0
5 44 6 P1.4/SPWM1 i/o bit 4 of port 1 & SPWM channel 1
6 1 7 P1.5/SPWM2 i/o bit 5 of port 1 & SPWM channel 2
7 2 8 P1.6/SPWM3 i/o bit 6 of port 1 & SPWM channel 3
8 3 9 P1.7/SPWM4 i/o bit 7 of port 1 & SPWM channel 4
9 4 10 RES H i Reset
10 5 11 P3.0/RXD i/o bit 0 of port 3 & Receive data
11 7 13 P3.1/TXD i/o bit 1 of port 3 & Transmit data
12 8 14 P3.2/#INT0 L/ - i/o bit 2 of port 3 & low true interrupt 0
13 9 15 P3.3/#INT1 L/ - i/o bit 3 of port 3 & low true interrupt 1
14 10 16 P3.4/T0 i/o bit 4 of port 3 & Timer 0
15 11 17 P3.5/T1 i/o bit 5 of port 3 & Timer 1
16 12 18 P3.6/#WR i/o bit 6 of port 3 & ext. memory write
17 13 19 P3.7/#RD i/o bit 7 of port 3 & ext. mem. read
18 14 20 XTAL2 o Crystal out
19 15 21 XTAL1 i Crystal in
20 16 22 VSS Sink Voltage, Ground
21 18 24 P2.0/A8 i/o bit 0 of port 2 & bit 8 of ext. memory address
22 19 25 P2.1/A9 i/o bit 1 of port 2 & bit 9 of ext. memory address
23 20 26 P2.2/A10 i/o bit 2 of port 2 & bit 10 of ext. memory address
24 21 27 P2.3/A11 i/o bit 3 of port 2 & bit 11 of ext. memory address
25 22 28 P2.4/A12 i/o bit 4 of port 2 & bit 12 of ext. memory address
26 23 29 P2.5/A13 i/o bit 5 of port 2 & bit 13 of ext. memory address
27 24 30 P2.6/A14 i/o bit 6 of port 2 & bit 14 of ext. memory address
28 25 31 P2.7/A15 i/o bit 7 of port 2 & bit 15 of ext. memory address
29 26 32 #PSEN o program storage enable
30 27 33 ALE o address latch enable
31 29 35 #EA L i external access
32 30 36 P0.7/AD7 i/o bit 7 of port 0 & data/address bit 7 of ext. memory
33 31 37 P0.6/AD6 i/o bit 6 of port 0 & data/address bit 6 of ext. memory
34 32 38 P0.5/AD5 i/o bit 5 of port 0 & data/address bit 5 of ext. memory
35 33 39 P0.4/AD4 i/o bit 4 of port 0 & data/address bit 4 of ext. memory
36 34 40 P0.3/AD3 i/o bit 3 of port 0 & data/address bit 3 of ext. memory
37 35 41 P0.2/AD2 i/o bit 2 of port 0 & data/address bit 2 of ext. memory
38 36 42 P0.1/AD1 i/o bit 1 of port 0 & data/address bit 1 of ext. memory
39 37 43 P0.0/AD0 i/o bit 0 of port 0 & data/address bit 0 of ext. memory
40 38 44 VDD Drive Voltage, +5 Vcc
17 23 P4.0 i/o bit 0 of Port 4
28 34 P4.1 i/o bit 1 of Port 4
39 1 P4.2 i/o bit 2 of Port 4
6 12 P4.3 i/o bit 3 of Port 4
Symbol Active I/O Names
Specifications subject to change without notice,contact your sales representatives for the most recent information.
4/25 Ver 1.0 SM8954A 10/03
SyncMOS Technologies Inc. SM8954A
October 2003
Special Function Register (SFR)
The address $80 to $FF can be accessed by direct addressing mode only.
Address $80 to $FF is SFR area.
The following table lists the SFRs which are identical to general 8052, as well as SM8954A Extension SFRs.
Special Function Register (SFR) Memory Map
$F8
$F0
$E8
$E0
$D8
$D0
$C8
B
ACC
P4
PSW
T2CON T2MOD RCAP2L RCAP2H TL2 TH2
$C0
$B8
$B0
$A8
$A0
$98
$90
$88
$80
Note: The text of SFRs with bold type characters are Extension Special Function Registers for
Addr SFR Reset 7 6 5 4 3 2 1 0
85H RCON ******00 RAMS1 RAMS0
86H DBANK 0***0001 BSE BS3 BS2 BS1 BS0
97H WDTKEY 00H WDTKEY7 WDTKEY6 WDTKEY5 WDTKEY4 WDTKEY3 WDTKEY2 WDTKEY1 WDTKEY0
9BH P1CON 00000*** SPWME4 SPWME3 SPWME2 SPWME1 SPWME0
9FH WDTC 0*0**000 WDTE CLEAR PS2 PS1 PS0
A3H SPWMC ******00 SPFS1 SPFS0
A4H SPWMD0 00H SPWMD04 SPWMD03 SPWMD02 SPWMD01 SPWMD00 BRM02 BRM01 BRM00
A5H SPWMD1 00H SPWMD14 SPWMD13 SPWMD12 SPWMD11 SPWMD10 BRM12 BRM11 BRM10
A6H SPWMD2 00H SPWMD24 SPWMD23 SPWMD22 SPWMD21 SPWMD20 BRM22 BRM21 BRM20
A7H SPWMD3 00H SPWMD34 SPWMD33 SPWMD32 SPWMD31 SPWMD30 BRM32 BRM31 BRM30
ACH SPWMD4 00H SPWMD44 SPWMD43 SPWMD42 SPWMD41 SPWMD40 BRM42 BRM41 BRM40
BFH SCONF 0*****00 WDR OME ALEI
C8H T2CON 00H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
C9H T2MOD ******00 T2OE DCEN
D8H P4 ****1111 P4.3 P4.2 P4.1 P4.0
IP SCONF
P3
IE SPWMD4
P2 SPWMC SPWMD0 SPWMD1 SPWMD2 SPWMD3
SCON SBUF P1CON WDTC
P1 WDTKEY
TCON TMOD TL0 TL1 TH0 TH1
P0 SP DPL DPH (Reserved) RCON DBANK PCON
SM8954A
$FF
$F7
$EF
$E7
$DF
$D7
$CF
$C7
$BF
$B7
$AF
$A7
$9F
$97
$8F
$87
Specifications subject to change without notice,contact your sales representatives for the most recent information.
5/25 Ver 1.0 SM8954A 10/03
SyncMOS Technologies Inc. SM8954A
October 2003
Extension Function Description
1. Memory Structure
The SM8954A is the general 8052 hardware core as a single chip micro controller. Its memory structure follows general 8052
structure.
1.1 Program Memory
The SM8954A has 16K byte on-chip flash memory which used as general program memory. The address range for the 16K
byte is $0000 to $3FFF.
3FFF
16K Program
memory space
0000
Note: The single flash block address structure for doing as well as program ROM flash.
1.2 Data Memory
The SM8954A has 1K bytes on-chip RAM, 256 bytes of it are the same as general 8052 internal memory structure while the
expanded 768 bytes on-chip RAM can be accessed by external memory addressing method (by instruction MOVX), or by
‘Bank mapping direct addressing mode’ as described in next page.
02FF
Expanded 768 bytes RAM
(Accessed by direct external
addressing mode, by instruction
FF
Higher 128 bytes (Access by
indirect addressing mode only)
80
7F
Lower 128 bytes (Accessed by
direct & indirect
00
addressing mode)
SFR (Accessed by direct
addressing mode only)
MOVX, or by Bank mapping
direct addressing mode)
FF
( OME = 1 )
80
0000
On-chip expanded RAM address structure.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
6/25 Ver 1.0 SM8954A 10/03
SyncMOS Technologies Inc. SM8954A
October 2003
1.2.1 Data Memory - Lower 128 byte ($00 to $7F, Bank 0 & Bank 1)
Data Memory $00 to $FF is the same as 8052.
The address $00 to $7F can be accessed by direct and indirect addressing modes.
Address $00 to $1F is register area.
Address $20 to $2F is memory bit area.
Address $30 to $7F is for general memory area.
1.2.2 Data Memory - Higher 128 byte ($80 to $FF, Bank 2 & Bank 3)
The address $80 to $FF can be accessed by indirect addressing mode or by bank mapping direct addressing mode.
Address $80 to $FF is data area.
1.2.3 Data Memory - Expanded 768bytes ($0000 to $02FF, Bank 4 ~ Bank 15)
From external address $0000 to $02FF is the on-chip expanded RAM area, total 768 bytes. This area can be accessed by
external direct addressing mode (by instruction MOVX) or by bank mapping direct addressing mode as described below:
1.3 Bank mapping direct addressing mode:
We provide RAM bank address ‘40H~7FH’ as mapping window which allow user access all the 1KB on-chip RAM through
this RAM bank address.
That means using direct addressing mode can access all the 1KB on-chip RAM. Please see next page for the mapping
mode table.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
7/25 Ver 1.0 SM8954A 10/03
SyncMOS Technologies Inc. SM8954A
October 2003
BS3 BS2 BS1 BS0 040h~07fh map-
ping address
0 0 0 0 000h~03fh lower 128 byte RAM
0 0 0 1 040h~07fh lower 128 byte RAM
0 0 1 0 080h~0bfh higher 128 byte RAM
0 0 1 1 0c0h~0ffh higher 128 byte RAM
0 1 0 0 0000h~003fh on-chip expanded 768 byte RAM
0 1 0 1 0040h~007fh “
0 1 1 0 0080h~00bfh “
0 1 1 1 00c0h~00ffh “
1 0 0 0 0100h~013fh “
1 0 0 1 0140h~017fh “
1 0 1 0 0180h~01bfh “
1 0 1 1 01c0h~01ffh “
1 1 0 0 0200h~023fh “
1 1 0 1 0240h~027fh “
1 1 1 0 0280h~02bfh “
1 1 1 1 02c0h~02ffh “
Note
With this bank mapping scheme, user can access entire 1K byte on-chip RAM with direct addressing method. That means
using the window area ($040~$07F), user can access any bank (64 byte) data of 1K byte on-chip RAM space which is
selected by BS[3:0] of data bank control register (DBANK, $86).
For example, user write #30h to $101 address:
MOV DBANK, #88H ; set bank mapping $040~$07f to $0100~$013f
MOV A, # 30H ; store #30H to A
MOV 41H, A ; write #30H to $0101 address
Specifications subject to change without notice,contact your sales representatives for the most recent information.
8/25 Ver 1.0 SM8954A 10/03
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