Supertex HV9120 Datasheet

Supertex inc.

www.supertex.com

High-Voltage,

OSC

OSC

Current-Mode PWM Controller

HV9120

Features

► 10 to 450V input voltage range
► <1.3mA supply current
► >1.0MHz clock
► >20:1 dynamic range @ 500KHz
► 49% Maximum duty cycle version
► Low internal noise

Applications

► Off-line high frequency power supplies
► Universal input power supplies
► High density power supplies
► Very high efciency power supplies
► Extra wide load range power supplies

General Description

The Supertex HV9120 is a Switch Mode Power Supply
(SMPS) controller subsystem that can start and run directly

from almost any DC input, from a 12V battery to a rectied
and ltered 240V AC line. It contains all the elements

required to build a single-switch converter except for the

switch, magnetic assembly, output rectier(s) and lter(s).

A unique input circuit allows the HV9120 to self-start
directly from a high voltage input, and subsequently
take the power to operate from one of the outputs of the

converter it is controlling, allowing very efcient operation

while maintaining input-to-output galvanic isolation
limited in voltage only by the insulation system of the
associated magnetic assembly. A ±2% internal bandgap

reference, internal operational amplier, very high speed

comparator, and output buffer allow production of rugged,

high performance, high efciency power supplies of 50W
or more, which can still be over 80% efcient at outputs
of 1.0W or less. The wide dynamic range of the controller

system allows designs with extremely wide line and load

variations with much less difculty and much higher
efciency than usual. The exceptionally wide input voltage

range also allows better usage of energy stored in input

dropout capacitors than with other PWM ICs. Remote on/

off controls allow either latching or nonlatching remote
shutdown. During shutdown, the power required is under

6.0mW.

For detailed circuit and application information, please
refer to application notes AN-H13, AN-H21 to AN-H24.

Functional Block Diagram

Error

–

+

4V

–

+

COMP FB

14 (18)

To
Internal
Circuits

8.6V

15 (19)

Amplifier

11 (14)

VREF

REF
GEN

16 (20)

BIAS

7 (9)

VDD

1 (3)

+VIN

Note:

Pin numbers in parentheses are for PLCC package.

Current

Sources

Pre-regulator/Startup

8.1V

2V

1.2V

IN

9 (11)

–

+

+

–

–

+

Modulator

Comparator

Current Limit

Comparator

Undervoltage

Comparator

OSC

OUT

8 (10)

R

Q

S

Q

T Q

S

R

To VDD

5 (6)

OUTPUT

6 (8)

-VIN

4 (5)

V

DD

SENSE

12 (16)

SHUTDOWN

13 (17)

RESET

Doc.# DSFP-HV9120
C031314

Supertex inc.

HV9120

www.supertex.com

Top Marking

Top Marking

Top Marking

Ordering Information

Part Number Package Options Packing

HV9120NG-G 16-Lead SOIC 45/Tube

HV9120NG-G M901 16-Lead SOIC 1000/Reel

HV9120NG-G M934 16-Lead SOIC 2500/Reel

HV9120P-G 16-Lead PDIP 24/Tube

HV9120PJ-G 20-Lead PLCC* 48/Tube

HV9120PJ-G M910 20-Lead PLCC* 1000/Reel

-G denotes a lead (Pb)-free / RoHS compliant package
* Obsolescence notice issued for the product in the 20-Lead PLCC package.

Absolute Maximum Ratings

Parameter Value

Input voltage, +V

IN

Device supply voltage, V

DD

450V

15.5V

Logic input voltage -0.3V to VDD +0.3V

Linear input voltage -0.3V to VDD +0.3V

Pre regulator input current

(continuous), I

IN

2.5mA

Operating temperature range -55°C to +125°C

Storage temperature range -65°C to +150°C

Power dissipation:

16-Lead SOIC
16-Lead PDIP

20-Lead PLCC

Stresses beyond those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in

the operational sections of the specications is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability. Voltages
are referenced to -VIN.

900mW
1000mW
1400mW

Typical Thermal Resistance

Pin Congurations

1

4

16

16-Lead SOIC

20-Lead PLCC

1

16-Lead PDIP

2

20

1

16

Product Marking

HV9120NG

YWW LLLLLLLL

Bottom Marking

CCCCCCCCC AAA

Package may or may not include the following marks: Si or

YYWW

HV9120P

LLLLLLLLLL

Bottom Marking

CCCCCCCCCCC

AAA

Package may or may not include the following marks: Si or

Y = Last Digit of Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging

*May be part of top marking

16-Lead SOIC

Y = Last Digit of Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging

*May be part of top marking

16-Lead PDIP

Package θ

ja

16-Lead SOIC 83°C/W

16-Lead PDIP 51°C/W

20-Lead PLCC 66°C/W

Doc.# DSFP-HV9120
C031314

YYWW AAA

HV9120PJ

LLLLLLLLLL

Bottom Marking

CCCCCCCCCCC

Package may or may not include the following marks: Si or

YY = Year Sealed
WW = Week Sealed
L = Lot Number
A = Assembler ID
C = Country of Origin*
= “Green” Packaging

*May be part of top marking

20-Lead PLCC

Supertex inc.

2

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Electrical Characteristics

(Unless otherwise specied, V

Sym Parameter # Min Typ Max Units Conditions

Reference

V

REF

Output voltage -

= 10V, +V

DD

= 48V, R

IN

= 390kΩ, R

BIAS

= 330kΩ, TA = 25°C.)

OSC

3.92 4.00 4.08

RL = 10MΩ

V

3.84 4.00 4.16 RL = 10MΩ, TA = -55°C to 125°C

HV9120

Z

I

SHORT

ΔV

OUT

Output impedance # 15 30 45 kΩ ---

Short circuit current - - 125 250 μA V

Change in V

REF

Oscillator

f

f

ΔV

TC

MAX

OSC

Oscillator frequency - 1.0 3.0 - MHz R

Initial accuracy

Voltage stability - - - 15 % 9.5V < VDD < 13.5V

OSC

Temperature coefcient # - 170 - ppm/°C TA = -55°C to 125°C

OSC

PWM

D

MAX

D

MIN

Maximum duty cycle # 49.0 49.4 49.6 % ---

Minimum duty cycle - - - 0 % ---

Maximum pulse width before
pulse drops out

Current Limit

V

LIM

t

D

Maximum input signal - 1.0 1.2 1.4 V V

Delay to output # - 80 120 ns V

= -V

REF

with temperature # - 0.25 - mV/°C TA = -55°C to 125°C

REF

OSC

1

- 80 100 120
kHz

- 160 200 240 R

R

OSC

OSC

IN

= 0Ω

= 330kΩ

= 150kΩ

# - 80 125 ns ---

= 0V

FB

= 1.5V, V

SENSE

COMP

≤ 2.0V

Error Amplier

V

FB

I

IN

V

OS

A

VOL

GB Unity gain bandwidth # 1.0 1.3 - MHz ---

Z

OUT

I

SOURCE

I

SINK

PSRR Power supply rejection # see Fig. 2 dB ---

Notes:

# Guaranteed by design.

1. Stray capacitance on OSC In pin must be ≤5pF.

Doc.# DSFP-HV9120
C031314

Feedback voltage - 3.92 4.00 4.08 V VFB shorted to COMP

Input bias current - - 25 500 nA VFB = 4.0V

Input offset voltage - nulled during trim - ---

Open loop voltage gain # 60 80 - dB ---

Out impedance # see Fig. 1 Ω ---

Output source current - -1.4 -2.0 - mA VFB = 3.4V

Output sink current - 0.12 0.15 - mA VFB = 4.5V

3

Supertex inc.

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Electrical Characteristics (cont.)

(Unless otherwise specied, V

Sym Parameter # Min Typ Max Units Conditions

Pre-Regulator/Startup

+V

V

+I

V

LOCK

TH

Input voltage - 10 - 450 V IIN < 10µA; VCC > 9.4V

IN

Input leakage current - - - 10 μA VDD > 9.4V

IN

VDD pre-regulator turn-off
threshold voltage

Undervoltage lockout - 7.0 8.1 8.9 V ---

Supply

I

I

BIAS

V

DD

I

Q

DD

Supply current - - 0.75 1.3 mA CL < 75pF

Quiescent supply current - - 0.55 - mA SHUTDOWN = -V

Nominal bias current - - 20 - μA ---

Operating range - 9.0 - 13.5 V ---

Shutdown Logic

t

SD

t

SW

t

RW

t

LW

V

V

I

IH

I

IL

SHUTDOWN delay # - 50 100 ns CL = 500pF, V

SHUTDOWN pulse width # 50 - - ns

RESET pulse width # 50 - - ns ---

Latching pulse width # 25 - - ns SHUTDOWN and RESET low

Input low voltage - - - 2.0 V ---

IL

Input high voltage - 7.0 - - V ---

IH

Input current, input high voltage - - 1.0 5.0 μA VIN = V

Input current, input low voltage - - -25 -35 μA VIN = 0V

= 10V, +V

DD

= 48V, R

IN

= 390kΩ, R

BIAS

= 330kΩ, TA = 25°C.)

OSC

- 8.0 8.7 9.4 V I

PREREG

= 10µA

DD

SENSE

IN

= -V

HV9120

IN

Output

V

OH

V

OL

R

OUT

t

R

t

F

Note:

# Guaranteed by design.

Output high voltage

Output low voltage

Output resistance

Rise time # - 30 75 ns CL = 500pF

Fall time # - 20 75 ns CL = 500pF

- VDD -0.25 - - V I

- VDD -0.3 - - V

- - - 0.2 V I

- - - 0.3 V

Pull up - - 15 25 Ω

Pull down - - 8.0 20 Ω

Pull up - - 20 30 Ω

Pull down - - 10 30 Ω

= 10mA

OUT

I

= 10mA,

OUT

TA = -55°C to 125°C

= -10mA

OUT

I

= -10mA,

OUT

TA = -55°C to 125°C

I

= ±10mA

OUT

I

= ±10mA,

OUT

TA = -55°C to 125°C

Doc.# DSFP-HV9120
C031314

4

Supertex inc.

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Test Circuits

+10V
(V

DD

(FB)

GND
(-V

Note:

Set feedback voltage so that V

)

Reference

)

IN

0.1µF

COMP

Error Amp Z

1.0V swept 100Hz - 2.2MHz

–

+

= V

± 1.0mV before connecting transformer.

DIVIDE

V

1

OUT

Tektronix

P6021
(1 turn

secondary)

V

60.4k

40.2k

2

Detailed Description

Pre regulator

The pre regulator/startup circuit for the HV9120 consists of

a high-voltage n-channel depletion-mode DMOS transistor

driven by an error amplier to form a variable current path
between the VIN terminal and the VDD terminal. Maximum

current (about 20 mA) occurs when V
ducing as VDD rises. This path shuts off altogether when VDD
rises to somewhere between 7.8 and 9.4V, so that if VDD is
held at 10 or 12V by an external source (generally the sup­ply the chip is controlling), no current other than leakage is
drawn through the high voltage transistor. This minimizes
dissipation.

An external capacitor between VDD and VSS is generally
required to store energy used by the chip in the time be­tween shutoff of the high voltage path and the VDD supply’s
output rising enough to take over powering the chip. This
capacitor should have a value of 100X or more the effective

gate capacitance of the MOSFET being driven, i.e.,

C

≥ 100 x (gate charge of FET at 10V)

STORAGE

as well as very good high frequency characteristics. Stacked
polyester or ceramic caps work well. Electrolytic capacitors
are generally not suitable. A common resistor divider string
is used to monitor VDD for both the undervoltage lockout cir-

cuit and the shutoff circuit of the high voltage FET. Setting

the undervoltage sense point about 0.6V lower on the string

than the FET shutoff point guarantees that the undervoltage
lockout always releases before the FET shuts off.

Bias Circuit

An external bias resistor, connected between the bias pin
and VSS is required by the HV9120 to set currents in a se­ries of current mirrors used by the analog sections of the

chip. Nominal external bias current requirement is 15 to
20µA, which can be set by a 390 to 510kΩ resistor if a 10V

= 0, with current re-

DD

HV9120

0.1V swept 10Hz - 1.0MHz

10.0V

V

is used, or a 510 to 680kΩ resistor if VDD will be 12V. A

DD

100k 1%

4.0V

Reference

precision resistor is not required; ±5% is ne.

Clock Oscillator
The clock oscillator of the HV9120 consists of a ring of
CMOS inverters, timing capacitors, a capacitor discharge

FET, and a frequency dividing ip-op. A single external re­sistor between the OSC IN and OSC OUT pins is required

to set oscillator frequency (see graph).

One difference exists between the Supertex HV9120 and
competitive 9120s: The oscillator is shut off when a shutoff
command is received. This saves about 150µA of quiescent
current, which aids in the construction of power supplies

to meet CCITT specication I-430, and in other situations

where an absolute minimum of quiescent power dissipation
is required.

Reference

The Reference of the HV9120 consists of a stable bandgap
reference followed by a buffer amplier which scales the

voltage up to approximately 4.0V. The scaling resistors of

the reference buffer amplier are trimmed during manufac­ture so that the output of the error amplier, when connected
in a gain of -1 conguration, is as close to 4.0V as possible.
This nulls out any input offset of the error amplier. As a con-

sequence, even though the observed reference voltage of a

specic part may not be exactly 4.0V, the feedback voltage

required for proper regulation will be.

A ≈ 50kΩ resistor is placed internally between the output
of the reference buffer amplier and the circuitry it feeds

(reference output pin and non-inverting input to the error

amplier). This allows overriding the internal reference with
a low-impedance voltage source ≤6.0V. Using an external

reference reinstates the input offset voltage of the error am-

plier, and its effect of the exact value of feedback voltage

0.1µF

PSRR

–

+

100k 1%

V

1

V

2

Doc.# DSFP-HV9120
C031314

5

Supertex inc.

HV9120

www.supertex.com

required. In general, because the reference voltage of the

Supertex HV9120 is not noisy, as some previous examples
have been, overriding the reference should seldom be nec­essary.

Because the reference of the HV9120 is a high impedance
node, and usually there will be signicant electrical noise

near it, a bypass capacitor between the reference pin and
VSS is strongly recommended. The reference buffer ampli-

er is intentionally compensated to be stable with a capaci­tive load of 0.01 to 0.1µF.

Error Amplier

The error amplier in the HV9120 is a true low-power dif­ferential input operational amplier intended for around-the­amplier compensation. It is of mixed CMOS-bipolar con-

struction: A PMOS input stage is used so the common-mode
range includes ground and the input impedance is very high.
This is followed by bipolar gain stages which provide high

gain without the electrical noise of all-MOS ampliers. The
amplier is unity-gain stable.

Current Sense Comparators

The HV9120 uses a true dual-comparator system with in­dependent comparators for modulation and current limiting.
This allows the designer greater latitude in compensation
design, as there are no clamps (except ESD protection) on

the compensation pin. Like the error amplier, the compara­tors are of low-noise BiCMOS construction.

Remote Shutdown

The SHUTDOWN and RESET pins of the HV9120 can be

used to perform either latching or non-latching shutdown of
a converter as required. These pins have internal current
source pull-ups so they can be driven from open-drain logic.

When not used, they should be left open or connected to

VDD.

Output Buffer

The output buffer of the HV9120 is of standard CMOS con-

struction (P-channel pull-up, N-channel pull-down). Thus the

body-drain diodes of the output stage can be used for spike
clipping if necessary, and external Schottky diode clamping
of the output is not required.

Truth Table

SHUTDOWN RESET Output

H H Normal operation

H H → L Normal operation, no change

L H Off, not latched

L L Off, latched

L → H L Off, latched, no change

Shutdown Timing Waveforms

1.5V

SENSE

VDD

OUTPUT

VDD

SHUTDOWN

50%

0

t

D

0

0

50%

≤ 10ns

t

R

VDD

SHUTDOWN

0

VDD

OUTPUT

0

t

SW

50%

50%

t

SD

90% 90%

t

, tF ≤ 10ns

R

≤ 10ns

t

F

VDD

RESET

0

Doc.# DSFP-HV9120
C031314

50%

t

LW

50%

t

RW

50%

Supertex inc.

6

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Typical Performance Curves

Error Amplifier Output Impedance (Z0)

6

10

5

10

4

10

3

10

(Ω)

0

2

Z

10

10

1.0

(Hz)

OUT

f

1M

100k

HV9120

Output Switching Frequency

vs. Oscillator Resistance

0.1
100 1K 10K 100K 1M 10M

Frequency (Hz)

PSRR - Error Amplifier and Reference

0

-10

-20

-30

-40

PSRR (dB)

-50

-60

-70

-80
10 100 1K 10K 100K 1M

Frequency (Hz)

100

10k

10k 100k 1M

R

(Ω)

OSC

Error Amplifier Open Loop Gain/Phase

80

70

60

50

40

Gain (dB)

20

10

0

-10
100 1K 10K 100K 1M

Frequency (Hz)

180

120

60

0

-60

-120

-180

10

Bias Current (µA)

1.0
105 106 10

Doc.# DSFP-HV9120
C031314

V

= 10V

DD

Bias Resistance (Ω)

V

DD

= 10V

7

Supertex inc.

7

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Pin Description 16-Lead SOIC

Pin # Description

1 +VIN

HV9120

Pin # Description

9 OSC IN

2 -

3 -

4 SENSE

5 OUTPUT

6 -VIN

7 VDD

8 OSC OUT

Pin Description 16-Lead PDIP

Pin # Description

1 +VIN

2 NC

3 NC

4 SENSE

5 OUTPUT

6 -VIN

7 VDD

10 NC

11 VREF

12 SHUTDOWN

13 RESET

14 COMP

15 FB

16 BIAS

Pin # Description

9 OSC IN

10 NC

11 VREF

12 SHUTDOWN

13 RESET

14 COMP

15 FB

8 OSC OUT

Pin Description 20-Lead PLCC

Pin # Description

1 NC

2 NC

3 +VIN

4 NC

5 SENSE

6 OUTPUT

7 NC

8 -VIN

9 VDD

10 OSC OUT

16 BIAS

Pin # Description

11 OSC IN

12 NC

13 NC

14 VREF

15 NC

16 SHUTDOWN

17 RESET

18 COMP

19 FB

20 BIAS

Doc.# DSFP-HV9120
C031314

8

Supertex inc.

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16-Lead SOIC (Narrow Body) Package Outline (NG)

9.90x3.90mm body, 1.75mm height (max), 1.27mm pitch

HV9120

D

16

Note 1
(Index Area
D/2 x E1/2)

e

1

b

E1

E

Top View

A

A2

A

A1

Seating

Plane

θ1

Gauge

Plane

L2

L1

L

θ

Seating

Plane

View B

View B

h

h

Side View

Note:

1. This chamfer feature is optional. If it is not present, then a Pin 1 identier must be located in the index area indicated. The Pin 1 identier can be:
a molded mark/identier; an embedded metal marker; or a printed indicator.

A

View A-A

Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1

O

0

Dimension

(mm)

MIN 1.35* 0.10 1.25 0.31 9.80* 5.80* 3.80*

NOM - - - - 9.90 6.00 3.90 - - - -

1.27

BSC

0.25 0.40

1.04

REF

0.25

BSC

MAX 1.75 0.25 1.65* 0.51 10.00* 6.20* 4.00* 0.50 1.27 8O15

JEDEC Registration MS-012, Variation AC, Issue E, Sept. 2005.
* This dimension is not specied in the JEDEC drawing.

Drawings are not to scale.
Supertex Doc. #: DSPD-16SONG, Version G041309.

O

5

O

Doc.# DSFP-HV9120
C031314

9

Supertex inc.

www.supertex.com

16-Lead PDIP (.300in Row Spacing) Package Outline (P)

.790x.250in body, .210in height (max), .100in pitch

HV9120

16

Note 1
(Index Area)

1

D1

A2

A

A1

e

D

Top View

Side View

D1

View B

E1

E

A

Seating

Plane

A

b1

L

b

View B

eA
eB

View A - A

Note:

1. A Pin 1 identier must be located in the index area indicated. The Pin 1 identier can be: a molded mark/identier; an embedded metal marker; or

a printed indicator.

Symbol A A1 A2 b b1 D D1 E E1 e eA eB L

MIN .130* .015 .115 .014 .045 .745†.005 .290†.240

Dimension

(inches)

JEDEC Registration MS-001, Variation AB, Issue D, June, 1993.
* This dimension is not specied in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.

Drawings not to scale.
Supertex Doc. #: DSPD-16DIPP, Version C021312.

Doc.# DSFP-HV9120
C031314

NOM - - .130 .018 .060 .790 - .310 .250 - .130

MAX .210 .035* .195 .023†.070 .810†.050* .325 .280 .430 .150

10

.100

BSC

.300

BSC

.300* .115

Supertex inc.

©2014

Supertex inc.

94089

el: 408-222-8888

www.supertex.com

20-Lead PLCC Package Outline (PJ)

.353x.353in body, .180in height (max), .050in pitch

D

.048/.042

x 45

O

3

D1

1

20

.056/.042

x 45

HV9120

O

.150max

.020max
(3 Places)

A

A1

A2

Note 1
(Index Area)

.075max

8

Note 2

e

13

Top View

18

E

E1

View

B

Base

Plane

Seating

Plane

.020min

Vertical Side View

b1

b

R

Horizontal Side View

Notes:

1. A Pin 1 identier must be located in the index area indicated. The Pin 1 identier can be: a molded mark/identier; an embedded metal marker; or

a printed indicator.

2. Actual shape of this feature may vary.

View B

Symbol A A1 A2 b b1 D D1 E E1 e R

Dimension

(inches)

MIN .165 .090 .062 .013 .026 .385 .350 .385 .350

NOM .172 .105 - - - .390 .353 .390 .353 .035

.050

BSC

.025

MAX .180 .120 .083 .021 .032 .395 .356 .395 .356 .045

JEDEC Registration MS-018, Variation AA, Issue A, June, 1993.

Drawings not to scale.
Supertex Doc. #: DSPD-20PLCCPJ, Version C031111

(The package drawing(s) in this data sheet may not reect the most current specications. For the latest package outline

information go to http://www.supertex.com/packaging.html.)

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives

an adequate “product liability indemnification insurance agreement.”
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the

Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.

Doc.# DSFP-HV9120
C031314

Supertex inc. does not assume responsibility for use of devices described, and limits its liability

Supertex inc. (website: http//www.supertex.com)

1235 Bordeaux Drive, Sunnyvale, CA

11

T