The information in this User’s Manual has been carefully reviewed and is believed to be accurate.
The vendor assumes no responsibility for any inaccuracies that may be contained in this document,
makes no commitment to update or to keep current the information in this manual, or to notify any
person or organization of the updates. Please Note: For the most up-to-date version of this
manual, please see our web site at www.supermicro.com.
SUPER MICRO COMPUTER reserves the right to make changes to the product described in this
manual at any time and without notice. This product, including software, if any, and documentation may not, in whole or in part, be copied, photocopied, reproduced, translated or reduced to any
medium or machine without prior written consent.
IN NO EVENT WILL SUPER MICRO COMPUTER BE LIABLE FOR DIRECT, INDIRECT, SPECIAL,
INCIDENTAL, SPECULATIVE OR CONSEQUENTIAL DAMAGES ARISING FROM THE USE
OR INABILITY TO USE THIS PRODUCT OR DOCUMENTATION, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. IN PARTICULAR, SUPER MICRO COMPUTER SHALL NOT
HAVE LIABILITY FOR ANY HARDWARE, SOFTWARE, OR DATA STORED OR USED WITH THE
PRODUCT, INCLUDING THE COSTS OF REPAIRING, REPLACING, INTEGRATING, INSTALLING
OR RECOVERING SUCH HARDWARE, SOFTWARE, OR DATA.
Any disputes arising between manufacturer and customer shall be governed by the laws of Santa
Clara County in the State of California, USA. The State of California, County of Santa Clara shall
be the exclusive venue for the resolution of any such disputes. Super Micro's total liability for
all claims will not exceed the price paid for the hardware product.
FCC Statement: This equipment has been tested and found to comply with the limits for a Class
A digital device pursuant to Part 15 of the FCC Rules. These limits are designed to provide
reasonable protection against harmful interference when the equipment is operated in a commercial
environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the manufacturer’s instruction manual, may cause harmful
interference with radio communications. Operation of this equipment in a residential area is likely
to cause harmful interference, in which case you will be required to correct the interference at your
own expense.
California Best Management Practices Regulations for Perchlorate Materials: This Perchlorate
warning applies only to products containing CR (Manganese Dioxide) Lithium coin cells. “Perchlorate
Material-special handling may apply. See www.dtsc.ca.gov/hazardouswaste/perchlorate”
WARNING: Handling of lead solder materials used in this
product may expose you to lead, a chemical known to
the State of California to cause birth defects and other
reproductive harm.
Manual Revision 1.0c
Release Date: June 7, 2007
Unless you request and receive written permission from SUPER MICRO COMPUTER, you may not
copy any part of this document.
Information in this document is subject to change without notice. Other products and companies
referred to herein are trademarks or registered trademarks of their respective companies or mark
holders.
(*Note:The drawings and pictures shown in this manual were based on
the latest PCB Revision available at the time of publishing of the manual. The
motherboard you’ve received may or may not look exactly the same as the
graphics shown in the manual.)
1-3
X7DBR-3/X7DBR-E User's Manual
Figure 1-2. X7DBR-3/E Motherboard Layout (not drawn to scale)
KB
JKB
MS
JMS
USB0/1
JUSB1
COM1
JCOM1
GLAN1
GLAN2
VGA
JVGA1
SAS 4-7
Pres#4-7
Act#4-7
JLAN1
JLAN2
JSM2
COM2
JCOM2
Pres#4
UPER X7DBR-3/E
S
J9B2
Bank4
J9B1
J8B3
Bank3
J8B2
J8B1
Bank2
J7B3
J7B2
Bank1
J7B1
PXH-V
Slot7
PCI-X 100MHz ZCRSXB-
Slot6
PCI-X 133MHz
GLAN
CTRLR
JPL1
JPL2
VGA
CTRLR
O
SIMS
Pres#5
®
DIMM 4B
DIMM 4A
DIMM 3B
DIMM 3A
DIMM 2B
DIMM 2A
DIMM 1B
DIMM 1A
C2
C1
2
2
JI
JI
JPG1
JP10
JIPMI
JP11
Pres#6Pres#7
SMB
IPMB
J18
JPS1
J10
SAS
CTRLR
Battery
3rd PWR
Fail
North Bridge
J13
SXB-
JWOR
PWLED SPK
WOR
J3P
S I/O
PWR
SMB
E2x8
LE1
JD1
E1x8
J42
JAR
J8
J4E3
J17
J41
SXB-
South
Bridge
JPWF
E3x8
J43
USB4/5
JUSB3
Pres#0
CPU1
CPU2
WOL
JWOL
USB2/3
JUSB2
Pres#1
4-pin
PWR
JPW2
BIOS
JBT1
Buzzer
SATA1
SATA3
JS2
SATA2
SATA0
JS1
Pres#2Pres#3
8-pin PWR
JPW3
20-pin ATX Main PWR
JWF1
Pre#0-3
Act#0-3
SATA5
JS4
SATA4
JS3
JWD
JCF1
JP12
SAS 1-3
JS6
JS5
Compact Flash
JIDE2
SGPIO2
J30
JOH1
JSM1
JS10
JPW1
IDE1
JIDE1
SGPIO1
Fan1
Fan2
Fan3
Fan4
Fan5
J22
J29
J7
JL1
JF1
FP Ctrl
Floppy
Act#4
Act#5
Act#6
Act#7
SAS LEDs (Act#4-#7, Pres.#4-#7) (*Note
Act=Active, Pre.=Present)
Act# Defi nition Act# Defi nition
Act#4SAS4:ActPre#4SAS0:Pre.4
Act#5SAS5:ActPre#5SAS1:Pre.5
Act#6SAS6:ActPre#6SAS2:Pre.6
Act#7SAS7:ActPre#7SAS2:Pre.7
Act#0
Act#1
Act#2
SAS LEDs (Act#0-#3, Pres.#0-#3) (*Note
Act=Active, Pre.=Present)
Act# Defi nition Act# Defi nition
Act#0SAS0:ActPre#0SAS0:Pre.0
Act#1SAS1:ActPre#1SAS1:Pre.1
Act#2SAS2:ActPre#2SAS2:Pre.2
Act#3SAS3:ActPre#3SAS2:Pre.3
Act#3
Note 1. Jumpers not indicated are for test purposes only.
Note 2. See Chapter 2 for detailed information on jumpers, I/O ports and
JF1 front panel connections.
Note 3. " " indicates the location of Pin 1.
Note 4. SAS is for the X7DBR-3 only.
Note 5. For Compact Card to work properly, please enable JCF1 by putting
jumper on it and connect JWF1 to the power input of the Compact Flash Jumper.
Note 6. When LE1 is on, make sure to remove the power cable before removing
or installing components.
1-4
Chapter 1: Introduction
Quick Reference ( X7DBR-3/X7DBR-E)
Jumper Description Default Setting
J3P 3rd PWR Failure Detect
JBT1 CMOS Clear See Chapter 2
JCF1 Compact Card Master/Slave Select On (Master)
2
JI
C1/JI2C2 SMB Bus to PCI-E Slots Off (Disabled)
JPG1 VGA Enable Pins 1-2 (Enabled)
JPL1/ JPL2 GLAN1/GLAN2 Enable Pins 1-2 (Enabled)
JPS1 (*Note1) SAS Enable Pins 1-2 (Enabled)(*Note)
• One 64-bit PCI-X ZCR slot (*One PCI-X-100 MHz Zero Channel RAID slot:
Slot 7) (*riser card required)
BIOS
• 8 Mb Phoenix
®
Flash ROM
• DMI 2.3, PCI 2.2, ACPI 1.0/2.0, Plug and Play (PnP), SMBIOS 2.3 and USB
Keyboard support
PC Health Monitoring
• Onboard voltage monitors for CPU cores, chipset voltage, +1.8V, +3.3V, +5V,
+12V, −12V, +3.3V Standby, +5V standby and VBAT
• Fan status monitor with fi rmware control
• CPU/chassis temperature monitors
• Low noise fan speed control
• Platform Environment Control Interface (PECI) ready
2
• I
C temperature sensing logic
• Thermal Monitor 2 (TM2) support
• CPU slow-down on temperature overheat
• CPU thermal trip support for processor protection
• Power-up mode control for recovery from AC power loss
• Auto-switching voltage regulator for CPU cores
• System overheat/Fan Fail LED Indicator and control
• Chassis intrusion detection
• System resource alert via Supero Doctor III
1-6
Chapter 1: Introduction
ACPI Features
• Slow blinking LED for suspend state indicator
• Main switch override mechanism
• ACPI Power Management
• Power-on mode for power recovery
Onboard I/O
• Six SATA ports (supporting Intel RAID 0, 1, 5 and 10) (*Adaptec supports
RAID 0, 1 and 10 for the X7DBR-E only)
• Eight SAS Connectors (*X7DBR-3 only)
• One SIMSO IPMI socket (AOC-SIMSO)
• Two Giga-bit LAN ports with IOAT Technology
• One EIDE Ultra DMA/100 bus master interface
• One IDE w/Compact Flash Card supported
• One fl oppy port interface
• Two COM ports(1 header, 1 port)
• Up to fi ve USB 2.0 (Universal Serial Bus) (2 ports, 3 Headers)
• ATI ES1000 16MB Graphic Controller
• Super I/O: Winbond W83627HG w/Hardware Monitor support: W83793G
Other
• External modem ring-on
• Wake-on-LAN (WOL)
• Wake-on-Ring (WOR)
• Console redirection
• Onboard Fan Speed Control by Thermal Management via BIOS
CD/Diskette Utilities
• BIOS fl ash upgrade utility and device drivers
Dimensions
• Ext. ATX 12" (L) x 13.05" (W) (304.80mm x 331.47mm)
1-7
X7DBR-3/X7DBR-E User's Manual
SAS
J5
#6
J14
#3
PCI-E_X4_SLOT(L1)
PCI-E_X4_SLOT(L2)
J12
PCI-X133
PCI-X_Slot(R)ZCR
PXH-V
VRM
ISL6307
LSB
MSB
PCI-E
Slot
J9
#4
PCI-EXP X8
PCI-EXP X8
PCI-Ex4
PCI-Ex8
PCI-X 133
PROCESSOR#2
1067/1333
MT/S
PORT
#4,5
PORT
#6,7
PORT
#2
PORT PORT
PORT
#0
PORT
#1,2
PCIX
5000P
MCH
PORTPORT
PCIE X4
PCIE X4
#4#4
ESB2
PROCESSOR#1
1067/1333
MT/S
FBD CHNL0
FBD CHNL1
FBD CHNL2
FBD CHNL3
#0#3
PCIE X4
ESI
VRM
ISL6307
#0
ATA 100
EXP. BUS
3.0 Gb/S
#1
#0#0
FBD DIMM
FBD DIMM
IDE CONN
EBUS CONN
#5
#4
#3
#2
#1
#0
SATA
#1
#1
FBD DIMM
#1
#0
FBD DIMM
#5
#4
#0
FWH
#3
#2
#1
USB
VGA
CONN
VGA
ES1000
SIMSO
PCI-X_SLOT(L)
PCI 32/33MMZ
RJ45
RJ45
PCI-33
GB LAN
GILGAL
KUMERAN
FDD
SIO
W83627
MS
KB
28-31
HF
USB 2.0
LPC
COM1
COM2
Figure 1-9. Block Diagram of the 5000P Chipset
Note: This is a general chipset block diagram. Please see the previous Motherboard
Features pages for details on the features of each motherboard.
1-8
Chapter 1: Introduction
1-2 Chipset Overview
Built upon the functionality and the capability of the 5000P chipset, the X7DBR-3/
X7DBR-E motherboard provides the performance and feature set required for dual
processor-based servers with confi guration options optimized for communications,
presentation, storage, computation or database applications. The 5000P chipset
supports a single or dual Dempsey 64-bit dual core processor(s) with front side
bus speeds of up to 1.333 GHz. The chipset consists of the 5000P Memory Con-
troller Hub (MCH), the Enterprise South Bridge 2 (ESB2), and the I/O subsystem
(PXH-V).
The 5000P MCH chipset is designed for symmetric multiprocessing across two
independent front side bus interfaces. Each front side bus uses a 64-bit wide, 1333
MHz data bus that transfers data at 10.7 GB/sec. The MCH chipset connects up to
8 Fully Buffered DIMM modules, providing up to 32 GB of DDR2 FBD ECC memory.
The MCH chipset also provides three x8 PCI-Express interface to the ESB2. In
addition, the 5000P chipset offers a wide range of RAS features, including memory
interface ECC, x4/x8 Single Device Data Correction, CRC, parity protection, memory
mirroring and memory sparing.
Xeon Dual Core Processor Features
Designed to be used with conjunction of the 5000P chipset, the Xeon Dual Core
Processor provides a feature set as follows:
The Xeon Dual Core Processor
*L1 Cache Size: Instruction Cache (32KB/16KB), Data Cache (32KB/24KB)
*L2 Cache Size: 4MB (2MB per core)
*Data Bus Transfer Rate: 8.5 GB/s
*Package: FC-LGA6/FC-LGA4, 771 Lands
1-9
X7DBR-3/X7DBR-E User's Manual
1-3 Special Features
Recovery from AC Power Loss
BIOS provides a setting for you to determine how the system will respond when
AC power is lost and then restored to the system. You can choose for the system
to remain powered off (in which case you must hit the power switch to turn it back
on) or for it to automatically return to a power- on state. See the Power Lost Con-
trol setting in the Advanced section (Boot Features) to change this setting. (*Note:
Default: Last State).
1-4 PC Health Monitoring
This section describes the PC health monitoring features of the X7DBR-3/X7DBR-
E. All have an onboard System Hardware Monitor chip that supports PC health
monitoring.
Onboard Voltage Monitors for CPU Cores, Memory, Chipset,
+1.8V, +3.3V, +5V, +12V, −12V, +3.3V Standby, +5V standby and
VBAT
An onboard voltage monitor will scan these voltages continuously. Once a
voltage becomes unstable, a warning is given or an error message is sent to the
screen. Users can adjust the voltage thresholds to defi ne the sensitivity of the
voltage monitor.
Fan Status Monitor with Firmware Control
The PC health monitor can check the RPM status of the cooling fans. The onboard
CPU and chassis fans are controlled by Thermal Management via BIOS (under
Hardware Monitoring in the Advanced Setting).
Environmental Temperature Control
The thermal control sensor monitors the CPU temperature in real time and will turn
on the thermal control fan whenever the CPU temperature exceeds a user-defi ned
threshold. The overheat circuitry runs independently from the CPU. Once it detects
that the CPU temperature is too high, it will automatically turn on the thermal fan
control to prevent any overheat damage to the CPU. The onboard chassis thermal
circuitry can monitor the overall system temperature and alert users when the chas-
sis temperature is too high.
1-10
Chapter 1: Introduction
CPU Overheat LED and Control
This feature is available when the user enables the CPU overheat warning function
in the BIOS. This allows the user to defi ne an overheat temperature. When this tem-
perature is exceeded, both the overheat fan and the warning LED are triggered.
System Resource Alert
This feature is available when used with Supero Doctor III in the Windows OS
environment or used with Supero Doctor II in Linux. Supero Doctor is used to
notify the user of certain system events. For example, if the system is running
low on virtual memory and there is insuffi cient hard drive space for saving the
data, you can be alerted of the potential problem. You can also confi gure Supero
Doctor to provide you with warnings when the system temperature goes beyond
a pre-defi ned range.
1-5 ACPI Features
ACPI stands for Advanced Confi guration and Power Interface. The ACPI specifi -
cation defi nes a fl exible and abstract hardware interface that provides a standard
way to integrate power management features throughout a PC system, including its
hardware, operating system and application software. This enables the system to
automatically turn on and off peripherals such as CD-ROMs, network cards, hard
disk drives and printers. This also includes consumer devices connected to the PC
such as VCRs, TVs, telephones and stereos.
In addition to enabling operating system-directed power management, ACPI
provides a generic system event mechanism for Plug and Play and an operating
system-independent interface for confi guration control. ACPI leverages the Plug
and Play BIOS data structures while providing a processor architecture-independent
implementation that is compatible with Windows 2000, Windows XP and Windows
2003 Server Operating Systems.
Slow Blinking LED for Suspend-State Indicator
When the CPU goes into a suspend state, the chassis power LED will start blinking
to indicate that the CPU is in suspend mode. When the user presses any key, the
CPU will wake-up and the LED will automatically stop blinking and remain on.
1-11
X7DBR-3/X7DBR-E User's Manual
Main Switch Override Mechanism
When an ATX power supply is used, the power button can function as a system
suspend button to make the system enter a SoftOff state. The monitor will be
suspended and the hard drive will spin down. Pressing the power button again
will cause the whole system to wake-up. During the SoftOff state, the ATX power
supply provides power to keep the required circuitry in the system alive. In case
the system malfunctions and you want to turn off the power, just press and hold
the power button for 4 seconds. This option can be set in the Power section of
the BIOS Setup routine.
External Modem Ring-On
Wake-up events can be triggered by a device such as the external modem ringing
when the system is in the SoftOff state. Note that external modem ring-on can only
be used with an ATX 2.01 (or above) compliant power supply.
Wake-On-LAN (WOL)
Wake-On-LAN is defi ned as the ability of a management application to remotely
power up a computer that is powered off. Remote PC setup, up-dates and asset
tracking can occur after hours and on weekends so that daily LAN traffi c is kept to
a minimum and users are not interrupted. The motherboard has a 3-pin header
(WOL) to connect to the 3-pin header on a Network Interface Card (NIC) that has
WOL capability. In addition, an onboard LAN controller can also support WOL with-
out any connection to the WOL header. The 3-pin WOL header is to be used with
a LAN add-on card only. *Note: Wake-On-LAN requires an ATX 2.01 (or above)
compliant power supply.
1-6 Power Supply
As with all computer products, a stable power source is necessary for proper and
reliable operation. It is even more important for processors that have high CPU
clock rates.
The X7DBR-3/X7DBR-E can only accommodate 20-pin ATX power supplies. Al-
though most power supplies generally meet the specifi cations required by the CPU,
some are inadequate. In addition, the 12V 4-pin and the 12V 8-pin power connec-
tions are also required to ensure adequate power supply to the system. Also your
power supply must supply 1.5A for the Ethernet ports.
1-12
Chapter 1: Introduction
It is strongly recommended that you use a high quality power supply that meets ATX
power supply Specifi cation 2.01 or above. It must also be SSI compliant (info at
http://www.ssiforum.org/). Additionally, in areas where noisy power transmission is
present, you may choose to install a line fi lter to shield the computer from noise. It
is recommended that you also install a power surge protector to help avoid problems
caused by power surges.
1-7 Super I/O
The disk drive adapter functions of the Super I/O chip include a fl oppy disk drive
controller that is compatible with industry standard 82077/765, a data separator,
write pre-compensation circuitry, decode logic, data rate selection, a clock genera-
tor, drive interface control logic and interrupt and DMA logic. The wide range of
functions integrated onto the Super I/O greatly reduces the number of components
required for interfacing with fl oppy disk drives. The Super I/O supports 360 K, 720
K, 1.2 M, 1.44 M or 2.88 M disk drives and data transfer rates of 250 Kb/s, 500 Kb/s
or 1 Mb/s.It also provides two high-speed, 16550 compatible serial communication
ports (UARTs). Each UART includes a 16-byte send/receive FIFO, a programmable
baud rate generator, complete modem control capability and a processor interrupt
system. Both UARTs provide legacy speed with baud rate of up to 115.2 Kbps
as well as an advanced speed with baud rates of 250 K, 500 K, or 1 Mb/s, which
support higher speed modems.
The Super I/O supports one PC-compatible printer port (SPP), Bidirectional Printer
Port (BPP) , Enhanced Parallel Port (EPP) or Extended Capabilities Port (ECP).
The Super I/O provides functions that comply with ACPI (Advanced Confi guration
and Power Interface), which includes support of legacy and ACPI power manage-
ment through an SMI or SCI function pin. It also features auto power management
to reduce power consumption.
1-13
X7DBR-3/X7DBR-E User's Manual
Notes
1-14
Chapter 2: Installation
Chapter 2
Installation
2-1 Static-Sensitive Devices
Electric-Static-Discharge (ESD) can damage electronic com ponents. To prevent
damage to your system board, it is important to handle it very carefully. The following
measures are generally suffi cient to protect your equipment from ESD.
Precautions
• Use a grounded wrist strap designed to prevent static discharge.
• Touch a grounded metal object before removing the board from the antistatic
bag.
• Handle the board by its edges only; do not touch its components, peripheral
chips, memory modules or gold contacts.
• When handling chips or modules, avoid touching their pins.
• Put the motherboard and peripherals back into their antistatic bags when not in
use.
• For grounding purposes, make sure your computer chassis provides excellent
conductivity between the power supply, the case, the mounting fasteners and
the motherboard.
• Use only the correct type of onboard CMOS battery as specifi ed by the manu-
facturer. Do not install the onboard battery upside down to avoid possible explo-
sion.
Unpacking
The motherboard is shipped in antistatic packaging to avoid static damage. When
unpacking the board, make sure the person handling it is static protected.
2-1
X7DBR-3/X7DBR-E User's Manual
2-2 Processor and Heatsink Fan Installation
When handling the processor package, avoid placing
direct pressure on the label area of the fan.
(*Notes: 1. Always connect the power cord last and always remove it before adding,
removing or changing any hardware components. Make sure that you install the
processor into the CPU socket before you install the CPU heatsink.
2. Intel's boxed Xeon CPU package contains the CPU fan and heatsink assembly.
If you buy a CPU separately, make sure that you use only Intel-certifi ed multi-di-
rectional heatsink and fan.
3. Make sure to install the motherboard into the chassis before you install the CPU
heatsink and fan.)
4. When purchasing an LGA 771 CPU or when receiving a motherboard with an LGA
771 CPU pre-installed, make sure that the CPU plastic cap is in place and none of
the CPU pins are bent; otherwise, contact the retailer immediately.
5. Refer to the MB Features Section for more details on CPU support.
!
Installation of the LGA771 Processor
1. Press the socket clip to release
the load plate, which covers the CPU
socket, from its locking position.
2. Gently lift the socket clip to open
the load plate.
Socket Clip
Load Plate
2-2
Load Plate
Chapter 2: Installation
3. Use your thumb and your index
fi nger to hold the CPU at the North
Center Edge and the South Center
Edge of the CPU.
4. Align CPU Pin1 (the CPU corner
marked with a triangle) against the
socket corner that is marked with a
triangle cutout.
5. Align the CPU key that is the
semi-circle cutout below a gold dot
against the socket key, the notch on
the same side of the triangle cutout
on the socket.
6. Once aligned, carefully lower the
CPU straight down to the socket.
(**Do not drop the CPU on the
socket. Do not move the CPU hori-
zontally or vertically. Do not rub the
CPU against the surface or against
any pins of the socket to avoid dam-
age to the CPU or the socket.)
Socket Key
(Socket Notch)
CPU Key (semi-
circle cutout)
below the circle.
Corner with a
triangle cutout
North Center Edge
South Center Edge
gold dot
CPU Pin1
7. With the CPU inside the socket,
inspect the four corners of the CPU
to make sure that the CPU is prop-
erly installed.
8. Use your thumb to gently push the
socket clip down to the clip lock.
9. If the CPU is properly installed
into the socket, the plastic cap will
be automatically released from the
load plate when the clip is pushed in
the clip lock. Remove the plastic cap
from the motherboard.
!
(*Warning: Please keep the
plastic cap. The motherboard and the
CPU must be shipped with the plas-
tic cap properly installed to protect
the CPU pins. Shipment without the
CPU plastic cap properly installed
will void the warranty.)
Socket clip
CPU in the CPU socket
Plastic cap
is released
from the
load plate
if the CPU
is properly
installed.
2-3
X7DBR-3/X7DBR-E User's Manual
Installation of the Heatsink
CEK Heatsink Installation
1. Do not apply any thermal grease to
the heatsink or the CPU die-the required
amount has already been applied.
2. Place the heatsink on top of the
CPU so that the four mounting holes
are aligned with those on the retention
mechanism.
3. Screw in two diagonal screws (ie the
#1 and the #2 screws) until just snug (-do
not fully tighten the screws to avoid pos-
sible damage to the CPU.)
CEK Passive Heatsink
Screw#1
Screw#2
4. Finish the installation by fully tightening
all four screws.
To Un-install the Heatsink
(Warning: We do not recommend
!
that the CPU or the heatsink be
removed. However, if you do need
to uninstall the heatsink, please
follow the instructions below to
uninstall the heatsink to prevent
damage done to the CPU or the
CPU socket.)
Screw#1
Screw#2
2-4
1. Unscrew and remove the heatsink
screws from the motherboard in the
sequence as show in the picture on the
right.
2. Hold the heatsink as shown in the
picture on the right and gently wiggle the
heatsink to loosen it from the CPU. (Do
not use excessive force when wiggling
the heatsink!!)
3. Once the heatsink is loosened, remove
the heatsink from the CPU socket.
Chapter 2: Installation
4. Clean the surface of the CPU and
the heatsink to get rid of the old thermal
grease. Reapply the proper amount of
thermal grease on the surface before you
re-install the CPU and the heatsink.
Mounting the Motherboard in the Chassis
All motherboards have standard mounting holes to fi t different types of chas-
sis. Make sure that the locations of all the mounting holes for both motherboard
and chassis match. Make sure that the metal standoffs click in or are screwed in
tightly. Then, use a screwdriver to secure the motherboard onto the motherboard
tray. (*Note: some components are very close to the mounting holes. Please take
precautionary measures to prevent damage done to these components when you
install the motherboard to the chassis.)
2-5
X7DBR-3/X7DBR-E User's Manual
2-3 Installing DIMMs
Note: Check the Supermicro web site for recommended memory modules.
CAUTION
Exercise extreme care when installing or removing DIMM
modules to prevent any possible damage. Also note that the
memory is interleaved to improve performance (see step 1).
DIMM Installation (See Figure 2-2)
1. Insert the desired number of DIMMs into the memory slots, starting with DIMM
#1A. The memory scheme is interleaved, so you must install two modules
at a time, beginning with DIMM #1A, then DIMM #2A and so on. For optimal
performance, please install memory modules in both Branch 0 and Branch 1
at the same time (up to 8 modules maximum.) (*See the Memory Installation
Table Below.)
(*See the Memory Installation Table Below.)
2. Insert each DIMM module vertically into its slot. Pay attention to the notch along
the bottom of the module to prevent inserting the DIMM module incorrectly.
3. Gently press down on the DIMM module until it snaps into place in the slot.
Repeat for all modules (see step 1 above).
Memory Support
The X7DBR-3/X7DBR-E supports up to 32 GB fully buffered (FBD) ECC DDR2
533/667 in 8 DIMMs. Populating DIMM modules with pairs of memory modules
of the same size and same type will result in Interleaved Memory which will
increase memory performance.
*Note 1: Due to OS limitations, some operating systems may not show more than
4 GB of memory.
Optimized DIMM Population Configurations
Branch 0 Branch 1
Number of
DIMMs
2 DIMMs 1A
4 DIMMs 1A
8 DIMMs 1A 1B
Bank 1
(Channel 0)
---------
---------
------
Bank 2
(Channel 1)
---------------------------------
2A
---------
2A
2A 2B
------
Bank 3
(Channel 2)
---------
3A
3A 3B
------
Bank 4
(Channel 3)
---------
4A
4A 4B
------
(*Notes: i. DIMM slot# specified: DIMM slot to be populated; “---“: DIMM slot not to
be populated. ii. Both FBD 533 MHz and 667MHz DIMMs are supported; however,
you need to use the memory modules of the same type and of the same speed on a
motherboard. iii. Interleaved memory is supported when pairs of DIMM modules are
installed. For best performance, please install memory modules of the same type and
of the same speed in both Branch 0 and Branch 1. iv. For memory to work
properly, you need to follow the restrictions listed above. )
2-6
Chapter 2: Installation
*Note 2: Due to memory allocation to system devices, memory remaining avail-
able for operational use will be reduced when 4 GB of RAM is used. The reduction
in memory availability is disproportional. (Refer to the Memory Availability Table
below for details.)
Possible System Memory Allocation & Availability
®
UPER X7DBR-3/E
S
System DeviceSizePhysical Memory
Firmware Hub fl ash memory
(System BIOS)
Local APIC4 KB3.99
Area Reserved for the chipset2 MB3.99
I/O APIC (4 Kbytes)4 KB3.99
PCI Enumeration Area 1256 MB3.76
PCI Express (256 MB)256 MB3.51
PCI Enumeration Area 2 (if
needed) -Aligned on 256-MB
boundary-
VGA Memory16 MB2.85
TSEG1 MB2.84
Memory available to OS &
other applications
1 MB3.99
512 MB3.01
Remaining (-Available)
(4 GB Total System Memory)
2.84
Figure 2-2. Installing and Removing DIMMs
®BD
To Remove:
Use your thumbs to
gently push the release tabs near both
ends of the module.
This should release
it from the slot.
To Install: Insert module vertically and press down until it
snaps into place. Pay attention to the alignment notch at
the bottom.
BD®S ot
2-7
X7DBR-3/X7DBR-E User's Manual
2-4 Control Panel Connectors/IO Ports
The I/O ports are color coded in conformance with the PC 99 specifi cation. See
Figure 2-3 below for the colors and locations of the various I/O ports.
A. Back Panel Connectors/IO Ports
®
UPER X7DBR-3/E
S
4
2
1
3
5
7
6
89
Figure 2-3. Back Panel I/O Port Locations and Defi nitions
Back Panel Connectors
1. Keyboard (Purple)
2. PS/2 Mouse (Green)
3. Back Panel USB Port 0
4. Back Panel USB Port 1
5. COM Port 1 (Turquoise)
6. Gigabit LAN 1
7. Gigabit LAN 2
8. VGA Port (Blue)
9. SAS#4-#7 (*X7DBR-3 only)
(*See Section 2-5 for details.)
2-8
Chapter 2: Installation
B. Front Control Panel
JF1 contains header pins for various buttons and indicators that are normally located
on a control panel at the front of the chassis. These connectors are designed specifi -
cally for use with Supermicro server chassis. See Figure 2-4 for the descriptions of
the various control panel buttons and LED indicators. Refer to the following section
for descriptions and pin defi nitions.
Figure 2-4. JF1 Header Pins
®
UPER X7DBR-3/E
S
Ground
X
Power LED
HDD LED
NIC1 LED
NIC2 LED
OH/Fan Fail LED
PWR Fail LED
Ground
Ground
1920
NMI
X
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Reset
PWR
2
1
Reset Button
Power Button
2-9
X7DBR-3/X7DBR-E User's Manual
C. Front Control Panel Pin Defi nitions
NMI Button
The non-maskable interrupt button
header is located on pins 19 and 20
of JF1. Refer to the table on the right
for pin defi nitions.
Power LED
The Power LED connection is located
on pins 15 and 16 of JF1. Refer to the
table on the right for pin defi nitions.
NMI Button
Pin Defi nitions (JF1)
Pin# Defi nition
19Control
20Ground
Power LED
Pin Defi nitions (JF1)
Pin# Defi nition
15+5V
16Ground
KB
MS
USB0/1
COM1
GLAN1
Pres#4-7
Act#4-7
GLAN2
VGA
SAS 4-7
C
S
Bank4
Bank3
Bank2
Bank1
PXH-V
LAN
G
CTRLR
JPL1
JPL2
2
OM
A. NMI
B. PWR LED
®
UPER X7DBR-3/E
DIMM 4B
DIMM 4A
DIMM 3B
DIMM 3A
DIMM 2B
DIMM 2A
DIMM 1B
DIMM 1A
C2
C1
2
2
JI
JI
PCI-X 100MHz ZCRSXB-
PCI-X 133MHz
VGA
CTRLR
JPG1
JP10
SM
SIMSO
IPMB
JP11
3rd PWR
Fail
North Bridge
Battery
SAS
CTRLR
JPS1
B
W
OR
SXB-
S I/O
LE1
PWLED SPK
1920
PWR
SMB
JPWF
JAR
E1x8
SXB-
E2x8
E3x8
South
Bridge
USB4/5
J8
J4E3
CPU1
CPU2
W
USB2/3
4-pin
8-pin PWR
PWR
20-pin ATX Main PWR
Fan1
Fan2
B
FP Ctrl
Fan3
Fan4
OH/Fan Fail LED
Fan5
JWD
Flash
JCF1
IDE1
F1
JW
Compact
Floppy
SGPIO1
SGPIO2
BIOS
JP12
JOH1
Pre#0-3
Act#0-3
SATA5
SATA4
SAS 1-3
JS10
J7
JL1
JBT1
Buzzer
L
O
SATA1
SATA3
SATA2
SATA0
Ground
X
Power LED
HDD LED
NIC1 LED
NIC2 LED
PWR Fail LED
Ground
Ground
NMI
A
X
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Reset
Reset Button
Power Button
PWR
2
1
2-10
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