Supero SUPER P3TDLR User Manual

SUPER

SUPER P3TDLR

®

USER’S MANUAL

Revision 1.0a

The information in this User’s Manual has been carefully reviewed and is believed to be
accurate. The vendor assumes no responsibility for any inaccuracies that may be contained
in this document, makes no commitment to update or to keep current the information in this
manual, or to notify any person or organization of the updates.

Please Note: For the
most up-to-date version of this manual, please see our web site at
www.supermicro.com.

SUPERMICRO COMPUTER reserves the right to make changes to the product described in
this manual at any time and without notice. This product, including software, if any, and
documentation may not, in whole or in part, be copied, photocopied, reproduced, translated or
reduced to any medium or machine without prior written consent.

IN NO EVENT WILL SUPERMICRO COMPUTER BE LIABLE FOR DIRECT, INDIRECT,
SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING FROM THE USE OR
INABILITY TO USE THIS PRODUCT OR DOCUMENTATION, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. IN PARTICULAR, THE VENDOR SHALL NOT HAVE
LIABILITY FOR ANY HARDWARE, SOFTWARE, OR DATA STORED OR USED WITH THE
PRODUCT, INCLUDING THE COSTS OF REPAIRING, REPLACING, INTEGRATING,
INSTALLING OR RECOVERING SUCH HARDWARE, SOFTWARE, OR DATA.

Any disputes arising between manufacturer and customer shall be governed by the laws of
Santa Clara County in the State of California, USA. The State of California, County of Santa
Clara shall be the exclusive venue for the resolution of any such disputes. Supermicro's total
liability for all claims will not exceed the price paid for the hardware product.

Unless you request and receive written permission from SUPER MICRO COMPUTER, you
may not copy any part of this document.

Information in this document is subject to change without notice. Other products and
companies referred to herein are trademarks or registered trademarks of their respective
companies or mark holders.

Copyright © 2001 by SUPER MICRO COMPUTER INC.
All rights reserved.

Printed in the United States of America.

Preface

About This Manual

This manual is written for system integrators, PC technicians and
knowledgeable PC users. It provides information for the installation and use
of the SUPER P3TDLR motherboard. The SUPER P3TDLR supports single or
dual Pentium® III FCPGA 500 MHz-1.26 GHz+ processors, including low
power Pentium III® processors, at front side bus speeds of 133 and 100
MHz. Please refer to the support section of our web site (http://
www.supermicro.com/TechSupport.htm) for a complete listing of supported
processors. Intel FCPGA processors are housed in a 370-pin package.

Manual Organization

Chapter 1 includes a checklist of what should be included in your

mainboard box, describes the features, specifications and performance of
the SUPER P3TDLR mainboard and provides detailed information about the
chipset.

Chapter 2 begins with instructions on handling static-sensitive devices.
Read this chapter when you want to install the processor and DIMM memory
modules and when mounting the mainboard in the chassis. Also refer to
this chapter to connect the floppy and hard disk drives, SCSI drives, the IDE
interfaces, the parallel and serial ports and the twisted wires for the power
supply, the reset button, the keylock/power LED, the speaker and the key­board.

Preface

If you encounter any problems, read Chapter 3, which describes trouble-
shooting procedures for the video, the memory and the setup configuration
stored in CMOS. For quick reference, a general FAQ [Frequently Asked
Questions] section is provided. Instructions are also included for contact­ing technical support. In addition, you can visit our web site at:

< www.supermicro.com/techsupport.htm >

for more detailed information.

Chapter 4 includes an introduction to BIOS and provides detailed informa­tion on running the CMOS Setup utility.

Appendix A gives information on BIOS error beep codes and messages.

Appendix B provides post diagnostic error messages.

iii

SUPER P3TDLR User’s Manual

Table of Contents

Preface

About This Manual ...................................................................................................... iii

Manual Organization ................................................................................................... iii

Chapter 1: Introduction

1-1 Overview ......................................................................................................... 1- 1

Checklist .................................................................................................... 1 - 1

Contacting Supermicro ............................................................................ 1 - 2

SUPER P3TDLR Image ............................................................................. 1-3

SUPER P3TDLR Layout ........................................................................... 1-4

SUPER P3TDLR Quick Reference .......................................................... 1-5

Server Works LE Chipset: System Block Diagram ............................. 1- 6

SUPER P3TDLR Motherboard Features................................................ 1-7

1-2 Chipset Overview........................................................................................... 1-9

1-3 Special Features ............................................................................................. 1-9

ATI Graphics Controller ........................................................................... 1 -9

BIOS Recovery ......................................................................................... 1-9

Recovery from AC Power Loss ........................................................... 1-9

1-4 PC Health Monitoring.................................................................................... 1-10

1-5 ACPI/PC 98 Features ................................................................................... 1-11

1-6 Power Supply ............................................................................................... 1-13

1- 7 Super I/O......................................................................................................... 1-13

Chapter 2: Installation

2-1 Handling the P3TDLR Motherboard.............................................................. 2-1

Preca utio ns ............................................................................................... 2-1

Unpacking .................................................................................................. 2 -2

2-2 Motherboard Installation ................................................................................ 2-2

2-3 Connecting Cables ......................................................................................... 2- 3

Connecting Data Cables .......................................................................... 2 - 3

Connecting Power Cables....................................................................... 2 -3

Connecting the Control Panel ................................................................. 2 -4

2-4 I/ O P o rt s ............................................................................................................ 2- 5

2-5 Installing Processors ...................................................................................... 2 -5

2-6 Installing Memory ............................................................................................ 2-7

2-7 Connector Definitions .................................................................................... 2-9

Power Supply Connectors ..................................................................... 2-9

Power Supply Fail Enable/Disable ......................................................... 2 - 9

iv

Table of Contents

Power LED ............................................................................................... 2-10

HDD LED .................................................................................................. 2-10

NIC1 LED .................................................................................................. 2-10

NIC2 LED .................................................................................................. 2-10

Overheat LED .......................................................................................... 2-11

Reset......................................................................................................... 2-11

PWR_ON ................................................................................................... 2-11

Fan Headers ............................................................................................ 2-12

Serial Ports .............................................................................................. 2-12

Universial Serial Bus .............................................................................. 2-13

Extra USB Connectors ........................................................................... 2-13

LAN1/LAN2 Ports .................................................................................... 2-13

SLED1 (SCSI LED) Indicator.................................................................. 2-13

Wake-On-Modem ..................................................................................... 2-14

Wake-On-LAN ......................................................................................... 2-14

2- 8 DIP Switch Settings ..................................................................................... 2-14

DIP Switch 1: Core/Bus Ratio.............................................................. 2-14

2-9 Jumper Settings ............................................................................................ 2-15

Explaination of Jumpers ........................................................................ 2-15

Front Side Bus Speed ........................................................................... 2-15

PCI64 Speed Setting ...............................................................................2-15

CMOS Clear............................................................................................. 2-16

Over Heat Alarm ..................................................................................... 2-16

LAN1 Enable/Disable .............................................................................. 2-16

LAN2 Enable/Disable .............................................................................. 2-16

SCSI Enable/Disable................................................................................ 2-17

Onboard VGA Enable/Disable ............................................................... 2-17

Watchdog Reset Enable/Disable .......................................................... 2-17

2-10 Floppy/Hard Disk and SCSI Connections ................................................. 2-18

Floppy Connector ................................................................................... 2-18

IDE Connectors ...................................................................................... 2-18

Ultra160 SCSI Connector ....................................................................... 2-19

2-11 Installing Software Drivers ......................................................................... 2-20

v

SUPER P3TDLR User’s Manual

Chapter 3: Troubleshooting

3-1 Troubleshooting Procedures ........................................................................ 3-1

Before Power On .................................................................................... 3-1

No Power .................................................................................................. 3-1

No Video ................................................................................................... 3-1

Memory Errors .......................................................................................... 3-2

Losing the System’s Setup Configuration ........................................... 3- 2

3-2 Technical Support Procedures .................................................................... 3-2

3-3 Frequently Asked Questions ........................................................................ 3-3

3-4 Returning Merchandise for Service ............................................................ 3-5

Chapter 4: BIOS

4-1 Introduction....................................................................................................... 4 -1

4-2 BIOS Features.................................................................................................. 4-2

4-3 Running Setup.................................................................................................. 4-2

Main BIOS Setup Menu ............................................................................ 4-3

4-4 Advanced BIOS Setup .................................................................................... 4 -4

4-5 Chipset Setup ................................................................................................. 4-15

4-6 PCI PnP Setup ................................................................................................ 4-17

4-7 Power Setup .................................................................................................. 4-21

4-8 Boot Setup ...................................................................................................... 4-24

4-9 Security Setup ............................................................................................... 4-26

4-10 Exit Setup ....................................................................................................... 4-28

Appendices:

Appendix A: BIOS Error Beep Codes and Messages ....................................... A - 1

Appendix B: AMIBIOS Post Checkpoint Codes .................................................... B- 1

vi

Chapter 1: Introduction

Chapter 1

Introduction

1-1 Overview

Checklist

Congratulations on purchasing your computer motherboard from an ac­knowledged leader in the industry. Supermicro boards are designed with
the utmost attention to detail to provide you with the highest standards in
quality and performance.

Please check that the following items have all been included with your
motherboard. If anything listed here is damaged or missing, contact your
retailer.

One (1) Supermicro Mainboard

Two (2) Supermicro Heatsinks (Retail Only)

Introduction

One (1) ribbon cable for IDE devices

One (1) floppy ribbon cable for (1) 5.25-inch floppy and (2) 3.5-inch floppy
drives

One (1) I/O backpanel shield

SCSI Accessories (depending on motherboard)

One (1) 68-pin LVD SCSI cable

One (1) set of SCSI driver diskettes

One (1) SCSI manual

One (1) Supermicro CD or diskettes containing drivers and utilities

One (1) BIOS User's Manual

1-1

SUPER P3TDLR User's Manual

CONTACTING SUPERMICRO

Introduction

Headquarters

Address: Super Micro Computer, Inc.

980 Rock Avenue

San Jose, CA 95131 U.S.A.
Tel: [phone]
Fax: [phone]
E-mail: [email protected] (General Information)

[email protected] (Technical Support)

Web site: www.supermicro.com

European Office

Address: Super Micro Computer B.V.

Het Sterrenbeeld 28, 5215 ML,
's-Hertogenbosch, The Netherlands
Tel: [phone]

Fax: [phone]

E-mail: [email protected] (General Infor­mation) [email protected]
(Technical Support)
[email protected] (Customer Support)

Asia-Pacific

Address: F3, #753 Chung-Cheng Road

Chung-Ho City, Taipei Hsien, Taiwan, R.O.C.
Tel: [phone]
Fax: [phone]
www : www.supermicro.com.tw
Email: [email protected]
Technical Support:

Tel : [phone], ext.132

1-2

SUPER P3TDLR

Figure 1-4A. SUPER P3TDLR Image

Chapter 1: Introduction

Introduction

1-3

SUPER P3TDLR User's Manual

Introduction

PS/2 KB/

MOUSE

COM1

Parallel

VGA

12"

JP8

®

J28

USB

J27
Port

NIC1

NIC2

CPU FAN

J14

J15

J11

J12

JP24

CPU
FAN

SUPER P3TDLR

Figure 1-8A. SUPER P3TDLR Layout

(not drawn to scale)

10.5"

ATX POWER

FCPGA

Processor

BANK1

1

JP1

BANK0

AIC­7892

SW1

FCPGA

Processor

PCI64 #1

PCI64 #2

PCI 1

PCI 2

ATI

RAGE

XL

NORTH
BRIDGE

1

JP2

SOUTH
BRIDGE

BIOS

COM2

SUPER

I/O

BANK2

JP7

JP11

JP7

BANK3

WOM

1

JBT1

JA21 SLED

WOL

IDE #1

J23

BATTERY

J106

CH FAN

THRM FAN

J26 J24

JF1

BLOWER FAN

CHASSIS FAN

J105

CH FAN

FLOPPY

IDE #2

ULTRA160 LVD SCSI

JA1

Also see the figure on page 2-7 for the locations of the I/O ports and
2-8 for the Front Control Panel (JF1) connectors.

1-4

Chapter 1: Introduction

P3TDLR Quick Reference

Jumpers Description Default Setting

JBT1 CMOS Clear (p. 2-18) Pins 1-2 (Normal)
JP1 SCSI (p. 2-19) Pins 1-2 (Enabled)
JP2 Front Side Bus Speed (p. 2-17) Pins 1-2 (Auto)
JP7 Overheat Alarm (p. 2-18) Closed (Enabled)
JP8 LAN1 Enable/Disable (p. 2-18) Open (Enabled)
JP11 Power Supply Fail (p. 2-11) Pin 4 (Reset)
JP12 Power Supply Fail (p. 2-11) Closed (Enabled)
JP13 Speed for 64-bit PCI (2-17) Closed (33 MHz)
JP24 LAN2 Enable/Disable (p. 2-18) Open (Enabled)
JP62 Onboard VGA (p. 2-19) Pins 1-2 (Enabled)
J210 Watchdog Reset (p. 2-19) Open (Disabled)

DIP Switches Description Default Setting
SW1(1-4) CPU Core/Bus Ratio (see p. 2-16)

Connectors Description

ATX Power 24-pin ATX Power Connector (p. 2-11)
DIMM0-DIMM3 Memory (SDRAM) Slots (p. 2-9)
COM1/2 COM1/COM2 Serial Port Connector (p. 2-14)
CPU FAN (2 ea) CPU1/CPU2 Fan Header (p. 2-14)
Fan Headers (5 ea) Chassis, thermal and blower (p. 2-14)
J23/J24 IDE Hard Disk Drive 1/2 Connectors (p. 2-20)
J26 Floppy Disk Drive Connector (p. 2-20)
J28 PS/2 Keyboard/Mouse (p. 2-9)
J105/106 USB3/USB4 (p. 2-15)
JA1 Ultra160 LVD SCSI Connector (p. 2-21)
JF1 Front Control Panel (p. 2-4)
JP61 PWR_LED (p. 2-4)
LAN1/2 Ethernet Ports 1/2 (p. 2-15)
SLED1 SCSI LED header (p. 2-15)
USB 1/2 Universal Serial Bus 1/2 Ports (p. 2-15)
WOL Wake-on-LAN Header (p. 2-16)
WOM Wake-on-Modem Header (p. 2-16)

Introduction

1-5

SUPER P3TDLR User's Manual

Introduction

64-bit

PCI Slots

Ultra160

SCSI Slot

USB

Ports

Pe ntiu m III

FCPGA

CPU

133/100 MHz Ho st Bus

66/33 MHz

Host (North) Bridge

1.5 Mb/sec

OSB4/OSB5

South Bridge

CNB30LE

BIOS 4Mb

Flash ROM

Pe ntiu m III

FCPGA

CPU

PC133/PC100

Registered

DIMMs

133/100 MHz

33 MHz

32-bit

PCI Slots

ATA33 IDE

Ports

Figure 1-9. ServerWorks LE Chipset:

System Block Diagram

*Note: This is a general block diagram. See next page for details on

actual processor support and PCI slots for your motherboard.

1-6

Chapter 1: Introduction

Features of the SUPER P3TDLR

CPU

• Single or dual Intel Pentium® III FCPGA 500 MHz-1.26+ GHz processors
and single or dual low power Pentium® III processors at front bus
speeds of 133 and 100 MHz

Note: Please refer to the support section of our web site for a complete listing of supported
processors. (http://www.supermicro.com/TechSupport.htm)

Memory

• Four 168-pin DIMM sockets supporting up to 4 GB registered ECC
DIMMs

Note: The memory and front side bus speeds are synchronized. If PC133 memory is used with a
100 MHz FSB, the memory will run at 100 MHz. See page 3-3 for details.

Chipset

• ServerWorks ServerSet III LE (see page 1-19 for details)

Expansion Slots

• Two 64-bit, 66/33 MHz PCI slots

• Two 32-bit, 33 MHz PCI slots

Introduction

BIOS

• 4 Mb AMI® Flash BIOS

• APM 1.2, DMI 2.1, PCI 2.2, ACPI 1.0, Plug and Play (PnP)

PC Health Monitoring

• Seven onboard voltage monitors for CPU core, chipset voltage, +5V
and +12V

• Fan status monitor with firmware/software on/off control

• Environmental temperature monitor and control

• CPU fan auto-off in sleep mode

• Power-up mode control for recovery from AC power loss

• System overheat LED and control

• System resource alert

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SUPER P3TDLR User's Manual

Introduction

ACPI/PC 98 Features

• Microsoft OnNow

• Slow blinking LED for suspend state indicator

• Main switch override mechanism

• External modem ring-on

Onboard I/O

• AIC-7892 for single channel Ultra160 SCSI

• 66 MHz SCSI supported

• Integrated ATI Rage XL Graphics Controller

• Intel 82559 for integrated onboard Ethernet

• 2 EIDE bus master interfaces support Ultra DMA/33

• 1 floppy port interface (up to 2.88 MB)

• 2 Fast UART 16550A compatible serial ports

• 1 EPP (Enhanced Parallel Port) and ECP (Extended Capabilities Port)

• PS/2 mouse and PS/2 keyboard ports

• 4 USB (Universal Serial Bus) ports

Other

• Selectable CPU and chassis fan speed control (set in BIOS)

• Internal/external modem ring-on

• Recovery from AC power loss control

• Wake-on-LAN (WOL)

• Multiple FSB clock frequency selections (set in BIOS)

supported parallel port

CD/Diskette Utilities

• BIOS flash upgrade utility

• Device Drivers

Dimensions

• SUPER P3TDLR - Full ATX: 12" x 10.5" (305 x 267 mm)

1-8

Chapter 1: Introduction

1-2 Chipset Overview

The ServerWorks ServerSetTM III LE is a high-performance core logic chipset
that consists of a North Bridge and a South Bridge.

The North Bridge includes an integrated main memory subsystem and a dual
channel PCI bus that bridges the processor bus to a 64-bit PCI bus and a
32-bit PCI bus. The North Bridge also packs and unpacks data for PCI
accesses, which reserves more processor bandwidth for multiprocessor
motherboards.

The South Bridge provides various integrated functions, including the PCI to
ISA bridge and support for UDMA33, security (passwords and system pro­tection), Plug & Play, USBs, power management, interrupt controllers and
the SMBus.

The North and South Bridges communicate over a serial bus that uses the
PCI clock as a timing reference. This serial bus uses a single pin on both
bridges to send a 4-bit word for transmitting commands back and forth.

1-3 Special Features

Introduction

ATI Graphics Controller

The P3TDLR has an integrated ATI video controller based on the Rage XL
graphics chip. The Rage XL fully supports sideband addressing and AGP
texturing. An 8 MB graphics memory chip has been integrated aboard the
P3TDLR to provide graphics memory. This onboard graphics package can
provide a bandwidth of up to 512 MB/sec over a 32-bit graphics memory
bus.

BIOS Recovery

The BIOS Recovery function allows you to use an image file to recover your
BIOS if the BIOS flashing procedure fails (see Section 3-3).

Recovery from AC Power Loss

BIOS provides a setting for you to determine how the system will respond
when AC power is lost and then restored to the system. You can choose
for the system to remain powered off (in which case you must press the

1-9

SUPER P3TDLR User's Manual

power switch to turn it back on) or for it to automatically return to a power
on state. See the Power Lost Control setting in the BIOS chapter of this
manual to change this setting. The default setting is "Always OFF."

Introduction

1-4 PC Health Monitoring

This section describes the PC health monitoring features of the SUPER
P3TDLR. All have an onboard System Hardware Monitor chip that supports
PC health monitoring.

Seven Onboard Voltage Monitors for the CPU Core, Chipset
Voltage, +5V and +12V

The onboard voltage monitor will scan these seven voltages continuously. Once
a voltage becomes unstable, it will give a warning or send an error message to
the screen. Users can adjust the voltage thresholds to define the sensitivity of
the voltage monitor.

Fan Status Monitor with Firmware/Software On/Off Control

The PC health monitor can check the RPM status of the cooling fans. The
onboard 3-pin CPU and chassis fans are controlled by the power management
functions. The thermal fan is controlled by the overheat detection logic.

Environmental Temperature Control

The thermal control sensor monitors the CPU temperature in real time and will
turn on the thermal control fan whenever the CPU temperature exceeds a user­defined threshold. The overheat circuitry runs independently from the CPU. It
can continue to monitor for overheat conditions even when the CPU is in sleep
mode. Once it detects that the CPU temperature is too high, it will automatically
turn on the thermal control fan to prevent any overheat damage to the CPU. The
onboard chassis thermal circuitry can monitor the overall system temperature
and alert users when the chassis temperature is too high.

CPU Fan Auto-Off in Sleep Mode

The CPU fan activates when the power is turned on. It can be turned off when
the CPU is in sleep mode. When in sleep mode, the CPU will not run at full
power, thereby generating less heat.

1-10

Chapter 1: Introduction

CPU Overheat LED and Control

This feature is available when the user enables the CPU overheat warning
function in the BIOS. This allows the user to define an overheat tempera­ture. When this temperature is exceeded, both the overheat fan and the
warning LED are triggered.

System Resource Alert

This feature is available when used with Intel's LANDesk Client Manager (op­tional). It is used to notify the user of certain system events. For example, if
the system is running low on virtual memory and there is insufficient hard drive
space for saving the data, you can be alerted of the potential problem.

Hardware BIOS Virus Protection

The system BIOS is protected by hardware so that no virus can infect the BIOS
area. The user can only change the BIOS content through the flash utility
provided by SUPERMICRO. This feature can prevent viruses from infecting the
BIOS area and destroying valuable data.

Auto-Switching Voltage Regulator for the CPU Core

The auto-switching voltage regulator for the CPU core can support up to 20A
current and auto-sense voltage IDs ranging from 1.4V to 3.5V. This will allow the
regulator to run cooler and thus make the system more stable.

1-5 ACPI/PC 98 Features

ACPI stands for Advanced Configuration and Power Interface. The ACPI speci­fication defines a flexible and abstract hardware interface that provides a stan­dard way to integrate power management features throughout a PC system,
including its hardware, operating system and application software. This enables
the system to automatically turn on and off peripherals such as CD-ROMs,
network cards, hard disk drives and printers. This also includes consumer
devices connected to the PC such as VCRs, TVs, telephones and stereos.

Introduction

In addition to enabling operating system-directed power management, ACPI pro­vides a generic system event mechanism for Plug and Play and an operating
system-independent interface for configuration control. ACPI leverages the Plug
and Play BIOS data structures while providing a processor architecture-indepen­dent implementation that is compatible with both Windows 98 and Windows NT

1-11

SUPER P3TDLR User's Manual

5.0. Note: To utilize ACPI, you must reinstall Windows 98/2000. You can
check to see if ACPI has been properly installed by looking for it in the

Introduction

Device Manager, which is located in the Control Panel in Windows.

Microsoft OnNow

The OnNow design initiative is a comprehensive, system-wide approach to
system and device power control. OnNow is a term for a PC that is always
on but appears to be off and responds immediately to user or other re­quests.

Slow Blinking LED for Suspend-State Indicator

When the CPU goes into a suspend state, the chassis power LED will start
blinking to indicate that the CPU is in suspend mode. When the user presses
any key, the CPU will wake-up and the LED will automatically stop blinking and
remain on.

Main Switch Override Mechanism

When an ATX power supply is used, the power button can function as a system
suspend button. When the user depresses the power button, the system will
enter a SoftOff state. The monitor will be suspended and the hard drive will spin
down. Depressing the power button again will cause the whole system to wake­up. During the SoftOff state, the ATX power supply provides power to keep the
required circuitry in the system alive. In case the system malfunctions and you
want to turn off the power, just depress and hold the power button for 4 seconds.
The power will turn off and no power will be provided to the motherboard.

External Modem Ring-On

Wake-up events can be triggered by a device such as the external modem ringing
when the system is in the SoftOff state. Note that external modem ring-on can
only be used with an ATX 2.01 (or above) compliant power supply.

Wake-On-LAN (WOL)

Wake-On-LAN is defined as the ability of a management application to remotely
power up a computer that is powered off. Remote PC setup, updates and

1-12

Chapter 1: Introduction

asset tracking can occur after hours and on weekends so that daily LAN
traffic is kept to a minimum and users are not interrupted. The motherboards
have a 3-pin header (WOL) to connect to the 3-pin header on a Network
Interface Card (NIC) that has WOL capability. Wake-On-LAN must be en­abled in BIOS. Note that Wake-On-Lan can only be used with an ATX 2.01
(or above) compliant power supply.

1-6 Power Supply

As with all computer products, a stable power source is necessary for
proper and reliable operation. It is even more important for processors that
have high CPU clock rates.

The SUPER P3TDLR accommodates ATX power supplies. Although most
power supplies generally meet the specifications required by the CPU, some
are inadequate. You should use one that will supply at least 300W of
power - or even higher wattage power supply is recommended for high­load configurations. Also your power supply must provide a +5V standby
voltage that supplies at least 1.5A of current.

It is strongly recommended that you use a high quality power supply that
meets ATX power supply Specification 2.02 or above. Additionally, in ar­eas where noisy power transmission is present, you may choose to install
a line filter to shield the computer from noise. It is recommended that you
also install a power surge protector to help avoid problems caused by
power surges.

1-7 Super I/O

The disk drive adapter functions of the Super I/O chip include a floppy disk
drive controller that is compatible with industry standard 82077/765, a data
separator, write pre-compensation circuitry, decode logic, data rate selec­tion, a clock generator, drive interface control logic and interrupt and DMA
logic. The wide range of functions integrated onto the Super I/O greatly
reduces the number of components required for interfacing with floppy disk
drives. The Super I/O supports 360 K, 720 K, 1.2 M, 1.44 M or 2.88 M disk
drives and data transfer rates of 250 Kb/s, 500 Kb/s or 1 Mb/s. It also
provides two high-speed, 16550 compatible serial communication ports
(UARTs), one of which supports serial infrared communication. Each UART
includes a 16-byte send/receive FIFO, a programmable baud rate generator,
complete modem control capability and a processor interrupt system.
Each UART includes a 16-byte send/receive FIFO, a programmable baud

Introduction

1-13

SUPER P3TDLR User's Manual

rate generator, complete modem control capability and a processor inter­rupt system. Both UARTs provide legacy speed with baud rate of up to

115.2 Kbps as well as an advanced speed with baud rates of 250 K, 500 K,

Introduction

or 1 Mb/s, which support higher speed modems.

The Super I/O supports one PC-compatible printer port (SPP), Bi-directional
Printer Port (BPP) , Enhanced Parallel Port (EPP) or Extended Capabilities Port
(ECP).

The Super I/O provides functions that comply with ACPI (Advanced Configuration
and Power Interface), which includes support of legacy and ACPI power manage­ment through an SMI or SCI function pin. It also features auto power manage­ment to reduce power consumption.

The IRQs, DMAs and I/O space resources of the Super I/O can flexibly adjust to
meet ISA PnP requirements, which suppport ACPI and APM (Advanced Power
Management).

1-14

Chapter 2: Installation

Chapter 2

Installation

This chapter covers the steps required to install the P3TDLR motherboard
into a chassis, connect the data and power cables and install add-on cards.
All motherboard jumpers and connections are also described. A layout and
quick reference chart are on pages 1-4 and 1-5. Remember to completely
close the chassis when you have finished working with the motherboard to
better cool and protect the system.

Tools Required

The only tools you will need to install the P3TDLR into the chassis are
a long and a short Philips screwdriver.

2-1 Handling the P3TDLR Motherboard

Static electrical discharge can damage electronic components. To prevent
damage to any printed circuit boards (PCBs), it is important to handle them
very carefully (see previous chapter). Also note that the size and weight
of the motherboard can cause it to bend if handled improperly, which may
result in damage. To prevent the motherboard from bending, keep one
hand under the center of the board to support it when handling. The fol­lowing measures are generally sufficient to protect your equipment from
static discharge.

Precautions

• Use a grounded wrist strap designed to prevent static discharge.

• Touch a grounded metal object before removing any board from its anti­static bag.

• Handle a board by its edges only; do not touch its components, periph­eral chips, memory modules or gold contacts.

• When handling chips or modules, avoid touching their pins.

• Put the motherboard, add-on cards and peripherals back into their anti­static bags when not in use.

2-1

SUPER P3TDLR User's Manual

• For grounding purposes, make sure your computer chassis provides ex­cellent conductivity between the power supply, the case, the mounting
fasteners and the motherboard.

Unpacking

The motherboard is shipped in antistatic packaging to avoid static electrical
damage. When unpacking the board, make sure the person handling it is
static protected.

2-2 Motherboard Installation

This section explains the first step of physically mounting the P3TDLR into
a chassis. Following the steps in the order given will eliminate the most
common problems encountered in such an installation. To remove the
motherboard, follow the procedure in reverse order.

1. Check compatibility of motherboard ports and I/O shield:

The P3TDLR requires a chassis big enough to support a 12" x 10"
motherboard, such as Supermicro's SC810 1U rackmount. Make sure
that the I/O ports on the motherboard properly align with their
respective holes in the I/O shield at the back of the chassis.

2. Mounting the motherboard onto the motherboard tray:

Carefully mount the motherboard to the motherboard tray by aligning
the board holes with the raised metal standoffs that are visible on
the bottom of the chassis. Insert screws into all the mounting holes
on your motherboard that line up with the standoffs and tighten until
snug (if you screw them in too tight, you might strip the threads).
Metal screws provide an electrical contact to the motherboard ground
to provide a continuous ground for the system.

2-2

Chapter 2: Installation

2-3 Connecting Cables

Now that the motherboard is installed, the next step is to connect the cables
to the board. These include the data (ribbon) cables for the peripherals and
control panel and the power cables.

Connecting Data Cables

The ribbon cables used to transfer data from the peripheral devices
have been carefully routed to prevent them from blocking the flow of
cooling air that moves through the system from front to back. If you
need to disconnect any of these cables, you should take care to
keep them routed as they were originally after reconnecting them
(make sure the red wires connect to the pin 1 locations). The
following data cables (with their locations noted) should be con­nected. (See the layout on page 5-10 for connector locations.)

l IDE Device Cables (J23 and J24)

l Floppy Drive Cable (J26)

l Ultra 160 LVD SCSI Connector (JA1)

l Control Panel Cable (JF1 Supplied with Supermicro Servers, see

next page)

Connecting Power Cables

The P3TDLR has a 24-pin primary power supply connector desig­nated "ATX Power" for connection to the ATX power supply. The
ATX Power connector also is keyed to accept 20-pin power connec­tors if the power supply you are using has that type. See Section 5­8 for power connector pin definitions.

2-3

SUPER P3TDLR User's Manual

Connecting the Control Panel

JF1 contains header pins for various front control panel connectors.
See Figure 5-1 for the pin locations of the various front control panel
buttons and LED indicators. Please note that even and odd numbered
pins are on opposite sides.

All JF1 wires have been bundled into a single ribbon cable to simplify
this connection. Make sure the red wire plugs into pin 1 as marked on
the board. The other end connects to JP4 of the Control Panel PCB
board, located just behind the system status LEDs on the chassis.
The control signals are all on the even numbered pins. See pages 5­12 to 5-14 for details and pin descriptions.

In addition to the 2-pin Power LED header on JF1, there is a 3-pin
header for the same function at JP61 on the motherboard, which is
located near JF1.

Figure 2-1. Control Panel Header Pins

JP61

2

JF1

Power LED (pins 1-3)

Power LED (pins 15-16)
HDD LED (pins 13-14)
NIC1 LED (pins 11-12)

NIC2 LED (pins 9-10)
Overheat LED (pins 7-8)
X (Key)
Reset Button (pins 3-4)
Power Button (pins 1-2)

1

2-4

Chapter 2: Installation

2-4 I/O Ports

The I/O ports are color coded in conformance with the PC 99 specification.
See Figure 2-2 below for the colors and locations of the various I/O ports.

Mouse

(Green)

LAN1

Keyboard

(Purple)

Note: The COM2 Port is a header on the motherboard, located next to the
mounting hole between the Super I/O chip and the RAGE XL chip.

USB

Ports

(Black)

COM1 Port

(Turquoise)

Figure 2-2. I/O Ports

VGA Graphics

Port (Blue)

2-5 Installing Processors

Avoid placing direct pressure to the top of the pro
cessor package. Always connect the power cord last

!

1. Installing the FCPGA processors:

The P3TDLR has two 370-pin sockets, which support single or dual Intel
Pentium® III FCPGA 500 MHz-1.26+ GHz processors and single or dual
low power Pentium® III processors at front bus speeds of 133 and 100
MHz. Lift the lever on the FCPGA socket and insert the processor (with
the heat sink attached) keeping the notched corner oriented toward pin
one on the socket. Make sure the processor is fully seated in the socket
and then close the lever. You can also install a single processor on the
motherboard without changing any jumper settings. (See Figure 5-4 for
views of a 370-pin FCPGA socket before and after processor installa­tion.)

and always remove it before adding, removing or
changing any hardware components.

LAN2

2-5

SUPER P3TDLR User's Manual

2. Attaching heat sinks to the processors:

Two passive heat sinks (one for each processor) have been included
with your SUPER P3TDLR. Secure a heat sink to each processor with a
suitable thermal compound to best conduct the heat from the processor to
the heat sink. Make sure that you apply the compound evenly and that
good contact is made between the CPU chip (the die) and the heat sink.
Insufficient contact or improper types of heat sinks and thermal com­pounds can cause the processor to overheat, which may crash the
system.

4. Removing the processors:

To remove the processors from the motherboard, simply follow the
installation process in reverse order.

Figure 2-3. FCPGA Socket: Empty and with Processor Installed

(low power Pentium III shown)

2-6

Chapter 2: Installation

2-6 Installing Memory

CAUTION! Exercise extreme care when install-

!

1. Memory support:

The P3TDLR supports 128/256/512 MB and 1 GB registered ECC SDRAM
DIMMs. PC133 and PC100 memory are both supported at their respective
speeds. However, the memory bus is synchronized to the front side bus
speed meaning you can not use PC100 with a 133 MHz FSB. Using
PC133 with a 100 MHz FSB will result in 100 MHz memory operation.

2. Memory Slots:

The P3TDLR has four DIMM slots. There is no need to install the DIMM
modules in pairs. The P3TDLR is not sensitive to the installed

position of the memory DIMMs in the DIMM slots.

3. Installing memory modules:

Insert each DIMM module parallel to its slot's guide rails. Pay attention to
the orientation of the two notches along the bottom of the module to
prevent inserting a DIMM module incorrectly. Gently press down on the
DIMM module until it snaps into place in the slot (see Figure 5-4).

ing or removing DIMM modules to prevent any
possible damage. The MEC must be populated
in the manner described in Step 2 below.

4. Memory Position:
The capacity of the memory modules can be mixed; however, the
memory speeds should all be the same for best results.

Figure 2-4. Side View of DIMM Installation into Slot

Notch

Release

Tab

To Install: Insert module vertically and press down until it snaps into
place. Pay attention to the bottom notches. T o Remove:
Use your thumbs to gently push each release tab outward to free the
DIMM from the slot.

DIMM

Note: Notch

should align

with the

receptive point

on the slot

Notch

Release

Tab

2-7

SUPER P3TDLR User's Manual

Figure 2-5. Side View of DIMM Installation into Slot

Top View of DIMM Slot

Release Tab

To Remove:

Use your thumbs to gently push each release tab outward.
This should release the DIMM from the slot.

Release Tab

2-8

2-7 Connector Definitions

Chapter 2: Installation

Power Supply Connectors

The primary power supply connec­tor on the P3TDLR is designated
as ATX POWER. This is a 24-pin
connector, which will also accept
20-pin power connectors, which
are used with some power sup­plies. If a 24-pin connector is
used, please refer to Table 2.1 for
pin definitions. If a 20-pin con­nector is used, please refer to
Table 2-2 for pin definitions.

ATX Power Supply 20-pin Connector

Pin Definitions (ATX PWR #1, ATX PW R #2)

Pin Number Definition
1 +3.3 V
2 +3.3 V
3 Ground
4 +5 V
5 Ground
6 +5 V
7 Ground
8 PW -O K
9 5V S B
10 +12V

Table 2-2

Pin Number Definition
11 3.3 V
12 -12 V
13 Ground
14 PS-ON
15 Ground
16 Ground
17 Ground
18 -5V
19 +5 V
20 +5 V

ATX Power Supply 24-pin Connector

Pin Number D efinition
1 +3 .3 V
2 +3 .3 V
3 Ground
4 +5 V
5 Ground
6 +5 V
7 Ground
8 P W R _ OK
9 5VSB
10 +12 V
11 +12 V
12 +3.3 V

Table 2-1

Pin De fin ition s (A TX POW E R )

Pin Number Definition
13 +3.3V
14 -12V
15 G round
16 PS_O N#
17 G round
18 G round
19 G round
20 Res
21 +5V
22 +5V
23 +5V
24 G round

Power Supply Fail
Enable/Disable

Header JP11 and jumper JP12 al­low you to enable or disable the
power supply fail annunciator
LEDs. The normal (default) posi­tion is closed to enable power fail
indications. See Table 2-3a and 2­3b for pin definitions.

2-9

Table 2-3a

Power Fail Header Pin

Definitio ns

(JP11)

Pin

Number

Defin i tio n

P/S 1 Fail Signal

1

P/S 2 Fail Signal

2

P/S 3 Fail Signal

3
4

Rese t (from M B )

Table 2-3b

On b o a rd VGA E n a b le /D is a ble

Jumper Settings (JP12)

Jumper

Position

Closed

Open

Defin i tio n

Enabled

Disabled

SUPER P3TDLR User's Manual

Power LED

The Power LED connection is lo­cated on pins 15 and 16 of JF1.
When illuminated, this LED indi­cates that power is applied to the
system. There is also a 3-pin
header for the Power LED located
at JP61. See Tables 2-4a and 2­4b for pin definitions and Figure 2­2 for pin locations.

HDD LED

The Hard Disk Drive LED connec­tion is located on pins 13 and 14
of JF1. This provides an indica­tion of IDE disk activity on the con­trol panel. See Table 2-5 for pin
definitions and Figure 2-2 for pin
locations.

NIC1 LED

The Network Interface Controller 1
LED connection is located on pins
11 and 12 of JF1. This header is
used to indicate network activity
on LAN (Ethernet) port 1. See
Table 2-6 for pin definitions and
Figure 2-2 for pin locations.

Table 2-4a

Overheat LED

Pin Definitions

(JF1 )

Pin

Number

Definition
15
16

+

-

IDE Hard Disk Drive LED

Number

Number

Table 2-4b

PWR_LED Pin

Definitio ns (JF 6 1 )

Pin

Number

1
2
3

Table 2-5

Pin Defin itio ns

(JF1 )

Pin

Defin i tio n

13
14

Pin Definitions

Pin

11
12

Table 2-6

NIC1 LED

(JF1 )

Definition

+

-

+

-

Defin i tio n

GND

+5V
Key

NIC2 LED

The Network Interface Controller 2
LED connection is located on pins
9 and 10 of JF1. This header is
used to indicate network activity
on LAN (Ethernet) port 2. See
Table 2-7 for pin definitions and
Figure 2-2 for pin locations.

2-10

Table 2-7

NIC2

Pin Definitions

(JF1 )

Pin

Number

Defin i tio n

9

10

+

-

Chapter 2: Installation

Overheat LED

Pins 7 and 8 of JF1 are for the
Overheat LED, which provides you
with advanced warning of chas­sis overheating. This LED will also
illuminate if the blower fan fails,
which will cause the chassis tem­perature to rise. Refer to Table 2­8 for pin definitions and Figure 2-2
for pin locations.

Reset

The Reset connection is located
on pins 3 and 4 of JF1. This con­nector attaches to the Reset but­ton on the control panel, which al­lows you to reboot the system.
See Table 2-9 for pin definitions
and Figure 2-2 for pin locations.

Table 2-8

Overheat LED

Pin Definitions

(JF1 )

Pin

Number

Defin i tio n
7
8

Table 2-9

Reset Button

Pin Definitions

(JF1 )

Pin

Number

Defin i tio n
3
4

Ground

+

-

Reset

PWR_ON

The PWR_ON connection is lo­cated on pins 1 and 2 of JF1. This
connector attaches to the Power
button on the control panel, which
allows you to turn the power to
the system on and off. The user
can also configure this button to
function as a suspend button.
(See the Power Button Mode set­ting in BIOS.) To turn off the
power when set to suspend mode,
hold down the power button for at
least 4 seconds. See Table 2-10
for pin definitions and Figure 2-1
for pin locations.

2-11

Table 2-10

PWR Button

Pin Definitions

(JF1 )

Pin

Number

Defin i tio n

1

PW_O N

2

Ground

SUPER P3TDLR User's Manual

Fan Headers*

There are several fan headers on
the P3TDLR that provide cooling
for various components. In addi­tion to one fan header for each
processor, there are two over­heat and two chassis fan head­ers. If used, a blower fan should
be connected to the chassis fan
header located near the JF1
header. See the motherboard lay­out on page 2-9 for locations.
Refer to Table 2-11 for pin defini­tions. Note: The maximum current limita-

tion for the onboard fans is 0.6 amps for each,
not to exceed 1.25 amps for any two fans. I.e.
both CPU fans, both chassis fans or both over­heat fans.

Serial Ports

Two connectors, for the COM1
and COM2 serial ports,are
located on the P3TDLR board
(see Figure 2-8). COM1 is
located near USB1 connectors.
COM 2 is located near the
AMIBIOS (U33). See the mother­board layout on page 2-9 for
locations. See Table 2-12 for pin
definitions.

Table 2-11

Fan Header Pin Definitions

(CPU, CHASSIS and OH FANs)

Pin

Number

1
2
3

* C aution: These fan headers

are DC power.

Table 2-12

Serial Port Pin Definitions

(CO M 1 , C O M 2 )

Pin Number Definition
1 CD
2 R X D
3 TXD
4 DTR
5 Ground

Defin i tio n

Ground (black)

+12V (red)

Tachometer

Pin Number Definition
6 DSR
7 RT S
8 CT S
9 ARI

2-12

Chapter 2: Installation

ATX PS/2 Keyboard and
PS/2 Mouse Ports

The ATX PS/2 keyboard and the
PS/2 mouse are located on J28.
See Table 2-13 for pin definitions.
(The mouse port is above the key­board port. See Figure 2-12.)

Universal Serial Bus (USB)

Two Universal Serial Bus connec­tors are located on U38. USB1 is
the bottom connector and USB2 is
the top connector. Refer to Table
2-14 for pin definitions.

Extra USB Connectors
(J105/J106)

J105 is USB3, and J106 is USB4.
You will need a USB cable (not in­cluded) to use this connection. Re­fer to Table 2-14 for pin definitions.

LAN1/LAN2 Ports

Table 2-13

PS/2 Keyboard

and Mouse Port

Pin Definitions

(J28)

Pin

Defin i tio n

Number

Data

1

NC

2

Ground

3

VCC

4

Clock

5
6

NC

USB1

Table 2-14

Pin
Number Definition
1+5V
2P0­ 3P0+
4 Ground
5Key

Universal Serial Bus Pin Definitions

Pin
Number Definition
1+5V
2P0­ 3P0+
4 Ground
5 N/A

USB2

Two Ethernet ports (designated
NIC1 and NIC2) are located beside
the VGA port on the I/O backplane.
These ports accept RJ45 type
cables. There are two jumpers for
the LAN1/LAN2 ports: JP8: NIC 1
Enable/Disable(Open: enable),
JP24: NIC2 Enable/Disable (Open:
enable). Each indicate a success­ful connection (yellow) and activ­ity (green).

SLED1 (SCSI LED) Indicator

The SLED connector is used to pro­vide an LED indication of SCSI ac­tivity. Refer to Table 2-15 for con­necting the SCSI LED.

2-13

RJ45 Ethernet Port

Table 2-15

SLED1 (SCSI LED) Pin

Definitio ns

Pin

Number

1
2
3
4

Defin i tio n

+

-

-

+

SUPER P3TDLR User's Manual

Wake-On-Modem

The Wake-on-Modem (WOM)
header allows your computer to
receive and be "awakened" by an
incoming call when in the suspend
state. Refer to Table 2-16 for pin
definitions. You must also have a
WOM card and cable to use WOM.

Wake-On-LAN

The Wake-On-LAN (WOL) header
allows the system to be woken up
upon receiving an appropriate sig­nal via the LAN. You must enable
the LAN Wake-Up setting in BIOS
to use this feature and have a
LAN card with a Wake-on-LAN
connector and cable. Refer to
Table 2-17 for pin definitions.

Table 2-16

Wake-on-modem Pin

Definitio ns (W O M)

Pin

Number

Number

Defin i tio n

1

Ground

2

Wake-up

Table 2-17
Wake-On-LAN Pin
Definitio ns (W O L)

Pin

Defin i tio n

1

+5V Standby

Ground

2

Wake-up

3

2-8 DIP Switch Settings

DIP Switch 1:
Core/Bus Ratio

One DIP switch labeled SW1 is lo­cated on the P3TDLR motherboard.
The switch housing has four indi­vidual switches. They are used to
set the CPU core/bus ratio. The
table on the right will show you
how to choose the proper CPU
core/bus ratio. After determining
the ratio, refer to Table 2-18 for
the correct settings of DIP switch

1.

2-14

Table 2-18

CP U Core /B u s R a t io S e le c t io n

(DIP S witch 1 )

133/100

CPU

600/450
667/500
733/550
800/600
866/650
933/700

1G/750

1.06G/800

1.13G/850

1.20G/900

1.26G/950

1.4G/1G

Core/bus ratio = CPU speed / front side bus
speed. Example: a 550 MHz CPU running at a
100 MHz FSB speed:
550 (MHz) / 100 (MHz) = 5.5 (ratio)

SW1

#1

ON

ON ON

ON

ON
ON

SW1

#2

ON

ON

ON

ON

SW1

#3

ON

ON
ON
ON

ON
ON
ON

SW1

#4
ON
ON
ON

ON
ON
ON
ONONON

2-9 Jumper Settings

Chapter 2: Installation

Explanation of
Jumpers

To modify the operation of the
motherboard, jumpers can be used
to choose between optional set­tings. Jumpers create shorts be­tween two pins to change the
function of the connector. Pin 1 is
identified with a square solder pad
on the printed circuit board. See
the motherboard layout pages for
jumper locations.

Note: Closed refers to the jumper being set
over both pins on a two-pin jumper header.
Open refers to the jumper being set over a
single pin of a two-pin jumper.

Front Side Bus Speed

JP2 sets the FSB speed. CPU
speed = FSB x Core/Bus ratio.
Core/Bus Ratio settings are de­scribed in Section 2-9. See Table
2-19 for jumper settings.

Connector

Pins

Jumper

Cap

Setting

3 2 1

3 2 1

Pin 1-2 short

Table 2-19

Front Side Bus Speed

Jumper Settings (JP2)

Jumper

Position

1-2
2-3

Open

* Note: The Auto setting allows

the CPU to set the speed.

Definition

Auto
100 MHz
133 MHz

PCI 64 Speed Setting

JP13 sets the speed PCI 64. When
JP13 is set to "open", the PCI
speed is set 66MHz, and when the
JP13 is closed, the PCI speed is
set to 33 MHz. See Table 2-20 for
jumper settings.

2-15

Table 2-20

PCI 64 Speed Setting

Jumper Settings (JP13)

Jumper

Position

Open

Closed

Definition

66 MHz
33 MHz

SUPER P3TDLR User's Manual

CMOS Clear

Refer to Table 2-21 for setting
JBT1 to clear CMOS. Always re­move the AC power cord from the
system before clearing CMOS.

Over Heat Alarm

Jumper JP7 allows you to enable
or disable the over heat alarm.
Refer to Table 2-22 for jumper set­tings.

LAN 1 Enable/Disable

Use jumper JP8 to enable or disable
the onboard LAN 1 (Ethernet) port.
The default setting is enabled. See
Table 2-23 for jumper settings.

Table 2-21

CMOS Clear Jumper Settings

Jumper

Position

(JBT1)

Definition
1-2
2-3

Jumper Settings (JP7)

Jumper

Position

Open

Closed

LAN 1 Enable/Disable

Jumper Settings (JP8)

Jumper

Position

Open

Closed

Normal

CMOS Clear

Table 2-22

Over Heat Alarm

Defin ition

Disabled

Enabled

Table 2-23

Definition

Enabled

Disabled

LAN 2 Enable/Disable

Use jumper JP24 to enable or disable
the onboard LAN 2 (Ethernet) port.
The default setting is enabled. See
Table 2-24 for jumper settings.

2-16

Table 2-24

LAN 2 Enable/Disable

Jumper Settings (JP24)

Jumper

Position

Open

Closed

Definition

Enabled

Disabled

Chapter 2: Installation

SCSI Enable/Disable

Jumper JP1 allows you to enable
or disable all onboard SCSI. The
normal (default) position is open to
enable SCSI operation. See Table
2-25 for jumper settings.

Onboard VGA
Enable/Disable

Jumper JP62 allows you to enable
or disable the onboard VGA. The
normal (default) position is open to
enable VGA operation. See Table
2-26 for jumper settings.

Watchdog Reset
Enable/Disable

Jumper JP210 allows you to en­able or disable the Watchdog func­tion. The normal (default) position
is open to disable Watchdog. See
Table 2-27 for jumper settings.

Table 2-25

SC S I E nable /D is a b le

Jumper Settings (JP1)

Jumper
Position

Pin 1-2
Pin 2-3

On b o a rd VGA E n a b le /D is a ble

Jumper Settings (JP62)

Jumper

Position

Closed

Watchdog Reset Enable/Disable

Jumper Settings (JP62)

Jumper
Position

Closed

Open

Open

Table 2-27

Definition

Enabled
Disabled

Table 2-26

Definition

Enabled

Disabled

Definition

Enabled
Disabled

2-17

SUPER P3TDLR User's Manual

2-10 Floppy/Hard Disk and SCSI Connections

Be aware of the following when connecting the floppy and hard disk drive
cables:

• A red mark on a wire typically designates the location of pin 1.

• A single floppy disk drive ribbon cable has 34 wires and two connectors
to provide for two floppy disk drives. The connector with the twisted
wires always connects to drive A, and the connector that does not have
twisted wires always connects to drive B.

Floppy Connector

The floppy connector is located
on J26 and requires a 34-pin rib­bon cable for operation. See
Table 2-28 for pin definitions.

Table 2-29

IDE Connector Pin Definitions

Pin Number Function
1 Res e t ID E
3 H o s t D a ta 7
5 H o s t D a ta 6
7 H o s t D a ta 5
9 H o s t D a ta 4
11 Host D a ta 3
13 Host D a ta 2
15 Host D a ta 1
17 Host D a ta 0
19 GN D
21 DRQ3
23 I/O W ri te ­ 25 I/O Read­ 27 IOCHRDY
29 DACK3­ 31 IR Q 1 4
33 Add r 1
35 Add r 0
37 Chip S e l e ct 0
39 A c tiv ity

(J23, J24)

Pin Number Function
2 GND
4 Ho st Data 8
6 Ho st Data 9
8 Hos t D a ta 1 0
10 Host D a ta 1 1
12 Host D a ta 1 2
14 Host D a ta 1 3
16 Host D a ta 1 4
18 Host D a ta 1 5
20 Key
22 GND
24 GND
26 GND
28 BA L E
30 GND
32 IOCS16 ­ 34 GND
36 Addr 2
38 C h ip S e le c t 1 ­ 40 GND

Floppy Connector Pin Definitions (J26)

Pin Number Function
1 GND
3 GND
5 K e y
7 GND
9 GND
11 GND
13 GND
15 GND
17 GND
19 GND
21 GND
23 GND
25 GND
27 GND
29 GND
31 GND
33 GND

Table 2-28

Pin Number Function
2 FDHDIN
4 Re s e rv ed
6 FDE D IN
8 Index­ 10 Motor Enable
12 Dr iv e S e le c t B ­ 14 Dr iv e S e le c t A ­ 16 Motor Enable
18 DIR ­ 20 STEP ­ 22 Write D a ta ­ 24 Write Gate ­ 26 Track 00­ 28 Write Protect­ 30 Read Data­ 32 Side 1 Select­ 34 Diske tte

IDE Connectors

There are no jumpers to config­ure the onboard IDE connectors
J23 and J24. Refer to Table 2­29 for pin definitions.

2-18

Ultra160 SCSI
Connector

Refer to Table 2-30 for
pin definitions for the
Ultra160 SCSI connector
located at JA1.

Connector

Contact
Number

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

Chapter 2: Installation

+DB(0)
+DB(1)
+DB(2)
+DB(3)
+DB(4)
+DB(5)
+DB(6)
+DB(7)
+DB(P)

+ATN

+BSY

+ACK

+RST

+MSG

+SEL
+C/D

+REQ

+I/O
+DB(8)
+DB(9)

Table 2-30

Connector

Contact
Number

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

Signal Names

68-pin Ultra160 SCSI Connectors (JA1)

Signal Names

+DB(12)
+DB(13)
+DB(14)
+DB(15)
+DB(P1)

GROUND

DIFFSENS
TERMPWR
TERMPWR

RESERVED

GROUND

GROUND

+DB(10)
+DB(11)

-DB(12)

-DB(13)

-DB(14)

-DB(15)

-DB(P1)

-DB(0)

-DB(1)

-DB(2)

-DB(3)

-DB(4)

-DB(5)

-DB(6)

-DB(7)

-DB(P)
GROUND
GROUND

TERMPWR
TERMPWR

RESERVED

GROUND

-ATN

GROUND

-BSY

-ACK

-RST

-MSG

-SEL

-C/D

-REQ

-I/O

-DB(8)

-DB(9)

-DB(10)

-DB(11)

2-19

SUPER P3TDLR User's Manual

2-11 Installing Software Drivers

After the OS (Operating System) has been installed, you must install the
software drivers. The necessary drivers are all included on the Supermicro
CD that came packaged with your motherboard. After inserting this CD into
your CDROM drive, the display shown in Figure 2-6 should appear. (If this
display does not appear, click on the My Computer icon and then on the icon
representing your CDROM drive. Finally, double click on the S "Setup" icon.)

Figure 2-6. Driver/Tool Installation Display Screen

Click the icons showing a hand writing on paper to view the readme files
for each item. The bottom icon with a CD on it allows you to view the
entire contents of the CD.
Video driver (ATI)
Build Netword Card disk
Build SCA disk (QLogic GEM 354): For integration with the SuperServer
SC850 and SC860 chassis.
Build SCSI disk (Ultra160)

2-20

Chapter 3: Troubleshooting

Chapter 3

Troubleshooting

3-1 Troubleshooting Procedures

Use the following procedures to troubleshoot your system. If you have
followed all of the procedures below and still need assistance, refer to the
‘Technical Support Procedures’ and/or ‘Returning Merchandise for Service’
section(s) in this chapter.

Note: Always disconnect the power cord before adding, changing
or installing any hardware components.

Before Power On

1. Make sure no short circuits exist between the motherboard and
chassis.

2. Disconnect all ribbon/wire cables from the motherboard, including those
for the keyboard and mouse.

3. Remove all add-on cards.

4. Install one CPU (making sure it is fully seated) and connect the chassis
speaker and the power LED to the motherboard. (Check all jumper
settings as well.)

Troubleshooting

No Power

1. Make sure no short circuits exist between the motherboard and the
chassis.

2. Verify that all jumpers are set to their default positions.

3. Check that the 115V/230V switch on the power supply is properly set.

4. Turn the power switch on and off to test the system.

5. The battery on your motherboard may be old. Check to verify that it
still supplies ~3VDC. If it does not, replace it with a new one.

No Video

1. If the power is on but you have no video, remove all the add-on cards
and cables.

2. Use the speaker to determine if any beep codes exist. Refer to
Appendix A for details on beep codes.

3-1

SUPER P3TDLR User's Manual

NOTE

If you are a system integrator, VAR or OEM, a POST
diagnostics card is recommended. For I/O port 80h codes,
refer to App. B.

Memory Errors

1. Make sure the DIMM modules are properly and fully installed.

2. Determine if different speeds of DIMMs have been installed and verify
that the BIOS setup is configured for the fastest speed of RAM used.
It is recommended to use the same RAM speed for all DIMMs in the
system.

Troubleshooting

3. Make sure you are using PC133 or PC100 compliant, registered ECC
SDRAM. EDO and unbuffered SDRAM are not supported.

4. Check for bad DIMM modules or slots by swapping a single module
between two slots and noting the results.

5. Make sure all memory modules are fully seated in their slots.

6. Check the power supply voltage 115V/230V switch.

Losing the System’s Setup Configuration

1. Check the setting of jumper JBT1. Ensure that you are using a high
quality power supply. A poor quality power supply may cause the
system to lose the CMOS setup information. Refer to page 1-13 for
details on recommended power supplies.

2. The battery on your motherboard may be old. Check to verify that it
still supplies ~3VDC. If it does not, replace it with a new one.

3. If the above steps do not fix the Setup Configuration problem, contact
your vendor for repairs.

3-2 Technical Support Procedures

Before contacting Technical Support, please take the following steps. Also,
note that as a motherboard manufacturer, Super Micro does not sell directly
to end-users, so it is best to first check with your distributor or reseller for
troubleshooting services. They should know of any possible problem(s)
with the specific system configuration that was sold to you.

1. Please go through the ‘Troubleshooting Procedures’ and 'Frequently
Asked Question' (FAQ) sections in this chapter or see the FAQs on our

3-2

Chapter 3: Troubleshooting

web site < http://www.supermicro.com/techsupport.htm > before con­tacting Technical Support.

2. BIOS upgrades can be downloaded from our web site at
< http://www.supermicro.com/techsupport/download.htm >.

Note: Not all BIOS can be flashed depending on the modifica­tions to the boot block code.

3. If you still cannot resolve the problem, include the following information
when contacting Super Micro for technical support:

•Motherboard model and PCB revision number

•BIOS release date/version
(this can be seen on the initial display when your system first boots up)

•System configuration
An example of a Technical Support form is on our web site at
http://www.supermicro.com/techsupport/contact_support.htm.

4. Distributors: For immediate assistance, please have your account number
ready when placing a call to our technical support department. We can be
reached by e-mail at < [email protected] > or by fax at (408)
503-8019.

Troubleshooting

3-3 Frequently Asked Questions

Question: What are the various types of memory that the SUPER
P3TDLR motherboard can support?

Answer: The SUPER P3TDLR has four DIMM slots that support 168-pin,

registered DIMMs with ECC only. Note that since the motherboard has a 133
MHz memory bus, both PC133 and PC100 memory are fully supported. How­ever, since the memory bus is synchronized to the front side bus speed,
you cannot use PC100 with a 133 MHz FSB. Also, using PC133 with a 100
MHz FSB will result in 100 MHz memory speed operation. Note: Unbuf-
fered SDRAM and non-ECC memory are not supported.

Question: How do I update my BIOS?

Answer: It is recommended that you do not upgrade your BIOS if you are

experiencing no problems with your system. Updated BIOS files are located
on our web site at http://www.supermicro.com. Please check our BIOS
warning message and the info on how to update your BIOS on our web
site. Also, check the current BIOS revision and make sure it is newer than

3-3

SUPER P3TDLR User's Manual

your BIOS before downloading. Select your motherboard model and down­load the BIOS file to your computer. Unzip the BIOS update file and you will
find the readme.txt (flash instructions), the flash.com (BIOS flash utility) and
the BIOS image (xxxxxx.rom) files. Copy these files onto a bootable floppy
and reboot your system. It is not necessary to set BIOS boot block protec­tion jumpers on the motherboard. At the DOS prompt, enter the command
"flash." This will start the flash utility and give you an opportunity to save
your current BIOS image. Flash the boot block and enter the name of the
update BIOS image file.

Note: It is important to save your current BIOS and rename it
"super.rom" in case you need to recover from a failed BIOS update.

Select flash boot block, then enter the update BIOS image. Select "Y" to
start the BIOS flash procedure and do not disturb your system until the
flash utility displays that the procedure is complete. After updating your

Troubleshooting

BIOS, please clear the CMOS then load Optimal Values in the BIOS.

Question: After flashing the BIOS my system does not have video.
How can I correct this?

Answer: If the system does not have video after flashing your new BIOS, it

indicates that the flashing procedure failed. To remedy this, first clear CMOS per
the instructions in this manual and retry the BIOS flashing procedure. If you still
do not have video, please use the following BIOS Recovery Procedure.
First, make sure jumper JPWAKE is set to pins 1-2. Then, turn your system
off and place the floppy disk with the saved BIOS image file (see above
FAQ) in drive A. Press and hold <CTRL> and <Home> at the same time,
then turn on the power with these keys pressed until your floppy drive
starts reading. Your screen will remain blank until the BIOS program is
done. If the system reboots correctly, then the recovery was successful.
The BIOS Recovery Procedure will not update the boot block in your BIOS.

Question: Do I need the CD that came with your motherboard?

Answer: The supplied compact disc has quite a few drivers and programs

that will greatly enhance your system. We recommend that you review the
CD and install the applications you need. Applications on the CD include
chipset drivers for Windows and security and audio drivers.

Question: Why can't I turn off the power using the momentary
power on/off switch?

Answer: The instant power off function is controlled in BIOS by the Power

Button Mode setting. When the On/Off feature is enabled, the motherboard

3-4

Chapter 3: Troubleshooting

will have instant off capabilities as long as the BIOS has control of the
system. When the Standby or Suspend feature is enabled or when the
BIOS is not in control such as during memory count (the first screen that
appears when the system is turned on), the momentary on/off switch must
be held for more than four seconds to shut down the system. This feature
is required to implement the ACPI features on the motherboard.

3-4 Returning Merchandise for Service

A receipt or copy of your invoice marked with the date of purchase is
required before any warranty service will be rendered. You can obtain
service by calling your vendor for a Returned Merchandise Authorization
(RMA) number. When returning to the manufacturer, the RMA number
should be prominently displayed on the outside of the shipping carton, and
mailed prepaid or hand-carried. Shipping and handling charges will be ap­plied for all orders that must be mailed when service is complete.

This warranty only covers normal consumer use and does not cover dam­ages incurred in shipping or from failure due to the alteration, misuse, abuse
or improper maintenance of products.

During the warranty period, contact your distributor first for any product
problems.

Troubleshooting

3-5

SUPER P3TDLR User's Manual

Troubleshooting

NOTES

3-6

Chapter 7: BIOS/Setup

Chapter 4

BIOS

4-1 Introduction

This chapter describes the AMIBIOS for the SUPER P3TDLR. The AMI
ROM BIOS is stored in a Flash EEPROM and can be easily upgraded using
a floppy disk-based application.

Note: Due to periodic changes to the BIOS, some settings may have been
added or deleted and might not yet be recorded in this manual. Refer to the
Manual Download area of our web site for any changes to BIOS that are
not reflected in this manual.

System BIOS

The BIOS is the Basic Input Output System used in all IBM® PC, XT™, AT®,
and PS/2® compatible computers. The BIOS ROM stores the system param­eters, such as amount of memory, type of disk drives and video displays,
etc. BIOS ROM requires very little power. When the computer is turned off,
a back-up battery provides power to the BIOS ROM, enabling it to retain the
system parameters. Each time the computer is powered-on, the computer is
then configured with the values stored in the BIOS ROM by the system
BIOS, which gains control when the computer is powered on.

BIOS

How To Change the Configuration Data

The configuration data that determines the system parameters may be
changed by entering the BIOS Setup utility. This Setup utility can be ac­cessed by pressing <Delete> at the appropriate time during system boot.

Starting the Setup Utility

Normally, the only visible POST (Power On Self Test) routine is the memory
test. As the memory is being tested, press the <Delete> key to enter the
main menu of the BIOS Setup utility. From the main menu, you can access
the other setup screens, such as the Chipset and Power menus. Section 4­3 gives detailed descriptions of each parameter setting in the Setup utility.

An AMIBIOS identification string is displayed at the left bottom corner of the
screen, below the copyright message.

4-1

SUPER P3TDLR User's Manual

4-2 BIOS Features

• Supports Plug and Play V1.0A and DMI 2.1

• Supports Intel PCI (Peripheral Component Interconnect) (PME) local bus
specification

• Supports Advanced Power Management (APM) specification v 1.1

• Supports ACPI

• Supports Flash ROM

AMIBIOS supports the LS120 drive made by Matsushita-Kotobuki Electronics
Industries Ltd. The LS120:

• Can be used as a boot device

• Is accessible as the next available floppy drive

AMIBIOS supports PC Health Monitoring chips. When a failure occurs in a
monitored activity, AMIBIOS can sound an alarm and display a message.
The PC Health Monitoring chips monitor:

BIOS

• CPU temperature

• Additional temperature sensors

• Chassis intrusion detector

• Five positive voltage inputs

• Two negative voltage inputs

• Three fan speed monitor inputs

4-3 Running Setup

*Optimal default settings are in bold text unless otherwise noted.

The BIOS setup options described in this section are selected by choos­ing the appropriate text from the Standard Setup screen. All displayed
text is described in this section, although the screen display is often all
you need to understand how to set the options (see on next page).

4-2

Chapter 7: BIOS/Setup

The Main BIOS Setup Menu

Press the <Delete> key during the POST (Power On Self Test) to enter the Main
Menu of the BIOS Setup Utility. All Main Setup options are described in this
section. The Main BIOS Setup screen is displayed below.

BIOS SETUP UTILITY

Main Advanced Chipset PCIPnP Power Boot Security Exit

AMIBIOS Version : 07.00xx
BIOS Build Date : xx/xx/xx
BIOS ID : SSM70626

Processor Type : PentiumIII™
Processor Speed : 933MHz

System Memory : 256MB

System Time [10:10:00]
System Date [Thu 08/24/00]

V02.03 (C)Copyright 1985-2000, American Megatrends, Inc.

Select Screen

↔

Select Item

↑↓

+- Change Field
Tab Select Field
F1 General Help
F10 Save and Exit
ESC Exit

BIOS

Use the <Up/Down> arrow keys or the <Tab> key to move between the
different settings in the above menu.

When the items "System Time", and "System Date" are highlighted, type in the
correct time/date in the time field, and then press <Enter>. The date must be
entered in MM/DD/YY format. The time is entered in HH:MM:SS format. The time
is in also 24-hour format. For example, 5:30 a.m. appears as 05:30:00 and 5:30
p.m. as 17:30:00.

Press the <ESC> key to exit the Main Menu and use the <Left/Right> arrow
keys to enter the other categories of BIOS settings. The next section is
describs in detail how to navigate through the menus.

*Note: Items displayed in gray are preset and cannot be selected.
Items with a blue arrow are commands, not options (i.e., Discard
Changes).

4-3

SUPER P3TDLR User's Manual

4-4 Advanced BIOS Setup

Choose "Advanced BIOS Setup" from the AMIBIOS Setup Utility main menu with
the <Left/Right> arrow keys. You should see the following display. Select one
of the items in the left frame of the screen, such as SuperIO Configuration, to
go to the sub screen for that item. Advanced BIOS Setup options are displayed
by highlighting the option using the arrow keys. All Advanced BIOS Setup
options are described in this section.

BIOS SETUP UTILITY

Main Advanced Chipset PCIPnP Power Boot Security

BIOS

Exit

Setup Warning
Setting items on this screen to incorrect
values may cause the system to malfunction!

> SuperIO Configuration
> IDE Configuration
> Floppy Configuration
> Boot Settings Configuration
> Event Log Configuration

Peripheral Device Configuration

>

Processor Configuration

>

> System Health Monitoring Hardware

V02.03 (C)Copyright 1985-2000, American Megatrends, Inc.

Configure SuperIO
Chipset Winbond627F

Select Screen

↔

Select Item

↑↓

Enter Go to Sub Screen
F1 General Help
F10 Save and Exit ESC
Exit

Use the <Up/Down> arrow keys to select the "Super I/O Configuration" line.
When the "Super IO Configuration" line is highlighted, Press <ENTER> to display

its menu.
The following Super IO Configuration screen will appear. Here you can select

your options for your computer's I/O (Input/Output) devices.

4-4

Super IO Configuration

BIOS SETUP UTILITY

Advanced

Configure Nat 317 Serial Port(s)and Parallel P

Serial Port1 Address
Serial Port1 IRQ
Serial Port2 Address
Serial Port2 IRQ
Parallel Port Address
Parallel Port IRQ
Parallel Port Mode
ECP Mode DMA Channel

V02.03 (C)Copyright 1985-2000, American Megatrends, Inc.

[3F8]
[4]
[2F8]
[3]
[378]
[7]
[ECP]
[3]

The Super IO Configuration includes the following items:

Chapter 7: BIOS/Setup

Select Screen

↔

Select Item

↑↓

+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit

Serial Port 1 Address

This option specifies the base I/O port address of serial port 1. The set­tings for this item include Disabled, 3F8 and 3E8 and 2E8. Select the de­sired setting and then press <Enter>.

Serial Port 1 IRQ

This option specifies the Interrupt Request address of serial port 1. The
settings for this item include Disabled, 4 and 3. Select the desired setting
and then press <Enter>.

Serial Port 2 Address

This option specifies the base I/O port address of serial port 2. The settings
for this item include Disabled, 2F8, 3E8 and 2E8. Select the desired setting
and then press <Enter>.

4-5

BIOS

SUPER P3TDLR User's Manual

Serial Port 2 IRQ

This option specifies the Interrupt Request address of serial port 2. The
settings for this item include Disabled, 4 and 3. Select the desired setting
and then press <Enter>.

Parallel Port Address

This option specifies the I/O address used by the parallel port. The settings
for this item include Disabled, 378, 278 and 3BC. Select your setting and
then press "Enter".

Parallel Port IRQ

This option allows the user to set the Parallel Port IRQ. The settings
for this item include 5 and 7.

Parallel Port Mode

This option specifies the parallel port mode. The settings for this item
include Normal, Bi-directional, EPP and ECP.

BIOS

ECP Mode DMA Channel

This option allows the user to set the setting for the ECP
Mode of the DMA Channel. The settings for this item include

0, 1 and 3.

IDE Configuration

Onboard PCI IDE Controller

This option allows the user to enable or disable the integrated IDE Control­ler. The settings include Disabled and Both. Select "Disabled" to disable
the Integrated IDE Controller. Select "Both" to enable both Primary and Sec­ondary IDE Controllers.

4-6

Chapter 7: BIOS/Setup

Primary IDE Master

When entering "Setup", BIOS automatically detects the presence of
IDE devices. This displays the auto detection status of the IDE de
vices. You can also manually configure the IDE drives by providing the
following information:

This option allows the user to configure the IDE devices. When the desired
item is highlighted (selected), press <Enter> and the following screen will
be displayed:

Type

This option sets the type of device that the AMIBIOS attempts
to boot from after AMIBIOS POST is completed. The settings
include Not installed, Auto, CDROM and ARMD. The "Auto"
setting allows BIOS to automatically detect the presence of
the IDE controller.

LBA/Large Mode

LBA (Logical Block Addressing) is a method of addressing
data on a disk drive. In LBA mode, the maximum drive capac
ity is 137 GB. The settings are Disabled and Auto. Select
"Disabled" to disable LBA mode. Select "Auto" to enable LBA
mode if your device supports it and is not already formatted
with the LBA mode.

BIOS

Block (Multi-Sector Transfer) Mode

This option sets the block mode multi sector transfers option
The settings include Disabled and Auto. Disabled: This op
tion prevents the BIOS from using Multi-Sector Transfer on
the specified channel. The data to and from the device will
occur one sector at a time. Auto: This option allows the
BIOS to auto detect device support for Multi-Sector Trans
fers on the specified channel. If supported, this option al
lows the BIOS to auto detect the number of sectors per block
for transfer from the hard disk drive to memory. The data
transfer to and from the device will occur multiple sectors at
a time (if the device supports it).

4-7

SUPER P3TDLR User's Manual

PIO Mode

IDE PIO (Programmable I/O) mode programs timing cycles be
tween the IDE drive and the programmable IDE controller. As
the PIO mode increases, the cycle time decreases. The
settings are: Auto, 0, 1, 2, 3 and 4.

DMA Mode

This item allows the users to select the DMA mode. The
settings are: Auto, SWDMA0, SWDMA1, SWDMA2,
MWDMA0, MWDMA1, MWDM2, UWDMA0, UWDMA1,
UWDMA2, UWDMA3 and UWDMA4. Select Auto to auto de­tect the DMA Mode. Select SWDMA0 through SWDMA2 to
set single word DMA0 through DMA2. Select MWDMA0
through MWDMA2 to set Multi-word DMA0 through DMA2.
Select UDMA0 trhough UDMA4 to set Ultra DMA0 through
Ultra DMA4.

S.M.A.R.T.

BIOS

S.M.A.R.T stands for Self-Monitoring Analysis and Reporting
Technology, a feature that can help predict impending drive
failures. The settings are Auto, Disabled and Enabled.
Select "Enabled" or "Disabled" to enable or disable the
S.M.A.R.T. Select "Auto" to auto detect S.M.A.R.T.

32Bit Data Transfer

The settings are Disabled, and Enabled. Select "En­abled" or "Disabled" to enable or disable the 32-bit Data
Transfer function.

ARMD Emulation Type

This option is used to select the emulation used when config
uring an LS120, MO (Magneto-Optical), or Iomega Zip drive.
The settings are Auto, Floppy and HardDisk.

4-8

Chapter 7: BIOS/Setup

Primary IDE Slave

When the system enters "Setup", BIOS automatically detects the presence
of IDE devices. This option displays the auto detection status of IDE de­vices. The settings for "Primary IDE Slave" are the same as those for the
"Primary IDE Master". The default setting for this option is ATAPI

CDROM.Secondary IDE Master

Secondary IDE Slave

This displays the status of auto detection of IDE devices. The settings for
"Secondary IDE Slave" are the same as those for the "Primary IDE Master".
The default setting for this option is Not Detected.

Hard Disk Write Protect

This item allows the user to prevent the hard disk from being overwritten.
The options are Enabled or Disabled. Enabled allows the drive to be used
normally; read, write and erase functions can all be performed. Disabled
prevents the hard disk from being erased. This function is effective only
when the device can be accessed through BIOS.

ATA(PI) Detect Timeout

Set this option to stop the system search for ATAPI devices within the
specified number of seconds. The options are 0, 5, 10, 15, 20, 25, 30, and

35 (seconds). Most ATA disk drives can be detected within 5 seconds.

ATA(PI) 80Pin Cable Detection

This option selects the mechanism for detecting the 80-pin ATA(PI) cable.
Options include Host & Device, Host, and Device. Host: This option
uses the motherboard onboard IDE controller to detect the type of IDE cable
used. Device This option uses the IDE disk drive to detect the type of IDE
cable used. Host & Device: This option uses both the motherboard onboard
IDE controller and IDE disk drive to detect the type of IDE cable used.

4-9

BIOS

SUPER P3TDLR User's Manual

Floppy Configuration

Floppy A

Use this option to specify which of floppy drive you have installed in the A
drive. The settings are Disabled, 360 KB 5 1/4", 1.2 MB 5 1/4", 720 KB 3 1/
2", 1.44 MB 3 1/2" and 2.88 MB 3 1/2".

Floppy B

Use this option to specify which of floppy drive you have installed in the B
drive. The settings are Disabled, 360 KB 5 1/4", 1.2 MB 5 1/4", 720 KB 3
1/2", 1.44 MB 3 1/2" and 2.88 MB 3 1/2".

Diskette Write Protect

This option allows you to prevent any writing to your floppy diskette. The
settings are Enabled and Disabled. The Enabled setting is effective only if
the device is accessed through BIOS.

Floppy Drive Seek

Use this option to Enable or Disable the floppy seek routine on bootup.

BIOS

Boot Settings Configuration

Quick Boot

This option allows the BIOS to skip certain tests that are normally performed
on boot up. You can disable the option to speed up boot time. The settings
are Disabled and Enabled.

Quiet Boot

If Disabled, this option will cause the normal POST messages to be dis­played upon setup. When Enabled, the OEM logo is displayed instead of the
POST messages. The default setting is Disabled.

Add-On ROM Display Mode

Set this option to display add-on ROM (read-only memory) messages. The
settings for this option are Force BIOS and Keep Current. Force BIOS
allows the computer to force a third party BIOS to display during system
boot. Keep Current has the system display AMIBIOS information on bootup.

4-10

Chapter 7: BIOS/Setup

BootUp Num Lock

This option is used to select the status of the Number Lock function on your
keyboard on bootup. The settings are On and Off.

BootUp CPU Speed

This option is used set the CPU speed to either High or Low.

PS/2 Mouse Support

This option specifies whether a PS/2 Mouse will be supported. Settings are

Enabled and Disabled.

Typematic Rate

Set this option to select the rate at which the computer repeats a key that
is held down. Settings are Fast and Slow. Fast: This sets the rate the
computer repeats a key to over 20 times per second. Under normal opera­tions, this setting should not be changed. Slow: This sets the rate the
computer repeats a key to under 8 times per second.

System Keyboard

This option is to let the system know if a keyboard is Present or Absent.

Primary Display

This option specifies the type of monitor display you have installed on the
system. The settings are Absent, VGA/EGA, Color 40 x 25, Color 80 x 25
and monochrome.

Parity Check

Use this option to either Enable or Disable the use of memory parity check­ing.

Boot to OS/2

This option can be used to boot the system to an OS/2 operating system.
The settings are No and Yes.

4-11

BIOS

SUPER P3TDLR User's Manual

Wait for F1 if Error

This settings for this option are Enabled and Disabled. Disabled: This
prevents the AMIBIOS to wait on an error for user intervention. This setting
should be used if there is a known reason for a BIOS error to appear. An
example would be a system administrator must remote boot the system
when the computer system does not have a keyboard currently attached. If
this setting is set, the system will continue to bootup into the operating
system. If "F1" is enabled, the system will wait until the BIOS setup is
entered. Enabled: This option configures the system BIOS to wait for any
error. If an error is detected, pressing <F1> will enter Setup and the BIOS
setting can be adjusted to fix the problem. This normally happens when
upgrading the hardware and not setting the BIOS to recognize it.

Press <Delete> Message Display

This option tells the system to display or not display the "Hit Delete to Enter
Setup" message. The settings are Enabled and Disabled.

Internal Cache

This option is for enabling or disabling the internal CPU L1 cache. Settings

BIOS

include Disabled, Write-Thru and Write-Back and Reserved. Disabled: This
option prevents the system from using the internal CPU L1 cache. This
setting should be used to slow the computer system down or to trouble­shoot error messages. Write-Thru: This option allows the computer system
to use the internal CPU L1 cache as Write-Though cache. Write-Through
cache is slower than Write-Back cache. It performs write operations to the
internal L1 CPU cache and system memory simultaneously. Write-Back
This option allows the computer system to use the internal CPU L1 cache as
Write-Back cache. Write-Back cache is faster than Write-Through cache.
Write-Back cache is a caching method in which modifications to data in the
cache aren’t copied to the cache source until absolutely necessary. Write­back caching is available on all CPUs supported by this BIOS. With these
CPUs, write operations stored in the L1 cache aren’t copied to main memory
until absolutely necessary. Write-Back cache is the default setting.

External Cache

This option is for enabling or disabling the internal CPU L2 cache. Settings
include Disabled, Write-Thru and Write-Back. See description above.

4-12

Chapter 7: BIOS/Setup

System BIOS Cacheable

This option enables you to move the system BIOS to the memory cache to
improve performance. Settings are Enabled and Disabled.

Event Log Configuration

Event Logging

This option Enables or Disables the logging of events. You can use this
screen to select options for the Event Log Configuration Settings. You can
access sub screens to view the event log and mark all events as read. Use
the up and down arrow keys to select an item, and the <+> (plus) and <->
(minus) keys to change the option setting. The settings are described on the
following pages. The screen is shown below.

ECC Event Logging

This option Enables or Disables the logging of ECC events. The events
logged by AMIBIOS are post errors such as a bad BIOS, floppy errors, or
hard drive errors.

Clear All Event Logs

This option can be used to tell the system to clear the event log on the next
boot up. The settings are No and Yes.

View Event Log

Highlighting this and pressing <Enter> will allow you to view the unread
events from the event log area.

View All Events as Read

Highlighting this and pressing <Enter> will mark all events in the log area as
having already been read.

4-13

BIOS

SUPER P3TDLR User's Manual

Peripheral Device Configuration

Onboard SCSI

This option allows you to enable the onboard SCSI. The settings are En­abled and Disabled.

Power Lost Control

This option determines how the system will respond when power is reap­plied after a power loss condition. Always On means the system will
automatically start up when power is reapplied. "Always Off" means you
must push the main power button to restart the system after power is
restored.

Processor Configuration

This option enables or disables the AMIBIOS to detect the serial number(s)
of the processor(s). The settings are Disabled and Enabled.

System Health Monitor

BIOS

The BIOS continuously monitors the health of your system by measuring
certain voltage levels and temperatures.

System Overheat Warning

This option allows you to Enable or Disable a system overheat warning
signal, used to notify you in the event of a dangerous rise in heat levels.

Overheat Warning Temperature

This option allows you to specify the temperature threshold that, when
exceeded, will trigger the overheat warning alarm.

The rest of the Health Monitor menu lists various voltages and temperatures
as they are currently being measured. These include CPU temperature, CPU
voltage, the rpms of the fans (CPU, chassis and thermal control) as well as
the primary voltage levels used by the system: +3.3V, +5V, +12V and -12V.

4-14

Chapter 7: BIOS/Setup

4-5 Chipset Setup

Choose "Chipset Setup" from the AMIBIOS Setup Utility main menu. The
screen is shown below. All Chipset Setup options are described following
the screen. You can use this screen to select options for the main
controller hub (MCH, or North Bridge) configuration.

BIOS SETUP UTILITY

Main Advanced Chipset PCIPnP Power Boot Security Ex it

C000,16k Shadow [Cached/WP]
C400,16k Shadow [Cached/WP]
C800,16k Shadow [Disabled]
CC00,16k Shadow [Disabled]
D000,16k Shadow [Disabled]
D400,16k Shadow [Disabled]
D800,16k Shadow [Disabled]
DC00,16k Shadow [Disabled]
Act to Deact [6 CLKS]
Act to Read/Write [3 CLKS]
RAS Precharge Time [3 CLKS]
RA Cycle Time [8]
Write to Deact [3 CLKS]
SDRAM CAS Latency [3]
ISA IO Cycle Delay [1.5 BCLK]
MPS 1.4 Support [Enabled]

V02.03 (C)Copyright 1985-2000, American Megatrends, Inc.

Options for MCH

Select Screen

↔

Select Item

↑↓

+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit

BIOS

C000, 16k Shadow

C400, 16k Shadow

C800, 16k Shadow

CC00, 16k Shadow

D000, 16k Shadow

D400, 16k Shadow

D800, 16k Shadow

4-15

SUPER P3TDLR User's Manual

DC00, 16k Shadow

These options specify how the 16 KB of video ROM at each of the above
addresses is treated. When Disabled, the contents of the video ROM are
not copied to RAM. When Enabled, the contents of 16 KB of video ROM
beginning at the above address are copied (shadowed) from ROM to RAM
for faster application. When set to Cached/WP, the contents of 16 KB of
video ROM beginning at the above address are copied (shadowed) from
ROM to RAM and can be written to or read from cache memory. The
settings for this option are Disabled, Enabled and Cached/WP. (The optimal
settings are Cached/WP for C000 and C400 and Disabled for all the other
settings.

Act to Deact

This settings for this option are 6 CLKS and 5 CLKS.

Act to Read/Write

This settings for this option are 3 CLKS and 2 CLKS.

RAS Precharge Time

BIOS

The precharge time is the number of cycles it takes for the RAS to
accumulate a charge before a DRAM refresh. Insufficient recharge
time may cause the DRAM to lose data. The settings are 3 CLKS (which is
more stable) and 2 CLKS. RAS stands for Row Address Strobe.

RAS Cycle Time

This option defines the RAS cycle time. Settings include 10 CLKS, 9 CLKS,
8 CLKS and 7 CLKS.

Write to Deact

This settings for this option are 3 CLKS and 2 CLKS.

SDRAM CAS Latency

This settings for this option are CAS Latency 3 and CAS Latency 2. CAS
stands for Column Address Strobe.

4-16

Chapter 7: BIOS/Setup

ISA IO Cycle Delay

This settings for this option are Full Delay, 1.5 BCLK, 2.5 BLCK and 3.5
BLCK.

MPS 1.4 Support

The settings for this option are Enabled and Disabled.

4-6 PCI PnP Setup

Choose PCI/PnP Setup from the AMIBIOS Setup main menu. All PCI/PnP
options are described in this section. The PCI/PnP Setup screen is shown
below.

BIOS SETUP UTILITY

Main Advanced Chipset PCIPnP Power Boot Security Exit

Plug & Play O/S
Reset Config Data
PCI Latency Timer
Allocate IRQ to VGA
Palette Snooping
PCI IDE BusMaster
OffBoard PCI/ISA IDE Card

USB Controller

PCI Slot-1 IRQ preference
PCI Slot-2 IRQ preference
Onboard VGA IRQ preference
Onboard LAN1 IRQ preference
Onboard LAN2 IRQ preference
PCI Slot-3 IRQ preference
PCI Slot-4 IRQ preference
Onboard SCSI IRQ preference

V02.03 (C)Copyright 1985-2000, American Megatrends, Inc.

[No]
[No]
[64]
[Yes]
[Disabled]
[Disabled]
[Auto]

[Enabled]

[Auto]
[Auto]
[Auto]
[Auto]
[Auto]
[Auto]
[Auto]
[Auto]

No: lets the BIOS
configure all the
devices in the system.
Yes: lets the
operating system
configure Plug and
Play (PnP) devices not
required for boot if
your system has a Plug
and Play operating
system.

Select Screen

↔

Select Item

↑↓

+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit

Plug & Play OS

BIOS

Choose the No setting for computers that do not meet the Plug and Play
specifications, which will allow the BIOS to configure all the devices in the
system. Choosing the Yes setting lets the operating system configure PnP
devices that are not required for boot up (if the system has a PnP operating
system). The operating system would have the ability to change interrupt,

4-17

SUPER P3TDLR User's Manual

I/O, and DMA settings. Set this option if the system is running Windows
95®, Windows 98® or Windows 2000®. Several other operating systems
are also PnP-aware.

Reset Configuration Data

Choosing the Yes setting will cause the PnP configuration data in the BIOS
to be cleared on the next boot up. Choosing the No setting does not force
PnP data to be cleared on the next boot.

PCI Latency Timer

This option specifies the latency timing of the PCI clocks for all PCI devices.
Settings include 32, 64, 96, 128, 160, 192, 224 and 248 PCI clocks.

Allocate IRQ to PCI VGA

This option lets you allocate an interrupt request (IRQ) to the PCI VGA
adapter card (if used). The settings are Yes and No.

Palette Snooping

When enabled, this option informs PCI devices that an ISA graphics device

BIOS

is installed. The settings are Disabled and Enabled. This does not neces­sarily indicate a physical ISA adapter card. The graphics chipset can be
mounted on a PCI card. Always check with your adapter card manuals
first, before modifying the default settings in the BIOS.

PCI IDE BusMaster

The settings for this option are Disabled and Enabled. Enable to specify
that the IDE controller on the PCI bus has bus mastering capabilities.

OffBoard PCI/ISA IDE Card

The settings for this option are Auto, PCI Slot 1, PCI Slot 2, PCI Slot 3, PCI
Slot 4, PCI Slot 5, and PCI Slot 6.

USB Function

The settings for this option are Disabled and Enabled. Disabled prevents
the use of the USB ports and Enabled allows the use of the USB ports.

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Chapter 7: BIOS/Setup

PCI Slot-1 IRQ Preference

This option allows you to change the IRQ for PCI slot 1. The settings are
Auto, 3, 4, 5, 7, 9, 10, 11, 12, 14, and 15. The Auto setting lets the BIOS
assign the IRQ.

PCI Slot-2 IRQ Preference

This option allows you to change the IRQ for PCI slot 2. The settings are
Auto, 3, 4, 5, 7, 9, 10, 11, 12, 14, and 15. The Auto setting lets the BIOS
assign the IRQ.

Onboard VGA IRQ Preference

This option allows you to change the IRQ for the onboard VGA. The set­tings are Auto, 3, 4, 5, 7, 9, 10, 11, 12, 14, and 15. The Auto setting lets
the BIOS assign the IRQ.

Onboard LAN1 IRQ Preference

This option allows you to change the IRQ for the onboard LAN1. The
settings are Auto, 3, 4, 5, 7, 9, 10, 11, 12, 14, and 15. The Auto setting
lets the BIOS assign the IRQ.

Onboard LAN2 IRQ Preference

This option allows you to change the IRQ for the onboard LAN2. The
settings are Auto, 3, 4, 5, 7, 9, 10, 11, 12, 14, and 15. The Auto setting
lets the BIOS assign the IRQ.

PCI Slot-3 IRQ Preference

This option allows you to change the IRQ for PCI slot 3. The settings are
Auto, 3, 4, 5, 7, 9, 10, 11, 12, 14, and 15. The Auto setting lets the BIOS
assign the IRQ.

PCI Slot-4 IRQ Preference

This option allows you to change the IRQ for PCI slot 4. The settings are
Auto, 3, 4, 5, 7, 9, 10, 11, 12, 14, and 15. The Auto setting lets the BIOS
assign the IRQ.

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BIOS

SUPER P3TDLR User's Manual

Onboard SCSI IRQ Preference

This option allows you to change the IRQ for the onboard SCSI. The set­tings are Auto, 3, 4, 5, 7, 9, 10, 11, 12, 14, and 15. The Auto setting lets
the BIOS assign the IRQ.

IRQ 3

IRQ 4

IRQ 5

IRQ 7

IRQ 9

IRQ 10

IRQ 11

IRQ 14

IRQ 15

BIOS

4-20

Chapter 7: BIOS/Setup

4-7 Power Setup

Choose "Power Setup" from the AMIBIOS Setup main menu. All Power
Setup options are described in this section. The Power Setup screen is
shown below.

BIOS SETUP UTILITY

Main Advanced Chipset PCIPnP Power Boot Security Exit

ACPI Aware O/S
Power Management
Power Button Mode
Sleep Button Enable
Green PC Monitor Power State
Video Power Down Mode
Hard Disk Power Down Mode
Inactivity Timer
Suspend Timeout (Minutes)
IRQ1
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ9
IRQ10
IRQ11
IRQ12
IRQ14
IRQ15

V02.03 (C)Copyright 1985-2000, American Megatrends, Inc.

ACPI Aware O/S

[Yes]
[Enabled]
[On/Off]
[Suspend]
[StandBy]
[Suspend]
[Disabled]
[Off]
[Off]
[Monitor]
[Ignore]
[Ignore]
[Ignore]
[Ignore]
[Ignore]
[Ignore]
[Ignore]
[Ignore]
[Monitor]
[Monitor
[Ignore]

Select Screen

↔

Select Item

↑↓

+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit

BIOS

This option allows the system to utilize Intel's ACPI (Advanced Configuration
and Power Interface) specification. Settings are No and Yes. DOS®,
Windows 3.x®, and Windows NT® are examples of non-ACPI aware oper­ating systems. Windows 95®, Windows 98® and Windows 2000® are
examples of ACPI aware operating systems.

Power Management

This option allows you to select using APM (Advanced Power Manage­ment). The settings are Disabled and Enabled.

Power Button Mode

This option specifies how the external power button on the computer chas­sis functions. When set to On/Off, depressing the power button turns the
computer on or off. When set to "Suspend", depressing the power button
places the computer in Suspend mode or Full On power mode. The Standby
setting places the computer in Standby or Full On mode.

4-21

SUPER P3TDLR User's Manual

Sleep Button Enable

This option is to enable the use of the sleep button. The settings are
Suspend and Disabled.

Green PC Monitor Power State

This option specifies the power state that a green PC-compliant monitor
enters when BIOS places it in a power saving state after the specified
period of display inactivity has expired. The settings include Standby, Sus-

pend and Off.

Video Power Down Mode

This option specifies the power state that the VGA video subsystem enters
after the specified period of display inactivity has expired. The settings
include Disabled, Standby and Suspend.

Hard Disk Power Down Mode

This option specifies the power conserving state that the hard disk drive(s)
enters after the specified period of inactivity has expired. The settings
include Disabled, Standby and Suspend.

BIOS

Inactivity Timer

This option specifies the length of hard disk inactivity time that should expire
before entering the power conserving state. The settings include Off, 1, 5,
10, 20, 30, 60 and 120 (minutes).

Suspend Timeout

This option specifies if BIOS is to monitor for display activity when in a
power saving state. The settings include Off, 1, 2, 3, 4, 5, 6, 7, 8, 9 and 10
(minutes).

IRQ1

IRQ3

IRQ4

IRQ5

IRQ6

4-22

Chapter 7: BIOS/Setup

IRQ7

IRQ9

IRQ10

IRQ11

IRQ12

IRQ14

IRQ15

With the above options, you can monitor each interrupt request and resume
the system's normal power up state when activated. Settings are Ignore
and Monitor. All IRQs are defaulted to Ignore except for IRQ 1, 12 and 14,
which default to Monitor.

4-23

BIOS

SUPER P3TDLR User's Manual

n

4-8 Boot Setup

Choose "Boot Setup" from the AMIBIOS Setup main menu. All Boot Setup
options are described in this section. The Boot Setup screen is shown
below.

Main Advanced Chipset PCIPnP Pow er Boot Se curity Exit

> Boot Device Priority
> Hard Disk Drives
> Removable Devices
> ATAPI CDROM Drives

BIOS

V02.03 (C)Copyright 1985-2000, American Megatrends, Inc.

BIOS SETUP UTILITY

Select Screen

↔

Select Item

↑↓

Enter Go to Sub Scree
F1 General Help
F10 Save and Exit
ESC Exit

Boot Device Priority

1st Boot Device

This option is used to specify the order of the boot sequence that will be
followed from the available system devices. The settings for the 1st Boot
Device are Removable Device, ATAPI CDROM, Hard Drive and Disabled.

2nd Boot Device

The settings for the 2nd Boot Device are Removable Device, ATAPI
CDROM, Hard Drive and Disabled.

4-24

Chapter 7: BIOS/Setup

3rd Boot Device

The settings for the 3rd Boot Device are Removable Device, ATAPI CDROM,
Hard Drive and Disabled.

Hard Disk Drives

Use this screen to view the hard drives that have been auto-detected or
entered manually on your system.

Removable Devices

Use this screen to view the removable devices that have been auto-de­tected or entered manually on your system.

ATAPI CDROM Drives

Use this screen to view the ATAPI CDROM drives that have been auto­detected or entered manually on your system.

4-25

BIOS

SUPER P3TDLR User's Manual

n

4-9 Security Setup

Choose "Security Setup" from the AMIBIOS Setup main menu. All Security
Setup options are described in this section. The Security Setup screen is
shown below.

Main Advanced Chipset PCIPnP Power Boot Security Exit

Supervisor Password : Not Installed
User Password : Not Installed

> Change Supervisor Password
> Change User Password
> Clear User Password
Boot Sector Virus Protection [Disabled]

BIOS

V02.03 (C)Copyright 1985-2000, American Megatrends, Inc.

BIOS SET UP U T ILITY

Install or Change the
password.

↔ Select Screen
↑↓

Select Item
Enter Go to Sub Scree
F1 General Help
F10 Save and Exit
ESC Exit

Supervisor Password

User Password

AMIBIOS provides both Supervisor and User password functions. If you
use both passwords, the Supervisor password must be set first.

The system can be configured so that all users must enter a password
every time the system boots or when AMIBIOS Setup is executed, using
either or both the Supervisor password or User password. The Supervisor
and User passwords activate two different levels of password security. If
you select password support, you are prompted for a 1 – 6 character
password. Type the password on the keyboard. The password does not
appear on the screen when typed. Make sure you write it down. If you
forget it, you must clear CMOS and reconfigure. Remember your Pass-
word! Keep a record of the new password when the password is
changed. If you forget the password, you must erase the system configu­ration information in CMOS.

4-26

Chapter 7: BIOS/Setup

Change Supervisor Password

This option allows you to change supervisor password that was entered
previously.

Change User Password

This option allows you to change a user password that was entered previ­ously.

Clear User Password

Use this option to clear the user password so that it is not required to be
entered when the system boots up.

Boot Sector Virus Protection

This option allows you to enable or disable a virus detection program to
protect the boot sector of your hard disk drive. The settings for this option
Disabled and Enabled. If Enabled, AMIBIOS will display a warning when
any program (or virus) issues a Disk Format command or attempts to write
to the boot sector of the hard disk drive.

4-27

BIOS

SUPER P3TDLR User's Manual

n

4-10 Exit Setup

Choose "Exit Setup" from the AMIBIOS Setup main menu. All Exit Setup
options are described in this section. The Exit Setup screen is shown
below.

Main Advanced Chipset PCIPnP Power Boot Security Exit

> Exit Saving Changes
> Exit Discarding Changes
> Load Optimal Defaults
> Load Fail-Safe Defaults
> Discard Changes

BIOS

V02.03 (C)Copyright 1985-2000, American Megatrends, Inc.

BIOS SETUP UTILITY

Exit system setup with
saving the changes.

Select Screen

↔

Select Item

↑↓

Enter Go to Sub Scree
F1 General Help
F10 Save and Exit
ESC Exit

Exit Saving Changes

Highlighting this setting and then pressing <Enter> will save any changes
you made in the BIOS Setup program and then exit. Your system should
then continue with the boot up procedure.

Exit Discarding Changes

Highlighting this setting and then pressing <Enter> will ignore any changes
you made in the BIOS Setup program and then exit. Your system should
then continue with the boot up procedure.

4-28

Chapter 7: BIOS/Setup

Load Optimal Defaults

Highlighting this setting and then pressing <Enter> provides the optimum
performance settings for all devices and system features.

Load Failsafe Defaults

Highlighting this setting and then pressing <Enter> provides the safest set
of parameters for the system. Use them if the system is behaving errati­cally.

Discard Changes

Highlighting this setting and then pressing <Enter> will ignore any changes
you made in the BIOS Setup program but will not exit the BIOS Setup pro­gram.

4-29

BIOS

SUPER P3TDLR User's Manual

NOTES

BIOS

4-30

Appendix A: BIOS Error Beep Codes

Appendix A

BIOS Error Beep Codes & Messages

During the POST (Power-On Self-Test) routines, which are performed
each time the system is powered on, errors may occur.

Non-fatal errors are those which, in most cases, allow the system to
continue the boot-up process. The error messages normally appear on
the screen.

Fatal errors are those which will not allow the system to continue the
boot-up procedure. If a fatal error occurs, you should consult with your
system manufacturer for possible repairs.

These fatal errors are usually communicated through a series of audible
beeps. The numbers on the following page correspond to the number of
beeps for the error described.

A-1

SUPER P3TDLR User’s Manual

AMIBIOS Error Beep Codes

POST Error Beep Codes

1 beep: Refresh failure - the memory refresh circuitry on the motherboard is

faulty. (Fatal error)

3 beeps: Base 64KB memory failure - memory failure occurred in the first

64KB of memory. (Fatal error)

6 beeps: Keyboard controller Gate A20 failure. The keyboard controller may

be bad. The BIOS cannot switch to protected mode. (Fatal error)

7 beeps: Processor exception interrupt error. The CPU generated an

exception interrupt. (Fatal error)

8 beeps: Display memory read/write error. The system video adapter is

either missing or its memory is faulty. This is not a fatal error.

Bootblock Error Beep Codes

2 beeps: BIOS ROM file absent - the BIOS was unable to find the specific

file name required to flash the BIOS.

4 beeps: Flash program successful.

5 beeps: Media read error. The floppy or ATAPI media is not present or

APPENDIX A

7 beeps: Flash not present. The BIOS was unable to detect the presence of

10 beeps: Flash erase error - the flash device could not be properly erased.

11 beeps: Flash program error.

12 beeps: BIOS ROM file incorrect size.

13 beeps: BIOS ROM image mismatch. The BIOS ROM file layout configu-

cannot be read.

a flash device.

ration does not match the image present in the flash device.

A-2

Appendix A: BIOS Error Beep Codes

If you hear... it's because...

5 short and 1 long beeps no memory detected in system

6 short and 1 long beeps EDO memory detected in system

7 short and 1 long beeps SMBUS (System Management Bus)

error

A-3

APPENDIX A

SUPER P3TDLR User’s Manual

Notes

APPENDIX A

A-4

Appendix B: AMIBIOS POST Diagnostic Error Messages

Appendix B

AMIBIOS POST Diagnostic Error Messages

This section describes the power-on self-tests (POST) port 80 codes for
the AMIBIOS.

Check
Point Description

00 Code copying to specific areas is done. Passing control

to INT 19h boot loader next.

03 NMI is Disabled. Next, checking for a soft reset or a

power-on condition.

05 The BIOS stack has been built. Next, disabling cache

memory.

06 Uncompressing the post code unit next.

07 Next, initializing the CPU init and the CPU data area.

08 The CMOS checksum calculation is done next.

0B Next, performing any required initialization before

keyboard BAT command is issued.

0C The keyboard controller I/B is free. Next, issuing the

BAT command to the keyboard controller.

0E The keyboard controller BAT command result has been

verified. Next, performing any necessary initialization
after the keyboard controller BAT command test.

0F The initialization after the keyboard controller BAT

command test is done. The keyboard command byte is
written next.

B-1

APPENDIX B

SUPER P3TDLR User’s Manual

Check
Point Description

10 The keyboard controller command byte is written.

Next, issuing the pin 23 and 24 blocking and unblocking
commands.

11 Next, checking if the <End or <Ins> keys were pressed

during power on. Initializing CMOS RAM if the
Initialize CMOS RAM in every boot AMIBIOS POST
option was set in AMIBCP or the <End> key was
pressed.

12 Next, disabling DMA controllers 1 and 2 and interrupt

controllers 1 and 2.

13 The video display has been disabled. Port B has been

initialized. Next, initializing the chipset.

14 The 8254 timer test will begin next.

19 The 8254 timer test is over. Starting the memory refresh

test next.

1A The memory refresh test line is toggling. Checking the

15 second on/off time next.

23 Reading the 8042 input port and disabling the

MEGAKEY Green PC feature next. Making the
BIOS code segment writable and performing any
necessary configuration before initializing the interrupt
vectors.

24 The configuration required before interrupt vector

initialization has completed. Interrupt vector initialization
is done. Clearing the password if the POST DIAG
switch is on.

25 Interrupt vector initialization is done. Clearing the

password if the POST DIAG Switch is on.

27 Any initialization before setting video mode will be

done next.

B-2

Appendix B: AMIBIOS POST Diagnostic Error Messages

Check
Point Description

28 Initialization before setting the video mode is complete.

Configuring the monochrome mode and color mode
settings next.

2A Bus initialization system, static, output devices will be

done next, if present.

2B Passing control to the video ROM to perform any

required configuration before the video ROM test.

2C All necessary processing before passing control to the

video ROM is done. Looking for the video ROM next
and passing control to it.

2D The video ROM has returned control to BIOS POST.

Performing any required processing after the video
ROM had control.

2E Completed post-video ROM test processing. If the

EGA/VGA controller is not found, performing the
display memory read/write test next.

2F The EGA/VGA controller was not found. The display

memory read/write test is about to begin.

30 The display memory read/write test passed. Look for

retrace checking next.

31 The display memory read/write test or retrace checking

failed. Performing the alternate display memory
read/write test next.

32 The alternate display memory read/write test passed.

Looking for alternate display retrace checking next.

34 Video display checking is over. Setting the display

mode next.

37 The display mode is set. Displaying the power on

message next.

B-3

APPENDIX B

SUPER P3TDLR User’s Manual

Check
Point Description

38 Initializing the bus input, IPL, and general devices next, if

present.

39 Displaying bus initialization error messages.

3A The new cursor position has been read and saved.

Displaying the Hit <DEL> message next.

40 Preparing the descriptor tables next.

42 The descriptor tables are prepared. Entering protected

mode for the memory test next.

43 Entered protected mode. Enabling interrupts for

diagnostics mode next.

44 Interrupts enabled if the diagnostics switch is on.

Initializing data to check memory wraparound at 0:0 next.

45 Data initialized. Checking for memory wraparound at

0:0 and finding the total system memory size next.

46 The memory wraparound test has completed. The

memory size calculation has been completed. Writing
patterns to test memory next.

47 The memory pattern has been written to extended

memory. Writing patterns to the base 640 KB memory
next.

48 Patterns written in base memory. Determining the

amount of memory below 1 MB next.

49 The amount of memory below 1 MB has been found

and verified. Determining the amount of memory above
1 MB memory next.

4B The amount of memory above 1 MB has been found

and verified. Checking for a soft reset and clearing the
memory below 1 MB for the soft reset next. If this is a
power on situation, going to checkpoint 4Eh next.

B-4

Appendix B: AMIBIOS POST Diagnostic Error Messages

Check
Point Description

4C The memory below 1 MB has been cleared via a soft

reset. Clearing the memory above 1 MB next.

4D The memory above 1 MB has been cleared via a soft

reset. Saving the memory size next. Going to checkpoint
52h next.

4E The memory test started, but not as the result of a soft

reset. Displaying the first 64 KB memory size next.

4F The memory size display has started. The display is

updated during the memory test. Performing the
sequential and random memory test next.

50 The memory below 1 MB has been tested and

initialized. Adjusting the displayed memory size for
relocation and shadowing next.

51 The memory size display was adjusted for relocation

and shadowing. Testing the memory above 1 MB next.

52 The memory above 1 MB has been tested and

initialized. Saving the memory size information next.

53 The memory size information and the CPU registers are

saved. Entering real mode next.

54 Shutdown was successful. The CPU is in real mode.

Disabling the Gate A20 line, parity, and the NMI next.

57 The A20 address line, parity, and the NMI are

disabled. Adjusting the memory size depending on
relocation and shadowing next.

58 The memory size was adjusted for relocation and

shadowing. Clearing the Hit <DEL> message next.

59 The Hit <DEL> message is cleared. The <WAIT>

message is displayed. Starting the DMA and interrupt
controller test next.

B-5

APPENDIX B

SUPER P3TDLR User’s Manual

Check
Point Description

60 The DMA page register test passed. Performing the

DMA Controller 1 base register test next.

62 The DMA controller 1 base register test passed.

Performing the DMA controller 2 base register test next.

65 The DMA controller 2 base register test passed.

Programming DMA controllers 1 and 2 next.

66 Completed programming DMA controllers 1 and 2.

Initializing the 8259 interrupt controller next.

7F Extended NMI source enabling is in progress.

80 The keyboard test has started. Clearing the output

buffer and checking for stuck keys. Issuing the
keyboard reset command next.

81 A keyboard reset error or stuck key was found. Issuing

the keyboard controller interface test command next.

82 The keyboard controller interface test completed.

Writing the command byte and initializing the circular
buffer next.

83 The command byte was written and global data

initialization has been completed. Checking for a
locked key next.

84 Locked key checking is over. Checking for a memory

size mismatch with CMOS RAM data next.

85 The memory size check is done. Displaying a soft error

and checking for a password or bypassing WINBIOS
Setup next.

86 The password was checked. Performing any required

programming before WINBIOS Setup next.

B-6

Appendix B: AMIBIOS POST Diagnostic Error Messages

Check
Point Description

87 The programming before WINBIOS Setup has

been completed. Uncompressing the WINBIOS Setup
code and executing the AMIBIOS Setup or WINBIOS
Setup utility next.

88 Returned from WINBIOS Setup and cleared the screen.

Performing any necessary programming after WINBIOS
Setup next.

89 The programming after WINBIOS Setup has been

completed. Displaying the power-on screen message
next.

8B The first screen message has been displayed. The

<WAIT...> message is displayed. Performing the PS/2
mouse check and extended BIOS data area allocation
check next.

8C Programming the WINBIOS Setup options next.

8D The WINBIOS Setup options are programmed.

Resetting the hard disk controller next.

8F The hard disk controller has been reset. Configuring the

floppy drive controller next.

91 The floppy drive controller has been configured.

Configuring the hard disk drive controller next.

95 Initializing the bus option ROMs from C800 next.

96 Initializing before passing control to the adaptor ROM at

C800.

97 Initialization before the C800 adaptor ROM gains

control has been completed. The adaptor ROM check
is next.

98 The adaptor ROM had control and has now returned

control to BIOS POST. Performing any required
processing after the option ROM returned control.

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APPENDIX B

SUPER P3TDLR User’s Manual

Check
Point Description

99 Any initialization required after the option ROM test has

been completed. Configuring the timer data area and
printer base address next.

9A Set the timer and printer base addresses. Setting the

RS-232 base address next.

9B Returned after setting the RS-232 base address.

Performing any required initialization before the
Coprocessor test next.

9C Required initialization before the Coprocessor test is

over. Initializing the Coprocessor next.

9D Coprocessor initialized. Performing any required

initialization after the Coprocessor test next.

9E Initialization after the Coprocessor test is complete.

Checking the extended keyboard, keyboard ID, and
Num Lock key next. Issuing the keyboard ID command
next.

A2 Displaying any soft errors next.

A3 The soft error display has completed. Setting the

keyboard typematic rate next.

A4 The keyboard typematic rate is set. Programming the

memory wait states next.

A5 Memory wait state programming is over. Clearing the

screen and enabling parity and the NMI next.

A7 NMI and parity enabled. Performing any initialization

required before passing control to the adaptor ROM at
E000 next.

A8 Initialization before passing control to the adaptor ROM

at E000h completed. Passing control to the adaptor
ROM at E000h next.

B-8

Appendix B: AMIBIOS POST Diagnostic Error Messages

Check
Point Description

A9 Returned from adaptor ROM at E000h control.

Next, performing any initialization required after
the E000 option ROM had control.

AA Initialization after E000 option ROM control has

completed. Displaying the system configuration next.

AB Building the multiprocessor table, if necessary. POST

next.

B0 The system configuration is displayed.

AC Uncompressing the DMI data and initializing DMI.

B1 Copying any code to specific areas.

D0h The NMI is disabled. Power on delay is starting.

Next, the initialization cade checksum will be verified.

D1h Initializing the DMA controller. Performing the keyboard

controller BAT test. Starting memory refresh, and
entering 4 GB flat mode next.

D3h Starting memory sizing next.

D4h Returning to real mode. Executing any OEM patches

and setting the stack next.

D5h Passing control to the uncompressed code in shadow

RAM at E000:0000h. The initialization code is copied
to segment 0 and control will be transferred to segment

0.

D6h Control is in segment 0. Next, checking if

<Ctrl><Home>was pressed and verifying the system
BIOS checksum.

If either <Ctrl><Home> was pressed or the system BIOS
checksum is bad, next the system will go to checkpoint code
E0h. Otherwise, going to checkpoint code D7h.

B-9

APPENDIX B

SUPER P3TDLR User’s Manual

Notes

B-10