The information in this User’s Manual has been carefully reviewed and is believed to be accurate.
The vendor assumes no responsibility for any inaccuracies that may be contained in this document,
makes no commitment to update or to keep current the information in this manual, or to notify any
person or organization of the updates. Please Note: For the most up-to-date version of this
manual, please see our web site at www.supermicro.com.
Super Micro Computer Inc. ("Supermicro") reserves the right to make changes to the product
described in this manual at any time and without notice. This product, including software, if any,
and documentation may not, in whole or in part, be copied, photocopied, reproduced, translated or
reduced to any medium or machine without prior written consent.
IN NO EVENT WILL SUPER MICRO COMPUTER BE LIABLE FOR DIRECT, INDIRECT, SPECIAL,
INCIDENTAL, SPECULATIVE OR CONSEQUENTIAL DAMAGES ARISING FROM THE USE
OR INABILITY TO USE THIS PRODUCT OR DOCUMENTATION, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. IN PARTICULAR, SUPER MICRO COMPUTER SHALL NOT
HAVE LIABILITY FOR ANY HARDWARE, SOFTWARE, OR DATA STORED OR USED WITH THE
PRODUCT, INCLUDING THE COSTS OF REPAIRING, REPLACING, INTEGRATING, INSTALLING
OR RECOVERING SUCH HARDWARE, SOFTWARE, OR DATA.
Any disputes arising between manufacturer and customer shall be governed by the laws of Santa
Clara County in the State of California, USA. The State of California, County of Santa Clara shall
be the exclusive venue for the resolution of any such disputes. Supermicro's total liability for
all claims will not exceed the price paid for the hardware product.
FCC Statement: This equipment has been tested and found to comply with the limits for a Class
A digital device pursuant to Part 15 of the FCC Rules. These limits are designed to provide
reasonable protection against harmful interference when the equipment is operated in a commercial
environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the manufacturer’s instruction manual, may cause harmful
interference with radio communications. Operation of this equipment in a residential area is likely
to cause harmful interference, in which case you will be required to correct the interference at your
own expense.
California Best Management Practices Regulations for Perchlorate Materials: This Perchlorate
warning applies only to products containing CR (Manganese Dioxide) Lithium coin cells. “Perchlorate
Material-special handling may apply. See www.dtsc.ca.gov/hazardouswaste/perchlorate”
WARNING: Handling of lead solder materials used in this
product may expose you to lead, a chemical known to
the State of California to cause birth defects and other
reproductive harm.
Manual Revision 1.0a
Release Date: April 28, 2008
Unless you request and receive written permission from Super Micro Computer, Inc., you may not
copy any part of this document.
Information in this document is subject to change without notice. Other products and companies
referred to herein are trademarks or registered trademarks of their respective companies or mark
holders.
(Notes: i. DIMM slot# specified: DIMM slot to be populated; “---“: DIMM slot not to be
populated. ii. Both Registered ECC DDR2 667MHz and 533 MHz DIMMs are supported;
however, you need to use the memory modules of the same speed and of the same type on
a motherboard. iii. For memory to work properly, you need to follow the restrictions listed
above. )
Optimized DIMM Population Configurations
Channel 0 Channel 1
Note 2: Due to OS limitations, some operating systems may not show more than
4 GB of memory.
Note 3: Due to memory allocation to system devices, memory remaining available
for operational use will be reduced when 4 GB of RAM is used. The reduction in
memory availability is disproportional. (Refer to the following Memory Availability
Table for details.
2-6
Page 27
Possible System Memory Allocation & Availability
Chapter 2: Installation
System DeviceSizePhysical Memory
Firmware Hub fl ash memory (System BIOS)1 MB3.99
Local APIC4 KB3.99
Area Reserved for the chipset2 MB3.99
I/O APIC (4 Kbytes)4 KB3.99
PCI Enumeration Area 1256 MB3.76
PCI Express (256 MB)256 MB3.51
PCI Enumeration Area 2 (if needed) -Aligned on 256MB boundary-
VGA Memory16 MB2.85
TSEG1 MB2.84
Memory available to OS and other applications 2.84
512 MB3.01
Remaining (-Available)
(4 GB Total System Memory)
Figure 2-2. Installing and Removing DIMMs
DDR2 DIMM
X7DCL-3/i
To R e move :
Use your thumbs to
gently push the re-
lease tabs near both
ends of the module
to release it from the
slot.
To I nstall : Insert module vertically and press
down until it snaps into place. Pay attention to the
alignment notch at the bottom.
Top View of DDR2 Slot
2-7
Page 28
X7DCL-3/X7DCL-i User's Manual
123
4
567
8
2-4 Control Panel Connectors/IO Ports
The I/O ports are color coded in conformance with the PC 99 specifi cation. See
Figure 2-3 below for the colors and locations of the various I/O ports.
Back Panel Connectors/IO Ports
X7DCL-3/i
Back Panel I/O Port Locations and Defi nitions
Back Panel Connectors
1. Keyboard (Purple)
2. PS/2 Mouse (Green)
3. Back Panel USB Port 0
4. Back Panel USB Port 1
5. COM Port 1 (Turquoise)
6. VGA Port (Blue)
7. Gigabit LAN 1
8. Gigabit LAN 2
(See Section 2-5 for details.)
2-8
Page 29
Chapter 2: Installation
Front Control Panel
JF1 contains header pins for various buttons and indicators that are normally
located on a control panel at the front of the chassis. These connectors are de-
signed specifi cally for use with Super Micro server chassis. See Figure 2- 4 for the
descriptions of the various control panel buttons and LED indicators. Refer to the
following section for descriptions and pin defi nitions.
JF1 Header Pins
1920
Ground
NMI
X7DCL-3/i
X
Power LED
HDD LED
NIC1 LED
NIC2 LED
OH/Fan Fail LED
PWR Fail LED
Ground
Ground
X
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Reset
PWR
2
1
Reset Button
Power Button
2-9
Page 30
X7DCL-3/X7DCL-i User's Manual
Front Control Panel Pin Defi nitions
NMI Button
The non-maskable interrupt button
header is located on pins 19 and 20
of JF1. Refer to the table on the right
for pin defi nitions.
Power LED
The Power LED connection is located
on pins 15 and 16 of JF1. Refer to the
table on the right for pin defi nitions.
NMI Button
Pin Defi nitions (JF1)
Pin# Defi nition
19Control
20Ground
Power LED
Pin Defi nitions (JF1)
Pin# Defi nition
15+5V
16Ground
X7DCL-3/i
2-10
A. NMI
B. PWR LED
Ground
B
Power LED
HDD LED
NIC1 LED
NIC2 LED
OH/Fan Fail LED
PWR Fail LED
Ground
Ground
1920
NMI
A
X
2
X
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Reset
Reset Button
Power Button
PWR
1
Page 31
HDD LED
Chapter 2: Installation
The HDD LED connection is located
on pins 13 and 14 of JF1. Attach a
hard drive LED cable here to display
disk activity (for any hard drives on
the system, including SAS, Serial
ATA and IDE). See the table on the
right for pin defi nitions.
NIC1/NIC2 LED Indicators
The NIC (Network Interface Control-
ler) LED connection for GLAN port1
is located on pins 11 and 12 of JF1
and the LED connection for GLAN
Port2 is on Pins 9 and 10. Attach the
NIC LED cables to display network
activity. Refer to the table on the right
for pin defi nitions.
HDD LED
Pin Defi nitions (JF1)
Pin# Defi nition
13+5V
14HD Active
GLAN1/2 LED
Pin Defi nitions (JF1)
Pin# Defi nition
9/11Vcc
10/12Ground
X7DCL-3/i
2-11
A. HDD LED
B. NIC1 LED
C. NIC2 LED
Ground
Power LED
HDD LED
A
B
NIC1 LED
NIC2 LED
C
OH/Fan Fail LED
PWR Fail LED
Ground
Ground
1920
NMI
X
2
X
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Reset
Reset Button
Power Button
PWR
1
Page 32
X7DCL-3/X7DCL-i User's Manual
Overheat/Fan Fail LED (OH)
Connect an LED to the OH/Fan Fail
connection on pins 7 and 8 of JF1
to provide advanced warnings of
chassis overheating or fan failure.
Refer to the table on the right for pin
defi nitions.
Power Fail LED
The Power Fail LED connection is
located on pins 5 and 6 of JF1. Re-
fer to the table on the right for pin
defi nitions.
OH/Fan Fail LED
Pin Defi nitions (JF1)
Pin# Defi nition
7Vcc
8Ground
OH/Fan Fail Indicator
Status
State Defi nition
OffNormal
OnOverheat
Flashing
Pin Defi nitions (JF1)
Pin# Defi nition
5Vcc
6Ground
Fan Fail
PWR Fail LED
X7DCL-3/i
2-12
A. OH/Fan Fail LED
B. PWR Supply Fail
Ground
X
Power LED
HDD LED
NIC1 LED
NIC2 LED
OH/Fan Fail LED
A
PWR Fail LED
B
Ground
Ground
1920
NMI
X
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Reset
Reset Button
Power Button
PWR
2
1
Page 33
Reset Button
The Reset Button connection is located
on pins 3 and 4 of JF1. Attach it to the
hardware reset switch on the computer
case. Refer to the table on the right for
pin defi nitions.
Power Button
The Power Button connection is located
on pins 1 and 2 of JF1. Momentarily
contacting both pins will power on/off
the system. This button can also be
configured to function as a suspend
button (with a setting in the BIOS - see
Chapter 4). To turn off the power when
set to suspend mode, press the button
for at least 4 seconds. Refer to the table
on the right for pin defi nitions.
Chapter 2: Installation
Reset Button
Pin Defi nitions (JF1)
Pin# Defi nition
3Reset
4Ground
Power Button
Pin Defi nitions (JF1)
Pin# Defi nition
1Signal
2+3V Standby
X7DCL-3/i
2-13
A. Reset Button
B. PWR Button
Ground
Power LED
HDD LED
NIC1 LED
NIC2 LED
OH/Fan Fail LED
PWR Fail LED
Ground
Ground
1920
NMI
X
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Reset
X
Reset Button
A
Power Button
PWR
2
1
B
Page 34
X7DCL-3/X7DCL-i User's Manual
2-5 Connecting Cables
ATX Power C onne ctor
A 24-pin main power supply connec-
tor is located at JPW2, and an 8-pin
CPU PWR connector is locatged at
JPW1 on the motherboard. These
power connectors meet the SSI EPS
12V specifi cation. See the table on
the right for pin defi nitions. For the
8-pin PWR (JPW1), refer to the item
below.
Processor Power
Connector
In addition to the Primary ATX power
connector, the 12V 8-pin CPU PWR
connector at JPW1 must also be con-
nected to provide adequate power to
your processors. See the table on the
right for pin defi nitions.
ATX Power 24-pin Connector
Pin Defi nitions
Pin# Defi nition Pin # Defi nition
13+3.3V1+3.3V
14-12V2+3.3V
15COM3COM
16PS_ON4+5V
17COM5COM
18COM6+5V
19COM7COM
20Res (NC)8PWR_OK
21+5V95VSB
22+5V10+12V
23+5V11+12V
24COM12+3.3V
12V 8-pin Power CPU
Connector
Pin Defi nitions
Pins Defi nition
1 through 4Ground
5 through 8+12V
Required Connection
A. 24-pin ATX PWR
B. 8-pin Processor PWR
CPU1
CPU1 VRM OH LED
LED5
JPWF1
JAR
KB/MS
USB0/1
COM1
VGA
8-Pin PWR
B
24-Pin PWR
A
DIMM2A
DIMM1A
DIMM2B
DIMM1B
DIMM2C
DIMM1C
SMB_PS
Fan 1
X7DCL-3/i
LAN1
JPL2
FAN6
VGA
CTRL
LAN
CTRL
FAN5
I-Button
LAN
CTRL
JPG1
SI/O
JWOR1
JKEY1
JI2C2
JWD1
Slot6 PCI-E x8
Slot5 PCI-E x8
JI2C1
Slot4 PCI-E x4(in x8 slot)
Slot3 PCI 33MHz
Slot2 PCI 33MHz
Slot1 PCI 33MHz
SIMLC
JWOL1
Intel
North Bridge
SP1
Buzzer
5100
System Status LED
Intel
ICH9R
South Bridge
SATA5
JBT1
BIOS
Battery
ITE
SAS-GPIO1
CTRL
SAS-GPIO0
USB4/5
JPA2
USB2/3
BPI2C
LED4
LAN2
JPL1
COM2
SATA-GPIO0
SATA4
SAS1
SAS0
SATA3
JD1
JP2
JP1
SATA-GPIO1
SATA2
SAS2
CPU2
Fan 2
LED6
CPU2 VRM OH LED
Fan 3
PWR LED
LED3
FP CTRL
JPA1
SATA1
SATA0
LED1
LSI
SAS
CTRL
SAS3
SAS4
Floppy
IDE
JL1
SAS6
SAS7
SAS5
Fan 4
2-14
Page 35
Chapter 2: Installation
Universal Serial Bus (USB)
There are six USB 2.0 (Universal Serial
Bus) ports/headers on the motherboard.
Two of them are Back Panel USB ports
(USB#0/1: JPUSB1), and the other
four are Front Panel USB connectors
(USB#2/3: JUSB2), or Front-Accessible
USB headers (USB#4/#5: JUSB3). See
the tables on the right for pin defi ni-
tions.
Back Panel USB (0/1)
Pin Defi nitions
Pin# Defi nitions
1+5V
2PO-
3PO+
4Ground
5N/A
Front Panel USB
Pin Defi nitions (USB2/3/4/5)
USB2/3
Pin # Defi nition
USB4/5
Pin # Defi nition
1+5V1+5V
2PO-2PO-
3PO+3PO+
4Ground4Ground
5Key5No connection
A. Backpanel USB 0/1
B. Front Panel USB 2/3
C. Front Panel USB 4/5
CPU1
CPU1 VRM OH LED
LED5
JPWF1
JAR
KB/MS
USB0/1
COM1
VGA
8-Pin PWR
A
24-Pin PWR
DIMM2A
DIMM1A
DIMM2B
DIMM1B
DIMM2C
DIMM1C
SMB_PS
Fan 1
X7DCL-3/i
LAN1
JPL2
COM2
CTRL
LAN
CTRL
FAN5
FAN6
I-Button
LAN
CTRL
VGA
JPG1
SI/O
JWOR1
JKEY1
JI2C2
JWD1
Slot6 PCI-E x8
Slot5 PCI-E x8
JI2C1
Slot4 PCI-E x4(in x8 slot)
Slot3 PCI 33MHz
Slot2 PCI 33MHz
Slot1 PCI 33MHz
SIMLC
JWOL1
Intel
North Bridge
SP1
Buzzer
5100
System Status LED
Intel
ICH9R
South Bridge
SATA5
JBT1
BIOS
Battery
ITE
SAS-GPIO1
CTRL
SAS-GPIO0
JPA2
C
LED4
USB4/5
B
USB2/3
BPI2C
LAN2
JPL1
SATA-GPIO0
SATA4
SAS1
SAS0
SATA3
JD1
JP2
JP1
SATA-GPIO1
SATA2
SAS3
SAS2
LSI
SAS
CTRL
CPU2
SATA1
SAS4
SAS5
SATA0
CPU2 VRM OH LED
PWR LED
LED3
JPA1
LED1
SAS6
SAS7
Fan 2
LED6
Fan 3
FP CTRL
Floppy
IDE
JL1
Fan 4
2-15
Page 36
X7DCL-3/X7DCL-i User's Manual
G
F
E
D
Fan Headers
The X7DCL-3/X7DCL-i has four chassis/
system fan headers (Fan3 to Fan6), and
two CPU Fans (Fans 1/2). All these fans
are 4-pin fans. However, Pins 1-3 of the fan
headers are backward compatible with the
traditional 3-pin fans. See the table on the
right for pin defi nitions. Note: The onboard
fan speeds are controlled by Thermal Man-
agement via BIOS Hardware Monitoring in
the Advanced Setting
. (The default setting
is Disabled.) Please use all 3-pin fans or
all 4-pin fans on the motherboard.
Chassis Intrusion
A Chassis Intrusion header is located at
JL1 on the motherboard. Attach an appro-
priate cable from the chassis to inform you
of a chassis intrusion when the chassis is
opened.
Fan Header
Pin Defi nitions (Fan1-6)
Pin# Defi nition
1Ground
2+12V
3Tachometer
4PWR Modulation
Chassis Intrusion
Pin Defi nitions (JL1)
Pin# Defi nition
1Intrusion Input
2Ground
CPU1
CPU2
SATA-GPIO1
SATA1
SATA2
LSI
SAS
CTRL
SAS3
SAS4
SATA0
SAS5
CPU1 VRM OH LED
CPU2 VRM OH LED
PWR LED
LED3
JPA1
LED1
SAS6
SAS7
LED5
A. Fan 1
B. Fan 2
C. Fan 3
D. Fan 4
E. Fan 5
F. Fan 6
G. Chassis Intrusion
Fan 2
LED6
B
Fan 3
C
FP CTRL
Floppy
IDE
JL1
Fan 4
JPWF1
JAR
KB/MS
USB0/1
COM1
VGA
8-Pin PWR
24-Pin PWR
DIMM2A
DIMM1A
DIMM2B
DIMM1B
DIMM2C
DIMM1C
SMB_PS
Fan 1
A
X7DCL-3/i
LAN1
JPL2
FAN6
VGA
CTRL
LAN
CTRL
FAN5
I-Button
LAN
CTRL
JPG1
SI/O
JWOR1
JKEY1
JI2C2
JWD1
Slot6 PCI-E x8
Slot5 PCI-E x8
JI2C1
Slot4 PCI-E x4(in x8 slot)
Slot3 PCI 33MHz
Slot2 PCI 33MHz
Slot1 PCI 33MHz
SIMLC
JWOL1
Intel
North Bridge
SP1
Buzzer
5100
System Status LED
JP2
JP1
Intel
ICH9R
South Bridge
BIOS
ITE
CTRL
LED4
USB4/5
SATA-GPIO0
SATA3
SATA4
SATA5
JBT1
JPA2
SAS-GPIO1
SAS-GPIO0
USB2/3
JD1
SAS2
SAS1
SAS0
Battery
BPI2C
LAN2
JPL1
COM2
2-16
Page 37
Chapter 2: Installation
ATX PS /2 Key boar d and
PS/2 Mouse Ports
The ATX PS/2 keyboard and the PS/2
mouse are located at JKM1. See the
table on the right for pin defi nitions.
(The mouse port is above the key-
board port.) See the table on the right
for pin defi nitions.
Serial Ports
COM1 is a connector located on the
IO Backpanel, and COM2 is a header
located at JCOM2. See the table on
the right for pin defi nitions.
PS/2 Keyboard and
Mouse Port Pin
Defi nitions
Pin# Defi nition
1Data
2NC
3Ground
4VCC
5Clock
6NC
Serial Port Pin Defi nitions
(COM1/COM2)
Pin # Defi nitionPin # Defi nition
1CD6DSR
2RD7 RTS
3TD8CTS
4DTR9RI
5Ground10NC
(Pin 10 is available on COM2
only. NC: No Connection.)
CPU1
CPU1 VRM OH LED
LED5
A. Keyboard/Mouse
B. COM1
C. COM2
JPWF1
JAR
8-Pin PWR
A
KB/MS
USB0/1
COM1
B
VGA
24-Pin PWR
DIMM2A
DIMM1A
DIMM2B
DIMM1B
DIMM2C
DIMM1C
SMB_PS
Fan 1
X7DCL-3/i
LAN1
JPL2
C
COM2
CTRL
LAN
CTRL
FAN5
FAN6
I-Button
LAN
CTRL
VGA
JPG1
SI/O
JWOR1
JKEY1
JI2C2
JWD1
Slot6 PCI-E x8
Slot5 PCI-E x8
JI2C1
Slot4 PCI-E x4(in x8 slot)
Slot3 PCI 33MHz
Slot2 PCI 33MHz
Slot1 PCI 33MHz
SIMLC
JWOL1
Intel
North Bridge
SP1
Buzzer
5100
System Status LED
Intel
ICH9R
South Bridge
SATA5
JBT1
BIOS
Battery
ITE
SAS-GPIO1
CTRL
SAS-GPIO0
USB4/5
JPA2
USB2/3
BPI2C
LED4
LAN2
JPL1
SATA-GPIO0
SATA4
SAS1
SAS0
SATA3
JD1
JP2
JP1
SATA-GPIO1
SATA2
SAS3
SAS2
LSI
SAS
CTRL
CPU2
SATA1
SAS4
SAS5
SATA0
CPU2 VRM OH LED
PWR LED
LED3
JPA1
LED1
SAS6
SAS7
Fan 2
LED6
Fan 3
FP CTRL
Floppy
IDE
JL1
Fan 4
2-17
Page 38
X7DCL-3/X7DCL-i User's Manual
Wake-On-Ring
The Wake-On-Ring header is lo-
cated at JWOR1. This feature allows
your computer to receive and be
"awakened" by an incoming call to
the modem when the system is in
the suspend state. See the table on
the right for pin defi nitions. You must
have a Wake-On-Ring card and cable
to use this feature.
Wake-On-LAN
The Wake-On-LAN header is located
at JWOL1 on the motherboard. See
the table on the right for pin defi ni-
tions. (You must have a LAN card
with a Wake-On-LAN connector, and
cable to use this feature.)
Wake-On-Ring
Pin Defi nitions
Pin# Defi nition
1Ground
2Wake-up
Wake-On-LAN
Pin Defi nitions
Pin# Defi nition
1+5V Standby
2Ground
3Wake-up
CPU1
CPU1 VRM OH LED
LED5
A. WOR
B. WOL
JPWF1
JAR
KB/MS
USB0/1
COM1
VGA
8-Pin PWR
24-Pin PWR
DIMM2A
DIMM1A
DIMM2B
DIMM1B
DIMM2C
DIMM1C
SMB_PS
Fan 1
X7DCL-3/i
LAN1
JPL2
FAN6
VGA
CTRL
LAN
CTRL
FAN5
I-Button
LAN
CTRL
JPG1
SI/O
A
JWOR1
JKEY1
JI2C2
JWD1
Slot6 PCI-E x8
Slot5 PCI-E x8
JI2C1
Slot4 PCI-E x4(in x8 slot)
Slot3 PCI 33MHz
Slot2 PCI 33MHz
Slot1 PCI 33MHz
SIMLC
JWOL1
Intel
5100
North Bridge
SP1
Buzzer
B
System Status LED
Intel
ICH9R
South Bridge
SATA5
JBT1
BIOS
Battery
ITE
SAS-GPIO1
CTRL
SAS-GPIO0
USB4/5
JPA2
USB2/3
BPI2C
LED4
LAN2
JPL1
COM2
SATA-GPIO0
SATA4
SAS1
SAS0
SATA3
JD1
JP2
JP1
SATA-GPIO1
SATA2
SAS2
CPU2
Fan 2
LED6
CPU2 VRM OH LED
Fan 3
PWR LED
LED3
FP CTRL
JPA1
SATA1
SATA0
LED1
LSI
SAS
CTRL
SAS3
SAS4
Floppy
IDE
JL1
SAS6
SAS7
SAS5
Fan 4
2-18
Page 39
GLAN 1/2 (Giga-bit Ethernet
Ports)
Two G-bit Ethernet ports are located
at JLAN1 and JLAN2 on the I/O
backplane. These ports accept RJ45
type cables.
Power LED/Speaker
On the JD1 header, pins 1-3 are for
a power LED, and pins 4-7 are for
the speaker. See the table on the
right for speaker pin defi nitions. Note:
The speaker connector pins are for
use with an external speaker. If you
wish to use the onboard speaker, you
should close pins 6-7 with a jumper.
Chapter 2: Installation
GLAN1
Speaker Connector
Pin Setting Defi nition
Pins 6-7Internal Speaker
Pins 4-7External Speaker
GLAN2
A. GLAN1
B. GLAN2
C. PWR LED/Speaker
CPU1
CPU1 VRM OH LED
LED5
JPWF1
JAR
KB/MS
USB0/1
COM1
VGA
8-Pin PWR
24-Pin PWR
DIMM2A
DIMM1A
DIMM2B
DIMM1B
DIMM2C
DIMM1C
SMB_PS
Fan 1
X7DCL-3/i
A
LAN1
JPL2
COM2
CTRL
LAN
B
CTRL
FAN5
FAN6
I-Button
LAN
CTRL
VGA
JPG1
SI/O
JWOR1
JKEY1
JI2C2
JWD1
Slot6 PCI-E x8
Slot5 PCI-E x8
JI2C1
Slot4 PCI-E x4(in x8 slot)
Slot3 PCI 33MHz
Slot2 PCI 33MHz
Slot1 PCI 33MHz
SIMLC
JWOL1
Intel
North Bridge
SP1
Buzzer
5100
System Status LED
Intel
ICH9R
South Bridge
SATA5
JBT1
BIOS
Battery
ITE
SAS-GPIO1
CTRL
SAS-GPIO0
USB4/5
JPA2
USB2/3
BPI2C
LED4
LAN2
JPL1
SATA-GPIO0
SATA4
C
SAS1
SAS0
SATA3
JD1
JP2
JP1
SATA-GPIO1
SATA2
SAS3
SAS2
LSI
SAS
CTRL
CPU2
SATA1
SAS4
SAS5
SATA0
CPU2 VRM OH LED
PWR LED
LED3
JPA1
LED1
SAS6
SAS7
Fan 2
LED6
Fan 3
FP CTRL
Floppy
IDE
JL1
Fan 4
2-19
Page 40
X7DCL-3/X7DCL-i User's Manual
Alarm Reset
If three power supplies are installed,
the system will notify you when any of
the three power modules fails. Con-
nect JAR1 to a micro-switch to turn
off the alarm that is activated when a
power module fails. See the table on
the right for pin defi nitions.
PWR Supply Failure/PWR
Fault Detect
The system can notify you in the
event of a power supply failure. This
feature is available when three power
supply units are installed in the chas-
sis with one acting as a backup. If you
only have one or two power supply
units installed, you should disable
this (the default setting) with JPWF1
to prevent false alarms.
Alarm Reset
Pin Defi nitions
Pin Setting Defi nition
Pin 1Ground
Pin 2+5V
PWR Supply PWR Fault
Connector
Jumper Setting Defi nition
OnEnabled
OffDisabled (Default)
B
CPU1
CPU2
SATA-GPIO1
SATA1
SATA2
LSI
SAS
CTRL
SAS3
SAS4
SATA0
SAS5
CPU1 VRM OH LED
CPU2 VRM OH LED
PWR LED
LED3
JPA1
LED1
SAS6
SAS7
LED5
A. Alarm Reset
B. PWR Fault
Fan 2
LED6
Fan 3
FP CTRL
Floppy
IDE
JL1
Fan 4
JPWF1
JAR
KB/MS
USB0/1
COM1
VGA
A
8-Pin PWR
24-Pin PWR
DIMM2A
DIMM1A
DIMM2B
DIMM1B
DIMM2C
DIMM1C
SMB_PS
Fan 1
X7DCL-3/i
LAN1
JPL2
FAN6
VGA
CTRL
LAN
CTRL
FAN5
I-Button
LAN
CTRL
JPG1
SI/O
JWOR1
JKEY1
JI2C2
JWD1
Slot6 PCI-E x8
Slot5 PCI-E x8
JI2C1
Slot4 PCI-E x4(in x8 slot)
Slot3 PCI 33MHz
Slot2 PCI 33MHz
Slot1 PCI 33MHz
SIMLC
JWOL1
Intel
North Bridge
SP1
Buzzer
5100
System Status LED
JP2
JP1
Intel
ICH9R
South Bridge
BIOS
ITE
CTRL
LED4
USB4/5
SATA-GPIO0
SATA3
SATA4
SATA5
JBT1
JPA2
SAS-GPIO1
SAS-GPIO0
USB2/3
JD1
SAS2
SAS1
SAS0
Battery
BPI2C
LAN2
JPL1
COM2
2-20
Page 41
VGA Connector
E
D
A VGA connector (JVGA) is located next
to the COM1 port on the IO backplane.
Refer to the board layout below for the
location.
GPIO Headers
Chapter 2: Installation
Four GPIO (Serial Links General Purpose
Input/Output) headers are located at J7,
J8, J9, J10 on the motherboard. These
headers are used to communicate with
the Seriel-Links System Monitoring chip
on the backplane. J7 and J8 are used to
monitor SATA activities, J9 and J10 are
used to monitor SAS connections. See
the table on the right for pin defi nitions.
Refer to the board layout below for the
locations of the headers.
(J9, J10: X7DCL-3 Only.)
JPWF1
JAR
KB/MS
USB0/1
COM1
A
VGA
8-Pin PWR
24-Pin PWR
DIMM2A
DIMM1A
DIMM2B
DIMM1B
DIMM2C
DIMM1C
X7DCL-3/i
LAN1
JPL2
COM2
CTRL
LAN
CTRL
FAN5
FAN6
I-Button
LAN
CTRL
VGA
JPG1
SI/O
JWOR1
JKEY1
JI2C2
JWD1
JI2C1
Slot6 PCI-E x8
Slot5 PCI-E x8
Slot4 PCI-E x4(in x8 slot)
Slot3 PCI 33MHz
Slot2 PCI 33MHz
JWOL1
Slot1 PCI 33MHz
SIMLC
LAN2
JPL1
Intel
North Bridge
SP1
Buzzer
5100
System Status LED
LED4
SMB_PS
BIOS
CTRL
ITE
Intel
ICH9R
South Bridge
USB4/5
BPI2C
JBT1
Battery
JPA2
Fan 1
B
SAS-GPIO1
SAS-GPIO0
USB2/3
SATA5
SATA-GPIO0
SATA4
SAS1
SAS0
SATA3
JD1
JP2
JP1
C
SATA-GPIO1
SATA2
SAS3
SAS2
LSI
SAS
CTRL
Serial-Links GPIO
Pin Defi nitions
Pin# Defi nition Pin Defi nition
1NC2 NC
3Ground4DATA Out
5Load6Ground
7Clock8NC
Note: NC= No Connections
CPU1 VRM OH LED
LED5
A. VGA
B. J7: SATA_GPIO#0
C. J8: SATA_GPIO#1
CPU1
D. J9: SAS_GPIO#0
E. J10: SAS_GPIO#1
CPU2
Fan 2
LED6
CPU2 VRM OH LED
Fan 3
PWR LED
LED3
FP CTRL
JPA1
SATA1
SATA0
LED1
Floppy
IDE
JL1
SAS6
SAS7
SAS5
SAS4
Fan 4
2-21
Page 42
X7DCL-3/X7DCL-i User's Manual
Power SMB (I2 C) Connector
Power SMB (I2 C) Connector (JPI2C1)
monitors the status of the power supply,
fan and system temperature. See the
table on the right for pin defi nitions.
BP PWR SMB (I2 C) Connector
Backplane Power SMB (I2 C) Connector
(J5) monitors power supply of backplane
IO connectors. See the table on the right
for pin defi nitions.
PWR SMB
Pin Defi nitions
Pin# Defi nition
1Clock
2Data
3PWR Fail
4Ground
5+3.3V
BP PWR SMB
Pin Defi nitions
Pin# Defi nition
1SMB_DAT_ICH_EXT
2Ground
3SMB_CLK_ICH_EXT
5No Connection
CPU1
CPU1 VRM OH LED
LED5
A. PWR SMB
B. Backplane PWR SMB
JPWF1
JAR
KB/MS
USB0/1
COM1
VGA
8-Pin PWR
24-Pin PWR
DIMM2A
DIMM1A
DIMM2B
DIMM1B
DIMM2C
DIMM1C
SMB_PS
Fan 1
A
X7DCL-3/i
LAN1
JPL2
COM2
CTRL
LAN
CTRL
FAN5
FAN6
I-Button
LAN
CTRL
VGA
S I/O
Slot6 PCI-E x8
Slot5 PCI-E x8
JI2C2
JI2C1
Slot4 PCI-E x4(in x8 slot)
JPG1
JWD1
JKEY1
JWOR1
Slot3 PCI 33MHz
Slot2 PCI 33MHz
Slot1 PCI 33MHz
SIMLC
JWOL1
Intel
North Bridge
SP1
Buzzer
5100
System Status LED
Intel
ICH9R
South Bridge
SATA5
JBT1
BIOS
Battery
ITE
SAS-GPIO1
CTRL
SAS-GPIO0
USB4/5
BPI2C
JPA2
USB2/3
B
LED4
LAN2
JPL1
SATA-GPIO0
SATA4
SAS1
SAS0
SATA3
JD1
JP2
JP1
SATA-GPIO1
SATA2
SAS3
SAS2
LSI
SAS
CTRL
CPU2
SATA1
SAS4
SAS5
SATA0
CPU2 VRM OH LED
PWR LED
LED3
JPA1
LED1
SAS6
SAS7
Fan 2
LED6
Fan 3
FP CTRL
Floppy
IDE
JL1
Fan 4
2-22
Page 43
Chapter 2: Installation
Keylock
The keyboard lock connection is desig-
nated JKEY1. Utilizing this header allows
you to inhibit any actions made on the
keyboard, effectively "locking" it.
Keylock
Pin Defi nitions
Pin# Defi nition
1Ground
2Keylock R-N
VGA
KB/MS
USB0/1
COM1
LAN1
LAN2
CPU1
CPU1 VRM OH LED
LED5
A. Keylock
JPWF1
JAR
8-Pin PWR
DIMM2A
DIMM1A
DIMM2B
DIMM1B
DIMM2C
DIMM1C
24-Pin PWR
SMB_PS
Fan 1
X7DCL-3/i
SATA-GPIO0
SATA4
SAS1
SAS0
SATA3
JD1
JP2
JP1
SATA-GPIO1
SATA2
SAS3
SAS2
LSI
SAS
CTRL
CPU2
SATA1
SAS4
SAS5
SATA0
CPU2 VRM OH LED
PWR LED
LED3
JPA1
LED1
SAS6
SAS7
Fan 2
LED6
Fan 3
FP CTRL
Floppy
IDE
JL1
Fan 4
JPL2
LAN
CTRL
FAN5
FAN6
I-Button
LAN
CTRL
JPL1
VGA
CTRL
JPG1
SI/O
COM2
A
JWOR1
JKEY1
JI2C2
JWD1
Slot6 PCI-E x8
Slot5 PCI-E x8
JI2C1
Slot4 PCI-E x4(in x8 slot)
Slot3 PCI 33MHz
Slot2 PCI 33MHz
Slot1 PCI 33MHz
SIMLC
JWOL1
Intel
North Bridge
SP1
Buzzer
5100
System Status LED
Intel
ICH9R
South Bridge
SATA5
JBT1
BIOS
Battery
ITE
SAS-GPIO1
CTRL
SAS-GPIO0
USB4/5
JPA2
USB2/3
BPI2C
LED4
2-23
Page 44
X7DCL-3/X7DCL-i User's Manual
Connector
Pins
Jumper
Cap
Setting
2-6 Jumper Settings
Explanation of
Jumpers
To modify the operation of the
motherboard, jumpers can be used
to choose between optional settings.
Jumpers create shorts between two pins
to change the function of the connector.
Pin 1 is identifi ed with a square solder
pad on the printed circuit board. See
the motherboard layout pages for jumper
locations.
Note: On two pin jumpers, "Closed"
means the jumper is on and "Open"
means the jumper is off the pins.
3 2 1
3 2 1
Pin 1-2 short
GLAN Enable/Disable
JPL1/JPL2 enable or disable GLAN
Port1/GLAN Port2 on the mother-
board. See the table on the right for
jumper settings. The default setting is
Enabled.
JPWF1
JAR
KB/MS
USB0/1
COM1
VGA
8-Pin PWR
24-Pin PWR
DIMM2A
DIMM1A
DIMM2B
DIMM1B
DIMM2C
DIMM1C
X7DCL-3/i
B
LAN1
JPL2
LAN2
LAN
CTRL
FAN5
FAN6
I-Button
LAN
CTRL
Slot6 PCI-E x8
A
JWOR1
JKEY1
JI2C2
JWD1
JI2C1
Slot5 PCI-E x8
Slot4 PCI-E x4(in x8 slot)
Slot3 PCI 33MHz
Slot2 PCI 33MHz
JWOL1
Slot1 PCI 33MHz
SIMLC
JPL1
VGA
CTRL
JPG1
SI/O
COM2
Intel
North Bridge
SP1
Buzzer
5100
System Status LED
SMB_PS
LED4
BIOS
CTRL
ITE
Intel
ICH9R
South Bridge
USB4/5
BPI2C
JBT1
Battery
JPA2
Fan 1
SAS-GPIO1
SAS-GPIO0
USB2/3
SATA5
SATA4
SAS0
JP2
SATA-GPIO0
SATA3
JD1
SAS2
SAS1
JP1
SATA-GPIO1
SATA2
SAS3
SAS
CTRL
GLAN Enable
Jumper Settings
Pin# Defi nition
1-2Enabled (default)
2-3Disabled
CPU1 VRM OH LED
LED5
A. GLAN Port1 Enable
B. GLAN Port2 Enable
CPU1
CPU2
Fan 2
LED6
CPU2 VRM OH LED
Fan 3
PWR LED
LED3
FP CTRL
JPA1
SATA1
SATA0
LED1
LSI
SAS4
Floppy
IDE
JL1
SAS6
SAS7
SAS5
Fan 4
2-24
Page 45
Chapter 2: Installation
CMOS Clear
JBT1 is used to clear CMOS. Instead of pins, this "jumper" consists of contact
pads to prevent the accidental clearing of CMOS. To clear CMOS, use a metal
object such as a small screwdriver to touch both pads at the same time to short
the connection. Always remove the AC power cord from the system before clear-
ing CMOS.
Note: For an ATX power supply, you must completely shut down the system,
remove the AC power cord and then short JBT1 to clear CMOS.
Watch Dog Enable/Disable
Watch Dog
Watch Dog is a system monitor that can reboot
the system when a software application hangs.
Close pins 1-2 to reset the system if an applica-
tion hangs. Close pins 2-3 to generate a non-
maskable interrupt signal for the application that
hangs. See the table on the right for jumper set-
tings. Watch Dog must also be enabled in the
BIOS.
Jumper Settings
Jumper Setting Defi nition
Pins 1-2Reset
(default)
Pins 2-3NMI
OpenDisabled
CPU1
CPU1 VRM OH LED
LED5
A. Clear CMOS
B. Watch Dog Enable
JPWF1
JAR
KB/MS
USB0/1
COM1
VGA
8-Pin PWR
24-Pin PWR
DIMM2A
DIMM1A
DIMM2B
DIMM1B
DIMM2C
DIMM1C
SMB_PS
Fan 1
X7DCL-3/i
LAN1
JPL2
COM2
CTRL
LAN
CTRL
FAN5
FAN6
I-Button
LAN
CTRL
VGA
JPG1
SI/O
JWOR1
JKEY1
JI2C2
JWD1
JI2C1
B
Slot6 PCI-E x8
Slot5 PCI-E x8
Slot4 PCI-E x4(in x8 slot)
Slot3 PCI 33MHz
Slot2 PCI 33MHz
Slot1 PCI 33MHz
SIMLC
JWOL1
Intel
North Bridge
SP1
Buzzer
5100
System Status LED
Intel
ICH9R
South Bridge
SATA5
A
JBT1
BIOS
Battery
ITE
SAS-GPIO1
CTRL
SAS-GPIO0
USB4/5
JPA2
USB2/3
BPI2C
LED4
LAN2
JPL1
SATA-GPIO0
SATA4
SAS1
SAS0
SATA3
JD1
JP2
JP1
SATA-GPIO1
SATA2
SAS3
SAS2
LSI
SAS
CTRL
CPU2
SATA1
SAS4
SAS5
SATA0
CPU2 VRM OH LED
PWR LED
LED3
JPA1
LED1
SAS6
SAS7
Fan 2
LED6
Fan 3
FP CTRL
Floppy
IDE
JL1
Fan 4
2-25
Page 46
X7DCL-3/X7DCL-i User's Manual
VGA Enable/Disable
JPG1 allows you to e n a b l e or disable the
VGA port. The default position is on pins
1 and 2 to enable VGA. See the table on
the right for jumper settings.
I2C Bus to PCI/PCI-Exp. Slots
Jumpers JPI2C1/JPI2C2 allow you to
connect the System Management Bus
2
(I
C) to PCI/PCI-Exp. slots. The default
setting is Open to disable the connec-
tion. See the table on the right for jumper
settings.
VGA Enable/Disable
Jumper Settings
Both Jumpers Defi nition
Pins 1-2Enabled (Default)
Pins 2-3Disabled
I2C to PCI/PCI-Exp. Slots
Jumper Settings
Jumper Setting Defi nition
ClosedEnabled
OpenDisabled (Default)
CPU1
CPU1 VRM OH LED
LED5
A. VGA Enabled
2
C1
B. JPI
2
C2
C. JPI
JPWF1
JAR
KB/MS
USB0/1
COM1
VGA
8-Pin PWR
24-Pin PWR
DIMM2A
DIMM1A
DIMM2B
DIMM1B
DIMM2C
DIMM1C
SMB_PS
Fan 1
X7DCL-3/i
LAN1
JPL2
FAN6
VGA
CTRL
LAN
CTRL
FAN5
I-Button
LAN
CTRL
C
JPG1
SI/O
JWOR1
JKEY1
JI2C2
JWD1
B
JI2C1
A
Slot6 PCI-E x8
Slot5 PCI-E x8
Slot4 PCI-E x4(in x8 slot)
Slot3 PCI 33MHz
Slot2 PCI 33MHz
Slot1 PCI 33MHz
SIMLC
JWOL1
Intel
North Bridge
SP1
Buzzer
5100
System Status LED
Intel
ICH9R
South Bridge
SATA5
JBT1
BIOS
Battery
ITE
SAS-GPIO1
CTRL
SAS-GPIO0
USB4/5
JPA2
USB2/3
BPI2C
LED4
LAN2
JPL1
COM2
SATA-GPIO0
SATA4
SAS1
SAS0
SATA3
JD1
JP2
JP1
SATA-GPIO1
SATA2
SAS2
CPU2
Fan 2
LED6
CPU2 VRM OH LED
Fan 3
PWR LED
LED3
FP CTRL
JPA1
SATA1
SATA0
LED1
LSI
SAS
CTRL
SAS3
SAS4
Floppy
IDE
JL1
SAS6
SAS7
SAS5
Fan 4
2-26
Page 47
SAS Enable/Disable
Chapter 2: Installation
JPA1 allows you to enable or disable
SAS Connectors. The default position is
on pins 1 and 2 to enable SAS. See the
table on the right for jumper settings.
(Note: This feature is available on the
X7DCL-3 only.)
Software RAID Enable
JPA2 allows you to select the SAS RAID
mode. You can use either Software
RAID or IT RAID. Close this jumper to
use Software RAID (Default). Set this
jumper to open to use the IT RAID mode.
Contact Tech. Support at Supermicro for
more information. See the table on the
right for jumper settings.
SAS Enable/Disable
Jumper Settings
Jumper Settings Defi nition
Pins 1-2Enabled (Default)
Pins 2-3Disabled
Software RAID
Jumper Settings
Jumper Settings Defi nition
Close (Default)Software RAID Enabled
Open (Note)IT Mode Enabled
(Note: Also contact tech support at Super Micro for
further instructions.)
(Note: This feature is available on the
X7DCL-3 only.)
JPWF1
JAR
KB/MS
USB0/1
COM1
VGA
8-Pin PWR
24-Pin PWR
DIMM2A
DIMM1A
DIMM2B
DIMM1B
DIMM2C
DIMM1C
X7DCL-3/i
LAN1
JPL2
COM2
FAN6
CTRL
LAN
CTRL
FAN5
I-Button
LAN
CTRL
VGA
SI/O
JPG1
JWOR1
JKEY1
JI2C2
JWD1
JI2C1
Slot6 PCI-E x8
Slot5 PCI-E x8
Slot4 PCI-E x4(in x8 slot)
Slot3 PCI 33MHz
Slot2 PCI 33MHz
JWOL1
Slot1 PCI 33MHz
SIMLC
LAN2
JPL1
Intel
North Bridge
SP1
Buzzer
5100
System Status LED
LED4
SMB_PS
BIOS
CTRL
ITE
Intel
ICH9R
South Bridge
JBT1
Battery
USB4/5
BPI2C
JPA2
Fan 1
SAS-GPIO1
SAS-GPIO0
USB2/3
B
SATA5
SATA-GPIO0
SATA4
SAS1
SAS0
JD1
JP2
SATA3
SAS2
JP1
SATA-GPIO1
SATA2
SAS3
LSI
SAS
CTRL
CPU1
CPU2
SATA1
SAS4
SATA0
SAS5
CPU1 VRM OH LED
CPU2 VRM OH LED
PWR LED
LED3
JPA1
LED1
SAS6
SAS7
LED5
A. SAS Enabled
B. Software RAID Enable
Fan 2
LED6
Fan 3
A
FP CTRL
Floppy
IDE
JL1
Fan 4
2-27
Page 48
X7DCL-3/X7DCL-i User's Manual
2-7 Onboard LED Indicators
GLAN LEDs
There are two GLAN ports on the moth-
erboard. Each Gigabit Ethernet LAN port
has two LEDs. The yellow LED indicates
activity, while the power LED may be
green, orange or off to indic ate the speed
of the connection. See the tables at right
for more information.
Onboard Power LED (LED3)
An Onboard Power LED is located at
LED3 on the motherboard. When this
LED is lit, the system is on. Be sure
to turn off the system and unplug the
power cord before removing or installing
components. See the layout below for the
LED location.
Link
LED
Activity
LED
Rear View
(when viewing from the back of the chassis.)
GLAN Activity Indicator
Settings
Color Status Defi nition
YellowFlashingLAN Active
GLAN Link Indicator
Settings
LED Color Defi nition
OffNo Connection or 10 Mbps
Green100 Mbps
Amber1 Gbps
CPU1
CPU1 VRM OH LED
LED5
A. GLAN Port1 LEDs
B. GLAN Port2 LEDs
C. Onboard PWR LED
JPWF1
JAR
KB/MS
USB0/1
COM1
VGA
8-Pin PWR
24-Pin PWR
DIMM2A
DIMM1A
DIMM2B
DIMM1B
DIMM2C
DIMM1C
SMB_PS
Fan 1
X7DCL-3/i
A
LAN1
JPL2
LAN
B
LAN2
JPL1
COM2
FAN6
VGA
CTRL
CTRL
FAN5
I-Button
LAN
CTRL
JPG1
SI/O
JWOR1
JKEY1
JI2C2
JWD1
Slot6 PCI-E x8
Slot5 PCI-E x8
JI2C1
Slot4 PCI-E x4(in x8 slot)
Slot3 PCI 33MHz
Slot2 PCI 33MHz
Slot1 PCI 33MHz
SIMLC
JWOL1
Intel
North Bridge
SP1
Buzzer
5100
System Status LED
Intel
ICH9R
South Bridge
SATA5
JBT1
BIOS
Battery
ITE
SAS-GPIO1
CTRL
SAS-GPIO0
USB4/5
JPA2
USB2/3
BPI2C
LED4
SATA-GPIO0
SATA4
SAS1
SAS0
SATA3
JD1
JP2
JP1
SATA-GPIO1
SATA2
SAS2
CPU2
Fan 2
LED6
CPU2 VRM OH LED
Fan 3
C
PWR LED
LED3
FP CTRL
JPA1
SATA1
SATA0
LED1
LSI
SAS
CTRL
SAS3
SAS4
Floppy
IDE
JL1
SAS6
SAS7
SAS5
Fan 4
2-28
Page 49
Chapter 2: Installation
System Status LED (LED4)
A Status LED Indicator is located at
LED4 on the motherboard. This LED dis-
plays different colors to show the status
of the system. Refer to the table on the
right for system status. See the layout
below for the LED location.
CPU_VRM Overheating LED
Indicators (LED5/LED6)
Two CPU_VRM Overheat LEDs are locat-
e d a t L E D 5 a n d L E D 6 o n t h e m o t h e r b o a r d .
These LEDs provide indications for
CPU_VRM Overheating. Refer to the
table on the right for LED5 and LED6
settings. See the layout below for the
LED locations.
Status LED Indicator
Settings
LED Color Defi nition
GreenPower On, system: normal
RedPWR on, PWR problem(s)
occur(s) or the 3rd PWR
not properly installed
YellowSystem Off, AC PWR:
connected
CPU_VRM Overheat LED Indicator
Settings
LED# Description
LED5: OnCPU1_VRM Overheating
LED6: OnCPU2_VRM Overheating
A. LED4: System Status LED
B. LED5: CPU1_VRM OH LED
C. LED6: CPU2_VRM OH LED
CPU1
B
CPU1 VRM OH LED
LED5
JPWF1
JAR
KB/MS
USB0/1
COM1
VGA
8-Pin PWR
24-Pin PWR
DIMM2A
DIMM1A
DIMM2B
DIMM1B
DIMM2C
DIMM1C
SMB_PS
Fan 1
X7DCL-3/i
LAN1
JPL2
COM2
CTRL
LAN
CTRL
FAN5
FAN6
I-Button
LAN
CTRL
VGA
JPG1
SI/O
JWOR1
JKEY1
JI2C2
JWD1
Slot6 PCI-E x8
Slot5 PCI-E x8
JI2C1
Slot4 PCI-E x4(in x8 slot)
Slot3 PCI 33MHz
Slot2 PCI 33MHz
Slot1 PCI 33MHz
SIMLC
JWOL1
Intel
North Bridge
SP1
Buzzer
5100
System Status LED
Intel
ICH9R
South Bridge
SATA5
JBT1
BIOS
Battery
ITE
SAS-GPIO1
CTRL
USB4/5
SAS-GPIO0
JPA2
USB2/3
BPI2C
A
LED4
LAN2
JPL1
SATA-GPIO0
SATA4
SAS1
SAS0
SATA3
JD1
JP2
JP1
SATA-GPIO1
SATA2
SAS3
SAS2
LSI
SAS
CTRL
CPU2
SATA1
SAS4
Fan 2
LED6
CPU2 VRM OH LED
C
Fan 3
PWR LED
LED3
FP CTRL
JPA1
SATA0
LED1
Floppy
IDE
JL1
SAS6
SAS7
SAS5
Fan 4
2-29
Page 50
X7DCL-3/X7DCL-i User's Manual
SAS LED Indicator (LED1)
A SAS LED is located at LED1 on the
motherboard. This LED indicates the status
of SAS connections. Refer to the table on
the right for LED1 settings. See the layout
below for the LED location.
(Available on the X7DCL-3 only)
SAS LED Indicator
Settings
LED# Description
LED1: OnSAS: Active
LED1: OffSAS: Not Active
A. LED1: SAS LED
CPU1
CPU1 VRM OH LED
LED5
JPWF1
JAR
KB/MS
USB0/1
COM1
VGA
8-Pin PWR
24-Pin PWR
DIMM2A
DIMM1A
DIMM2B
DIMM1B
DIMM2C
DIMM1C
SMB_PS
Fan 1
X7DCL-3/i
LAN1
JPL2
FAN6
VGA
CTRL
LAN
CTRL
FAN5
I-Button
LAN
CTRL
JPG1
SI/O
JWOR1
JKEY1
JI2C2
JWD1
Slot6 PCI-E x8
Slot5 PCI-E x8
JI2C1
Slot4 PCI-E x4(in x8 slot)
Slot3 PCI 33MHz
Slot2 PCI 33MHz
Slot1 PCI 33MHz
SIMLC
JWOL1
Intel
North Bridge
SP1
Buzzer
5100
System Status LED
Intel
ICH9R
South Bridge
SATA5
JBT1
BIOS
Battery
ITE
SAS-GPIO1
CTRL
SAS-GPIO0
USB4/5
JPA2
USB2/3
BPI2C
LED4
LAN2
JPL1
COM2
SATA-GPIO0
SATA4
SAS1
SAS0
SATA3
JD1
JP2
JP1
SATA-GPIO1
SATA2
SAS2
CPU2
Fan 2
LED6
CPU2 VRM OH LED
Fan 3
PWR LED
LED3
FP CTRL
JPA1
A
SATA1
SATA0
LED1
LSI
SAS
CTRL
SAS3
SAS4
Floppy
IDE
JL1
SAS6
SAS7
SAS5
Fan 4
2-30
Page 51
Chapter 2: Installation
2-8 Floppy Drive, SIMLC IPMI and Hard Disk Drive
Connections
Note the following when connecting the fl oppy and hard disk drive cables:
• The fl oppy disk drive cable has seven twisted wires.
• A red mark on a wire typically designates the location of pin 1.
Floppy Drive Connector
Floppy Connector
The fl oppy connector is located at
JFDD1. See the table below for pin
defi nitions.
JPWF1
KB/MS
USB0/1
COM1
VGA
JAR
8-Pin PWR
DIMM2A
DIMM1A
DIMM2B
DIMM1B
DIMM2C
DIMM1C
24-Pin PWR
X7DCL-3/i
LAN1
JPL2
LAN2
LAN
CTRL
FAN5
FAN6
I-Button
LAN
CTRL
Slot6 PCI-E x8
JPL1
VGA
CTRL
SI/O
COM2
Slot5 PCI-E x8
JI2C2
JI2C1
Slot4PCI-Ex4(inx8slot)
JPG1
JWOR1
JKEY1
Slot3 PCI 33MHz
Slot2 PCI 33MHz
JWD1
JWOL1
Slot1 PCI 33MHz
SIMLC
Intel
North Bridge
SP1
Buzzer
5100
System Status LED
LED4
SMB_PS
BIOS
ITE
CTRL
Intel
ICH9R
South Bridge
USB4/5
Fan 1
SATA-GPIO0
SATA3
SATA4
SATA5
JBT1
JD1
Battery
SAS-GPIO1
SAS-GPIO0
JPA2
USB2/3
SAS2
SAS1
SAS0
BPI2C
JP2
JP1
SATA-GPIO1
SATA2
SAS3
CTRL
Pin# Defi nition Pin # Defi nition
1Ground2FDHDIN
3Ground4Reserved
5Key6FDEDIN
7Ground8Index
9Ground10Motor Enable
11Ground12Drive Select B
13Ground14Drive Select B
15Ground16Motor Enable
17Ground18DIR
19Ground20STEP
21Ground22Write Data
23Ground24Write Gate
25Ground26Track 00
27Ground28Write Protect
29Ground30Read Data
31Ground32Side 1 Select
33Ground34Diskette
CPU1 VRM OH LED
LED5
A. Floppy Disk Drive
CPU1
CPU2
Fan 2
LED6
CPU2 VRM OH LED
Fan 3
PWR LED
LED3
FP CTRL
A
JPA1
SATA1
SATA0
LED1
LSI
SAS
SAS4
Floppy
IDE
JL1
SAS6
SAS7
SAS5
Fan 4
Pin Defi nitions (Floppy)
2-31
Page 52
X7DCL-3/X7DCL-i User's Manual
IDE Connector
An IDE Connector is located at JIDE1
on the motherboard. This motherboard
uses the ITE IT8213F Controller. An
IDE Driver is required for the IDE drive
to function properly. See the table on
the right for pin defi nitions.
SIMLC IPMI Slot
A Low Profile SIMLC IPMI Slot is
located on the motherboard. Refer
to the layout below for the IPMI Slot
location.
IDE Drive Connector
Pin Defi nitions
Pin# Defi nition Pin # Defi nition
1Reset IDE2Ground
3Host Data 74Host Data 8
5Host Data 66Host Data 9
7Host Data 58Host Data 10
9Host Data 410Host Data 11
11Host Data 312Host Data 12
13Host Data 214Host Data 13
15Host Data 116Host Data 14
17Host Data 018Host Data 15
19Ground20Key
21DRQ322Ground
23I/O Write24Ground
25I/O Read26Ground
27IOCHRDY28BALE
29DACK330Ground
31IRQ1432IOCS16
33Addr134Ground
35Addr036Addr2
37Chip Select 038Chip Select 1
39Activity40Ground
A. IDE
B. SIMLC
CPU1
CPU1 VRM OH LED
LED5
JPWF1
JAR
KB/MS
USB0/1
COM1
VGA
8-Pin PWR
24-Pin PWR
DIMM2A
DIMM1A
DIMM2B
DIMM1B
DIMM2C
DIMM1C
SMB_PS
Fan 1
X7DCL-3/i
LAN1
JPL2
FAN6
VGA
CTRL
LAN
CTRL
FAN5
I-Button
LAN
CTRL
JPG1
SI/O
JWOR1
JKEY1
JI2C2
JWD1
Slot6 PCI-E x8
Slot5 PCI-E x8
JI2C1
Slot4 PCI-E x4(in x8 slot)
Slot3 PCI 33MHz
Slot2 PCI 33MHz
Slot1 PCI33MHz
SIMLC
JWOL1
Intel
5100
North Bridge
SP1
Buzzer
B
System Status LED
Intel
ICH9R
South Bridge
SATA5
JBT1
BIOS
Battery
ITE
SAS-GPIO1
CTRL
SAS-GPIO0
USB4/5
JPA2
USB2/3
BPI2C
LED4
LAN2
JPL1
COM2
SATA-GPIO0
SATA4
SAS1
SAS0
SATA3
JD1
JP2
JP1
SATA-GPIO1
SATA2
SAS2
CPU2
Fan 2
LED6
CPU2 VRM OH LED
Fan 3
PWR LED
LED3
FP CTRL
JPA1
SATA1
SATA0
LED1
LSI
SAS
CTRL
SAS3
SAS4
Floppy
IDE
A
JL1
SAS6
SAS7
SAS5
Fan 4
2-32
Page 53
Chapter 3: Troubleshooting
Chapter 3
Troubleshooting
3-1 Troubleshooting Procedures
Use the following procedures to troubleshoot your system. If you have followed all
of the procedures below and still need assistance, refer to the ‘Technical Support
Procedures’ and/or ‘Returning Merchandise for Service’ section(s) in this chapter.
Note: Always disconnect the power cord before adding, changing or install-
ing any hardware components.
Before Power On
Make sure that there are no short circuits between the motherboard and the
1.
chassis.
Disconnect all ribbon/wire cables from the motherboard, including those for
2.
the keyboard and mouse. Remove all add-on cards.
Install a CPU in CPU Socket and connect the chassis speaker and the power
3.
LED to the motherboard. (Make sure that the CPU is properly seated. Be sure
to check all jumper settings as well.)
No Power
Make sure that there are no short circuits between the motherboard and the
1.
chassis.
Make sure that all jumpers are set to their default positions.
2.
Make sure that the 115V/230V switch on the power supply is properly set.
3.
Turn the power switch on and off to test the system. The battery on your
4.
motherboard may be old. Check to verify that it still supplies ~3VDC. If it
does not, replace it with a new one.
No Video
If the power is on but you have no video, remove all the add-on cards and
1.
cables.
Use the speaker to determine if any beep codes exist. Refer to the Appendix
2.
for details on beep codes.
Losing the System’s Setup Confi guration
Make sure that you are using a high quality power supply. A poor quality
1.
power supply may cause the system to lose the CMOS setup information.
Refer to Section 1-6 for details on recommended power supplies.
The battery on your motherboard may be old. Check to verify that it still
2.
3-1
Page 54
X7DCL-3/X7DCL-i User's Manual
supplies ~3VDC. If it does not, replace it with a new one.
If the above steps do not fi x the Setup Confi guration problem, contact your
3.
vendor for repairs.
NOTE
If you are a system integrator, VAR or OEM, a POST diagnostics
card is recommended. For I/O port 80h codes, refer to App. B.
Memory Errors
Make sure the DIMM modules are properly and fully installed. Check if
1.
DIMMs of different speeds or types have been installed. Also make sure that
the BIOS setup is confi gured for the fastest speed of RAM used.
It is recommended to use the same RAM speed for all DIMMs in the system.
2.
Make sure you are using the correct type of Single-Rank, Registered ECC
DDR2 667/533 SDRAM (recommended by the manufacturer.)
Check for bad DIMM modules or slots by swapping a single module between
3.
four slots and noting the results. Make sure all memory modules are fully
seated in their slots. As an interleaved memory scheme is used, you must
install two modules at a time, beginning with DIMM 1A, then DIMM 2A, and
so on (see Section 2-3). Check the position of the 115V/230V switch on the
power supply.
3-2 Technical Support Procedures
Before contacting Technical Support, please take the following steps. Also, note
that as a motherboard manufacturer, Super Micro does not sell directly to end-us-
ers, so it is best to fi rst check with your distributor or reseller for troubleshooting
services. They should know of any possible problem(s) with the specifi c system
confi guration that was sold to you.
1.
Please go through the ‘Troubleshooting Procedures’ and 'Frequently Asked
Question' (FAQ) sections in this chapter or see the FAQs on our web site (http://
www.supermicro.com/support/faqs/) before contacting Technical Support.
2.
BIOS upgrades can be downloaded from our web site at http://www.supermicro.
com/support/bios/.
3.
If you still cannot resolve the problem, include the following information when
contacting Super Micro for technical support:
•
Motherboard model and PCB revision number
•
BIOS release date/version (this can be seen on the initial display when your
system fi rst boots up)
3-2
Page 55
Chapter 3: Troubleshooting
System confi guration
•
An example of a Technical Support form is on our web site at http://www.
•
supermicro.com/support/contact.cfm/.
Distributors: For immediate assistance, please have your account number
•
ready when placing a call to our technical support department. We can be
reached by e-mail at support@supermicro.com or by fax at: (408) 503-8000,
option 2.
3-3 Frequently Asked Questions
Question: What are the various types of memory that my motherboard can
support?
Answer: The X7DCL-3/X7DCL-i has six 240-pin DIMM slots that support Single-
Rank, Registered ECC DDR2 667/533 SDRAM modules. It is strongly recom-
mended that you do not mix memory modules of different speeds and sizes. (See
Chapter 2 for detailed Information.)
Question: How do I update my BIOS?
Answer: It is recommended that you do not upgrade your BIOS if you are experi-
encing no problems with your system. Updated BIOS fi les are located on our web
site at http://www.supermicro.com/support/bios/. Please check our BIOS warning
message and the information on how to update your BIOS on our web site. Also,
check the current BIOS revision, and make sure that it is newer than your BIOS
before downloading. Select your motherboard model and download the BIOS fi le
to your computer. Unzip the BIOS fi les onto a bootable fl oppy and reboot your
system. Follow the Readme.txt to continue fl ashing the BIOS.
(
Warning: Do not shut down or reset the system while updating BIOS to
prevent possible system boot failure!)
Question: What's on the CD that came with my motherboard?
Answer: The supplied compact disc has quite a few drivers and programs that will
greatly enhance your system. We recommend that you review the CD and install
the applications you need. Applications on the CD include chipset drivers for the
Windows OS, and security and audio drivers.
3-4 Returning Merchandise for Service
A receipt or copy of your invoice marked with the date of purchase is required
before any warranty service will be rendered. You can obtain service by calling
your vendor for a Returned Merchandise Authorization (RMA) number. When
returning to the manufacturer, the RMA number should be prominently displayed
3-3
Page 56
X7DCL-3/X7DCL-i User's Manual
on the outside of the shipping carton, and mailed prepaid or hand-carried. Ship-
ping and handling charges will be applied for all orders that must be mailed when
service is complete.
This warranty only covers normal consumer use and does not cover damage in-
curred in shipping or from failure due to the alternation, misuse, abuse or improper
maintenance of products.
During the warranty period, contact your distributor fi rst for any product prob-
lems.
3-4
Page 57
Chapter 4: BIOS
Chapter 4 BIOS
4-1 Introduction
This chapter describes the Phoenix BIOS™ Setup utility for the X7DCL-3/X7DCL-i.
The Phoenix ROM BIOS is stored in a fl ash chip and can be easily upgraded using
a fl oppy disk-based program.
Note: Due to periodic changes to the BIOS, some settings may have been added or
deleted and might not yet be recorded in this manual. Please refer to the Manual
Download area of the Super Micro web site <http://www.supermicro.com> for any
changes to the BIOS that may not be refl ected in this manual.
System BIOS
The BIOS is the Basic Input Output System used in all IBM® PC, XT™, AT®, and
®
PS/2
compatible computers. The Phoenix BIOS stores the system parameters,
types of disk drives, video displays, etc. in the CMOS. The CMOS memory requires
very little electrical power. When the computer is turned off, a backup battery pro-
vides power to the CMOS Logic, enabling it to retain system parameters. Each time
the computer is powered on, the computer is confi gured with the values stored in
the CMOS Logic by the system BIOS, which gains control at boot up.
How To Change the Confi guration Data
The CMOS information that determines the system parameters may be changed by
entering the BIOS Setup utility. This Setup utility can be accessed by pressing the
<Delete> key at the appropriate time during system boot. (See below.)
Starting the Setup Utility
Normally, the only visible POST (Power On Self Test) routine is the memory test. As
the memory is being tested, press the <Delete> key to enter the main menu of the
BIOS Setup utility. From the main menu, you can access the other setup screens,
such as the Security and Power menus. Beginning with Section 4-3, detailed de-
scriptions are given for each parameter setting in the Setup utility.
Warning: Do not shut down or reset the system while updating BIOS
to prevent possible boot failure.
4-1
Page 58
X7DCL-3/X7DCL-i User's Manual
4-2 Running Setup
Default settings are in bold text unless otherwise noted.
The BIOS setup options described in this section are selected by choosing the ap-
propriate text from the main BIOS Setup screen. All displayed text is described in
this section, although the screen display is often all you need to understand how
to set the options (see the next page).
When you fi rst power on the computer, the Phoenix BIOS™ is immediately acti-
vated.
While the BIOS is in control, the Setup program can be activated in one of two
ways:
1. By pressing <Delete> immediately after turning the system on, or
2. When the message shown below appears briefl y at the bottom of the screen
during the POST (Power On Self-Test), press the <Delete> key to activate the main
Setup menu:
Press the <Delete> key to enter Setup
4-3 Main BIOS Setup
All main Setup options are described in this section. The main BIOS Setup screen
is displayed below.
Use the Up/Down arrow keys to move among the different settings in each menu.
Use the Left/Right arrow keys to change the options for each setting.
Press the <Esc> key to exit the CMOS Setup Menu. The next section describes in
detail how to navigate through the menus.
Items that use submenus are indicated with the
press the <Enter> key to access the submenu.
icon. With the item highlighted,
4-2
Page 59
Main BIOS Setup Menu
Chapter 4: BIOS
Main Setup Features
System Time
To set the system date and time, key in the correct information in the appropriate
fi elds. Then press the <Enter> key to save the data.
System Date
Using the arrow keys, highlight the month, day and year fi elds, and enter the correct
data. Press the <Enter> key to save the data.
BIOS Date
This fi eld displays the date when this version of BIOS was built.
Legacy Diskette A
This setting allows the user to set the type of fl oppy disk drive installed as diskette A.
The options are Disabled, 360Kb 5.25 in, 1.2MB 5.25 in, 720Kb 3.5 in, 1.44/1.25MB,
3.5 in and 2.88MB 3.5 in.
4-3
Page 60
X7DCL-3/X7DCL-i User's Manual
IDE Primary Master/Slave, SATA Port1, SATA Port2, SATA Port3
and SATA Port4
These settings allow the user to set the parameters of IDE Primary Master/Slave,
SATA Port1 Master/Slave, SATA Port2 Master/Slave, SATA Port3 Master, and
SATA Port4 Master slots. Hit <Enter> to activate the following sub-menu screen
for detailed options of these items. Set the correct confi gurations accordingly. The
items included in the sub-menu are:
Type
This option allows the user to select the type of IDE hard drive. The option
Auto will allow the BIOS to automatically confi gure the parameters of the
HDD installed at the connection. Enter a number between 1 to 39 to select a
predetermined HDD type. Select User to allow the user to enter the parameters
of the HDD installed. Select CDROM if a CDROM drive is installed. Select ATAPI
if a removable disk drive is installed.
4-4
Page 61
Chapter 4: BIOS
CHS Format
The following items will be displayed by the BIOS:
TYPE: This item displays the type of IDE or SATA Device.
Cylinders: This item indicates the status of Cylinders.
Headers: This item indicates the number of headers.
Sectors: This item displays the number of sectors.
Maximum Capacity: This item displays the maximum storage capacity of the
system.
LBA Format
The following items will be displayed by the BIOS:
Total Sectors: This item displays the number of total sectors available in the
LBA Format.
Maximum Capacity: This item displays the maximum capacity in the LBA
Format.
Multi-Sector Transfers
This item allows the user to specify the number of sectors per block to be used
in multi-sector transfer. The options are Disabled, 4 Sectors, 8 Sectors, and
16 Sectors.
LBA Mode Control
This item determines whether the Phoenix BIOS will access the IDE Channel 0
Master Device via the LBA mode. The options are Enabled and Disabled.
32 Bit I/O
This option allows the user to enable or disable the function of 32-bit data transfer.
The options are Enabled and Disabled.
Transfer Mode
This option allows the user to set the transfer mode. The options are Standard,
Fast PIO1, Fast PIO2, Fast PIO3, Fast PIO4, FPIO3/DMA1 and FPIO4/DMA2.
Ultra DMA Mode
This option allows the user to select Ultra DMA Mode. The options are Disabled,
This setting allows the user to enable or disable the function of the Serial ATA. The
options are Disabled and Enabled.
Native Mode Operation
Select the native mode for ATA. The options are: Parallel ATA, Serial ATA, Both,
and Auto.
SATA Controller Mode
Select Compatible to allow the SATA and PATA drives to be automatically-detected
and be placed in the Legacy Mode by the BIOS. Select Enhanced to allow the
SATA and PATA drives to be to be automatically-detected and be placed in the
Native IDE Mode. (Note: The Enhanced mode is supported by the Windows
2000 OS or a later version.)
When the SATA Controller Mode is set to "Enhanced", the following items will
display:
Serial ATA (SATA) RAID Enable
Select Enable to enable Serial ATA RAID Functions. (For the Windows OS
environment, use the RAID driver if this feature is set to Enabled. If this item is
set to Disabled, the item-SATA AHCI Enable will be available.) The options are
Enabled and Disabled.
ICH RAID Code Base
Select Intel to enable Intel's SATA RAID fi rmware to confi gure Intel's SATA RAID
settings.
SATA AHCI
Select Enable to enable the function of Serial ATA Advanced Host Interface. (Take
caution when using this function. This feature is for advanced programmers only.
The options are Enabled and Disabled.)
System Memory
This display informs you how much system memory is recognized as being present
in the system.
Extended Memory
This display informs you how much extended memory is recognized as being
present in the system.
4-6
Page 63
Chapter 4: BIOS
4-4 Advanced Setup
Choose Advanced from the Phoenix BIOS Setup Utility main menu with the arrow keys.
You should see the following display. The items with a triangle beside them have sub
menus that can be accessed by highlighting the item and pressing <Enter>.
Boot Features
Access the submenu to make changes to the following settings.
QuickBoot Mode
If enabled, this feature will speed up the POST (Power On Self Test) routine by
skipping certain tests after the computer is turned on. The settings are Enabled
and Disabled. If Disabled, the POST routine will run at normal speed.
QuietBoot Mode
This setting allows you to Enable or Disable the graphic logo screen during boot-
up.
POST Errors
Set to Enabled to display POST Error Messages if an error occurs during bootup.
If set to Disabled, the system will continue to boot without displaying any error
message even when a boot error occurs.
ACPI Mode
Use the setting to determine if you want to employ ACPI (Advanced Confi guration
and Power Interface) power management on your system. The options are Yes
and No.
4-7
Page 64
X7DCL-3/X7DCL-i User's Manual
Power Button Behavior
If set to Instant-Off, the system will power off immediately as soon as the user
hits the power button. If set to 4-sec., the system will power off when the user
presses the power button for 4 seconds or longer. The options are instant-off and
4-sec override.
Resume On Modem Ring
Select On to “wake your system up” when an incoming call is received by your
modem. The options are On and Off.
Power Loss Control
This setting allows you to choose how the system will react when power returns
after an unexpected loss of power. The options are Stay Off, Power On, and
Last State.
Watch Dog
If enabled, this option will automatically reset the system if the system is not active
for more than 5 minutes. The options are Enabled and Disabled.
Summary Screen
This setting allows you to Enable or Disable the summary screen which displays
the system confi guration during bootup.
Memory Cache
Cache System BIOS Area
This setting allows you to designate a reserve area in the system memory to be used
as a System BIOS buffer to allow the BIOS to write (cache) data into this reserved
memory area. Select Write Protect to enable this function, and this area will be
reserved for BIOS ROM access only. Select Uncached to disable this function and
make this area available for other devices.
Cache Video BIOS Area
This setting allows you to designate a reserve area in the system memory to be
used as a Video BIOS buffer to allow the BIOS to write (cache) data into this
reserved memory area. Select Write Protect to enable the function and this area
will be reserved for Video BIOS ROM access only. Select Uncached to disable this
function and make this area available for other devices.
4-8
Page 65
Chapter 4: BIOS
Cache Base 0-512K
If enabled, this feature will allow the data stored in the base memory area: block
0-512K to be cached (written) into a buffer, a storage area in the Static DROM
(SDROM) or to be written into L1, L2 cache inside the CPU to speed up CPU
operations. Select Uncached to disable this function. Select Write Through to allow
data to be cached into the buffer and written into the system memory at the
same time. Select Write Protect to prevent data from being written into the base
memory area of Block 0-512K. Select Write Back to allow the CPU to write data
back directly from the buffer without writing data to the System Memory for fast
CPU data processing and operation. The options are Uncached, Write Through,
Write Protect, and Write Back.
Cache Base 512K-640K
If enabled, this feature will allow the data stored in the memory area: 512K-640K
to be cached (written) into a buffer, a storage area in the Static DROM (SDROM)
or written into L1, L2, L3 cache inside the CPU to speed up CPU operations.
Select Uncached to disable this function. Select Write Through to allow data to
be cached into the buffer and written into the system memory at the same time.
Select Write Protect to prevent data from being written into the base memory
area of Block 512-640K. Select Write Back to allow the CPU to write data back
directly from the buffer without writing data to the System Memory for fast CPU
data processing and operation. The options are Uncached, Write Through, Write
Protect, and Write Back.
Cache Extended Memory
If enabled, this feature will allow the data stored in the extended memory area to
be cached (written) into a buffer, a storage area in the Static DROM (SDROM)
or written into L1, L2, L3 cache inside the CPU to speed up CPU operations.
Select Uncached to disable this function. Select Write Through to allow data
to be cached into the buffer and written into the system memory at the same
time. Select Write Protect to prevent data from being written into the extended
memory area above 1MB. Select Write Back to allow the CPU to write data back
directly from the buffer without writing data to the System Memory for fast CPU
data processing and operation. The options are Uncached, Write Through, Write
Protect, and Write Back.
Discrete MTRR Allocation
If enabled, MTRRs (-Memory Type Range Registers) are confi gured as distinct,
separate units and cannot be overlapped. If enabled, the user can achieve better
graphic effects when using a Linux graphic driver that requires the write-combining
confi guration with 4GB or more memory. The options are Enabled and Disabled.
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PCI Confi guration
Access the submenu to make changes to the following settings for PCI devices.
Access the submenu for each of the settings above to make changes to the
following:
Option ROM Scan
When enabled, this setting will initialize the device expansion ROM. The options
are Enabled and Disabled.
Enable Master
This setting allows you to enable the selected device as the PCI bus master.
The options are Enabled and Disabled.
Latency Timer
This setting allows you to set the clock rate for Bus Master. A high-priority, high-
throughout device may benefi t from a greater clock rate. The options are Default,
0020h, 0040h, 0060h, 0080h, 00A0h, 00C0h, and 00E0h. For Unix, Novell and
other Operating Systems, please select the option: other. If a drive fails after
the installation of a new software, you might want to change this setting and
try again. A different OS requires a different Bus Master clock rate.
Large Disk Access Mode
This setting determines how large hard drives are to be accessed. The options are
DOS or Other (for Unix, Novelle NetWare and other operating systems).
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Advanced Chipset Control
Access the submenu to make changes to the following settings.
Warning: Take Caution when changing the Advanced settings. An incorrect
setup, a very high DRAM frequency or an incorrect DRAM timing may cause
the system become unstable. When this occurs, reset the setting to the default
setting.
Crystal Beach Features
This feature cooperates with the Intel I/O AT (Acceleration Technology) to accelerate
the performance of TOE devices. (Note: A TOE device is a specialized, dedicated
processor that is installed on an add-on card or a network card to handle some or all
packet processing of this add-on card. For this motherboard, the TOE device is built
inside the ICH9R South Bridge chip.) The options are Enabled and Disabled.
SERR Signal Condition
This setting specifi es the ECC Error conditions that an SERR# is to be asserted.
The options are None, Single Bit, Multiple Bit, and Both.
4GB PCI Hole Granularity
This feature allows you to select the granularity of PCI hole for PCI slots. If MTRRs
are not enough, this option may be used to reduce MTRR occupation. The options
are: 256 MB, 512 MB, 1GB and 2GB.
Route Port 80h Cycles to
This feature allows the user to decide which bus to send debug information to. The
options are Disabled, PCI and LPC.
Enabling Multi-Media Timer
Select Yes to activate a set of timers that are alternative to the traditional 8254
timers for the OS use. The options are Yes and No.
USB Host Controller 1
Select Enabled to enable USB Host Controller 1. The options are Enabled and
Disabled.
USB Host Controller 2
Select Enabled to enable USB Host Controller 2. The options are Enabled and
Disabled.
Legacy USB Support
This setting allows you to enable support for Legacy USB devices. The settings
are Enabled and Disabled.
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Advanced Processor Options
Access the submenu to make changes to the following settings.
CPU Speed
This is a display that indicates the speed of the installed processor.
Frequency Ratio (Available if supported by the CPU.)
The feature allows the user to set the internal frequency multiplier for the CPU.
The options are: Default, x12, x13, x14, x15, x16, x17 and x18.
Core-Multi-Processing (Available if supported by the CPU.)
Set to Enabled to use a processor's Second Core and beyond. (Please refer to
Intel's web site for more information.) The options are Disabled and Enabled.
Thermal Management 2 (Available if supported by the CPU.)
Set to Enabled to use Thermal Management 2 (TM2) which will lower CPU voltage
and frequency when the CPU temperature reaches a predefi ned overheat threshold.
Set to Disabled to use Thermal Manager 1 (TM1), allowing CPU clocking to be
regulated via CPU Internal Clock modulation when the CPU temperature reaches
the overheat threshold.
C1 Enhanced Mode (Available if supported by the CPU.)
Set to Enabled to enable Enhanced Halt State to lower CPU voltage/frequency to
prevent overheat. The options are Enabled and Disabled. (Note: please refer to
Intel’s web site for detailed information.)
Execute Disable Bit (Available if supported by the CPU and the
OS.)
Set to Enabled to enable Execute Disable Bit and allow the processor to classify
areas in memory where an application code can execute and where it cannot, and
thus preventing a worm or a virus from inserting and creating a fl ood of codes to
overwhelm the processor or damage the system during an attack. This feature is
available when your OS and your CPU support the function of Execute Disable
Bit. The options are Disabled and Enabled. Note: For more information regarding
hardware/software support for this function, please refer to Intel's and Microsoft's
web sites.
Intel <R> Virtualization Technology (Available if supported by the
CPU.)
Select Enabled to use the feature of Virtualization Technology to allow one platform
to run multiple operating systems and applications in independent partitions, creating
multiple "virtual" systems in one physical computer. The options are Enabled and
Disabled. Note: If there is any change to this setting, you will need to power off
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Chapter 4: BIOS
and restart the system for the change to take effect. Please refer to Intel’s web site
for detailed information.
Intel EIST Support (Available if supported by the CPU.)
Select Enabled to use the Enhanced Intel SpeedStep Technology and allows the
system to automatically adjust processor voltage and core frequency in an effort
to reduce power consumption and heat dissipation. The options are Enabled and
Disabled. Please refer to Intel’s web site for detailed information.
I/O Device Confi guration
Access the submenu to make changes to the following settings.
KBC Clock Input
This setting allows you to select clock frequency for KBC. The options are 6MHz,
8MHz, 12MHz, and 16MHz.
Serial Port A
This setting allows you to assign control of serial port A. The options are Enabled
(user defi ned), Disabled, and Auto (BIOS- or OS- controlled).
Base I/O Address
This setting allows you to select the base I/O address for serial port A. The options
are 3F8, 2F8, 3E8, and 2E8.
Interrupt
This setting allows you to select the IRQ (interrupt request) for serial port A. The
options are IRQ3 and IRQ4.
Serial Port B
This setting allows you to assign control of serial port B. The options are Enabled
(user defi ned), Disabled, Auto (BIOS controlled) and OS Controlled.
Mode
This setting allows you to set the type of device that will be connected to serial
port B. The options are Normal and IR (for an infrared device).
Base I/O Address
This setting allows you to select the base I/O address for serial port B. The
options are 3F8, 2F8, 3E8 and 2E8.
Interrupt
This setting allows you to select the IRQ (interrupt request) for serial port B. The
options are IRQ3 and IRQ4.
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Floppy Disk Controller
This setting allows you to assign control of the fl oppy disk controller. The options
are Enabled (user defi ned), Disabled, and Auto (BIOS and OS controlled).
Base I/O Address
This setting allows you to select the base I/O address for the Floppy port. The
options are Primary and Secondary.
DMI Event Logging
Access the submenu to make changes to the following settings.
Event Log Validity
This is a display to inform you of the event log validity. It is not a setting.
Event Log Capacity
This is a display to inform you of the event log capacity. It is not a setting.
View DMI Event Log
Highlight this item and press <Enter> to view the contents of the event log.
Event Logging
This setting allows you to Enable or Disable event logging.
ECC Event Logging
This setting allows you to Enable or Disable ECC event logging.
Mark DMI Events as Read
Highlight this item and press <Enter> to mark the DMI events as read.
Clear All DMI Event Logs
Select Yes and press <Enter> to clear all DMI event logs. The options are Yes
and No.
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Console Redirection
Access the submenu to make changes to the following settings.
COM Port Address
This item allows you to specify which COM port to direct the remote console to:
Onboard COM A or Onboard COM B. This setting can also be Disabled.
BAUD Rate
This item allows you to set the BAUD rate for the console redirection. The options
are 300, 1200, 2400, 9600, 19.2K, 38.4K, 57.6K, and 115.2K.
Console Type
This item allows you to choose the console redirection type. The options are VT100,
VT100/8bit, PC-ANSI/7bit, PC ANSI, VT100+,
and VT-UTF8.
Flow Control
This item allows you to set the fl ow control for the console redirection. The options
are: None, XON/XOFF, and CTS/RTS.
Console Connection
This item allows you to decide how the console redirection is to be connected:
either Direct or Via Modem.
Continue CR after POST
This item allows you to decide whether you want to continue with the console
redirection after POST routines. The options are On and Off.
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Hardware Monitor Logic
CPU Temperature Threshold
This option allows the user to set a CPU temperature threshold that will activate the
alarm system when the CPU temperature reaches this pre-set temperature threshold.
The hardcode default setting is 80
CPU is 75oC and for the 5000 Series CPU is 80oC.) (See below.)
Temperature Monitoring (Available if supported by the CPU)
This function monitors the following PECI (Platform Environment Control Interface)
items:
CPU1 Temperature/CPU1 Second Core/CPU2 Temperature/CPU2 Second
Core/System Temperature
Fan1-Fan6 Speeds: If the feature of Auto Fan Control is enabled, the BIOS will
automatically display the status of the fans indicated in this item.
o
C. (The default setting for the Intel 5100 Series
Fan Speed Control Modes
This feature allows the user to decide how the system controls the speeds of the
onboard fans. The CPU temperature and the fan speed are correlative. When
the CPU on-die temperature increases, the fan speed will also increase, and vice
versa. If the option is set to 3-pin fan, the fan speed is controlled by voltage. If the
option is set to 4-pin, the fan speed will be controlled by Pulse Width Modulation
(PWM). Select 3-pin if your chassis came with 3-pin fan headers. Select 4-pin if
your chassis came with 4-pin fan headers. Select Workstation if your system is
used as a Workstation. Select Server if your system is used as a Server. Select
Disable to disable the fan speed control function to allow the onboard fans to run
at full speed (12V) at all times. The Options are: 1. Disable, 2. 3-pin (Server), 3.
3-pin (Workstation), 4. 4-pin (Server) and 5. 4-pin (Workstation).
Voltage Monitoring
The following items will be monitored and displayed: