Page 1
®
SUPER
X7DBR-8+
X7DBR-i+
USER’S MANUAL
Revision 1.0b
Page 2
The information in this User’s Manual has been carefully reviewed and is believed to be accurate.
The vendor assumes no responsibility for any inaccuracies that may be contained in this document,
makes no commitment to update or to keep current the information in this manual, or to notify any
person or organization of the updates. Please Note: For the most up-to-date version of this
manual, please see our web site at www.supermicro.com.
SUPER MICRO COMPUTER reserves the right to make changes to the product described in this
manual at any time and without notice. This product, including software, if any, and documentation may not, in whole or in part, be copied, photocopied, reproduced, translated or reduced to any
medium or machine without prior written consent.
IN NO EVENT WILL SUPER MICRO COMPUTER BE LIABLE FOR DIRECT, INDIRECT, SPECIAL,
INCIDENTAL, SPECULATIVE OR CONSEQUENTIAL DAMAGES ARISING FROM THE USE
OR INABILITY TO USE THIS PRODUCT OR DOCUMENTATION, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. IN PARTICULAR, SUPER MICRO COMPUTER SHALL NOT
HAVE LIABILITY FOR ANY HARDWARE, SOFTWARE, OR DATA STORED OR USED WITH THE
PRODUCT, INCLUDING THE COSTS OF REPAIRING, REPLACING, INTEGRATING, INSTALLING
OR RECOVERING SUCH HARDWARE, SOFTWARE, OR DATA.
Any disputes arising between manufacturer and customer shall be governed by the laws of Santa
Clara County in the State of California, USA. The State of California, County of Santa Clara shall
be the exclusive venue for the resolution of any such disputes. Super Micro's total liability for
all claims will not exceed the price paid for the hardware product.
FCC Statement: This equipment has been tested and found to comply with the limits for a Class
A digital device pursuant to Part 15 of the FCC Rules. These limits are designed to provide
reasonable protection against harmful interference when the equipment is operated in a commercial
environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the manufacturer’s instruction manual, may cause harmful
interference with radio communications. Operation of this equipment in a residential area is likely
to cause harmful interference, in which case you will be required to correct the interference at your
own expense.
California Best Management Practices Regulations for Perchlorate Materials: This Perchlorate
warning applies only to products containing CR (Manganese Dioxide) Lithium coin cells. “Perchlorate
Material-special handling may apply. See www.dtsc.ca.gov/hazardouswaste/perchlorate”
WARNING: Handling of lead solder materials used in this
product may expose you to lead, a chemical known to
the State of California to cause birth defects and other
reproductive harm.
Revision Number: 1.0b
Release Date: June 13, 2007
Unless you request and receive written permission from SUPER MICRO COMPUTER, you may not
copy any part of this document.
Information in this document is subject to change without notice. Other products and companies
referred to herein are trademarks or registered trademarks of their respective companies or mark
holders.
Copyright © 2007 by SUPER MICRO COMPUTER INC.
All rights reserved.
Printed in the United States of America
Page 3
Preface
About This Manual
This manual is written for system integrators, PC technicians and
knowledgeable PC users. It provides information for the installation and use of the
X7DBR-8+/X7DBR-i+ motherboard. The X7DBR-8+/X7DBR-i+
supports dual Intel
667 MHz/1.066 GHz/1.333 GHz. With dual 64-bit Xeon dual core processors, the
5000P chipset, and 16 DDR2 FBD 667/533 memory modules built-in, the X7DBR-
8+/X7DBR-i+ offers substantial functionality and performance enhancements to the
motherboards based on the NetBurst microarchitecture while remaining compat-
ible with the 32-bit based software. The features include Intel Hyper-Threading
Technology, Virtualization Technoogy, Hyper Pipelined Technology, Execution Trace
Cache, Thermal Monitor 1/2 (TM1/TM2), Enhanced Intel SpeedStep technology,
Advanced Dynamic Execution, Advanced Transfer Cache, Streaming SIMD Exten-
sions 3 (SSE3) and Extended Memory 64 Technology (EM64T). These features
allow the motherboard to operate at much higher speeds with better power manage-
ment in much safer environments than the traditional motherboards. The X7DBR-
8+/X7DBR-i+ is ideal for high performance dual processor (DP) enterprise server
environments. This product is intended to be professionally installed.
XEON 64-bit dual core processors at a front side bus speed of
Preface
Manual Organization
Chapter 1 describes the features, specifi cations and performance of the mainboard
and provides detailed information about the chipset.
Chapter 2 provides hardware installation instructions. Read this chapter when
installing the processor, memory modules and other hardware components into
the system. If you encounter any problems, see Chapter 3, which describes
troubleshooting procedures for the video, the memory and the system setup stored
in CMOS.
Chapter 4 includes an introduction to BIOS and provides detailed information on
running the CMOS Setup utility.
Appendix A and Appendix B provide BIOS POST Messages and POST Codes.
Appendix C, Appendix D and Appendix E list HostRAID Setup Guidelines and
Other Software Driver and Program Installation Instructions.
Conventions Used in the Manual:
Special attention should be given to the following symbols for proper installation and
to prevent damage done to the components or injury to yourself:
Danger/Caution: Instructions to be strictly followed to prevent
catastrophic system failure or to avoid bodily injury.
Warning: Important information given to ensure proper system installation
or to prevent damage to the components.
(*Note): Note: Additional Information given to differentiate various models or
to ensure correct system setup.
iii
Page 4
X7DBR-8+/X7DBR-i+ User's Manual
Table of Contents
Preface
About This Manual ...................................................................................................... iii
Manual Organization ................................................................................................... iii
Conventions Used in the Manual .................................................................................. iii
Chapter 1: Introduction
1-1 Overview ......................................................................................................... 1-1
Checklist ................................................................................................... 1-1
Contacting Supermicro ............................................................................. 1-2
X7DBR-8+/X7DBR-i+ Image ...................................................... 1-3
X7DBR-8+/X7DBR-i+ Layout ...................................................... 1-4
Quick Reference ...................................................................................... 1-5
Motherboard Features ................................................................................ 1-6
Intel 5000P Chipset: System Block Diagram ........................................... 1-8
1-2 Chipset Overview ........................................................................................... 1-9
1-3 Special Features ........................................................................................... 1-10
Recovery from AC Power Loss .............................................................. 1-10
1-4 PC Health Monitoring .................................................................................... 1-10
1-5 ACPI Features .............................................................................................. 1-11
1-6 Power Supply ............................................................................................... 1-12
1-7 Super I/O ........................................................................................................ 1-12
Chapter 2: Installation
2-1 Static-Sensitive Devices ................................................................................. 2-1
Precautions ................................................................................................ 2-1
Unpacking ................................................................................................ 2-1
2-2 Processor and Heatsink Installation ............................................................... 2-2
2-3 Installing DIMMs ............................................................................................. 2-6
2-4 Control Panel Connectors and IO Ports ......................................................... 2-8
A. Back Panel Connectors/IO Ports .............................................................. 2-8
B. Front Control Panel ................................................................................... 2-9
C. Front Control Panel Pin Defi nitions ........................................................ 2-10
NMI Button ............................................................................................. 2-10
Power LED ............................................................................................. 2-10
HDD LED .............................................................................................. 2-11
NIC1/NIC2 LEDs ................................................................................... 2-11
Overheat/Fan Fail LED ......................................................................... 2-12
Power Fail LED ........................................................................................ 2-12
iv
Page 5
Table of Contents
Reset Button ......................................................................................... 2-13
Power Button .......................................................................................... 2-13
2-5 Connecting Cables ......................................................................................... 2-14
ATX Power Connector .......................................................................... 2-14
Processor Power Connector ................................................................. 2-14
Universal Serial Bus (USB0/1) ................................................................ 2-15
Chassis Intrusion .................................................................................... 2-15
Fan Headers .......................................................................................... 2-16
ATX PS/2 Keyboard and Mouse Ports ..................................................... 2-17
Serial Ports ............................................................................................. 2-17
Wake-On-Ring .......................................................................................... 2-18
Wake-On-LAN .......................................................................................... 2-18
GLAN (Ethernet Ports) ............................................................................. 2-19
Speaker/Power LED Header .................................................................. 2-19
Power Fault .............................................................................................. 2-20
Alarm Reset .............................................................................................. 2-20
Overheat LED/Fan Fail ............................................................................ 2-21
SMB Connector ........................................................................................ 2-21
SMB Power Connector ............................................................................. 2-22
VGA Connector ........................................................................................ 2-22
Compact Flash Card PWR Connector ..................................................... 2-23
Unit Identifi cation Switches ...................................................................... 2-23
2-6 Jumper Settings .............................................................................................. 2-24
Explanation of Jumpers ......................................................................... 2-24
GLAN Enable/Disable ............................................................................ 2-24
Clear CMOS ............................................................................................. 2-25
Watch Dog ................................................................................................ 2-25
SCSI Controller Enabled/Disabled ........................................................... 2-26
SCSI Termination Enabled/Dsiabled ........................................................ 2-26
3rd PWR Supply PWR Fault .................................................................... 2-27
VGA Enable/Disable ................................................................................. 2-27
I2C Bus to PCI Slots ................................................................................ 2-28
Compact Flash Master/Slave Enable/Disable .......................................... 2-28
2-7 Onboard Indicators .......................................................................................... 2-29
GLAN LEDs .............................................................................................. 2-29
Onboard SCSI Activity LED ..................................................................... 2-30
2-8 Floppy, Hard Disk Drive, SIMSO-DIMM IPMI, Zero Channel RAID and SCSI
Connections ..................................................................................................... 2-31
Floppy Connector .................................................................................... 2-31
v
Page 6
X7DBR-8+/X7DBR-i+ User's Manual
SIMSO Slot .............................................................................................. 2-32
Zero Channel RAID Card Slot ................................................................ 2-32
IDE Connectors ....................................................................................... 2-33
Ultra 320 SCSI Connectors ..................................................................... 2-34
Chapter 3: Troubleshooting
3-1 Troubleshooting Procedures ........................................................................... 3-1
Before Power On ....................................................................................... 3-1
No Power ................................................................................................... 3-1
No Video .................................................................................................. 3-1
Memory Errors ........................................................................................... 3-1
Losing the System’s Setup Confi guration ................................................ 3-1
3-2 Technical Support Procedures ....................................................................... 3-2
3-3 Frequently Asked Questions .......................................................................... 3-3
3-4 Returning Merchandise for Service ................................................................. 3-4
Chapter 4: BIOS
4-1 Introduction ....................................................................................................... 4-1
4-2 Running Setup ................................................................................................. 4-2
4-3 Main BIOS Setup ............................................................................................. 4-2
4-4 Advanced Setup ............................................................................................... 4-7
4-5 Security Setup ............................................................................................... 4-24
4-6 Boot Setup ...................................................................................................... 4-25
4-7 Exit .................................................................................................................. 4-26
Appendices:
Appendix A: BIOS POST Messages .......................................................................... A-1
Appendix B: BIOS POST Codes ................................................................................B-1
Appendix C: Intel HostRAID Setup Guidelines ..........................................................C-1
Appendix D: Adaptec HostRAID Setup Guidelines ...................................................D-1
Appendix E: Installing Other Software Programs and Drivers .................................. E-1
vi
Page 7
Chapter 1: Introduction
Chapter 1
Introduction
1-1 Overview
Checklist
Congratulations on purchasing your computer motherboard from an acknowledged
leader in the industry. Supermicro boards are designed with the utmost attention
to detail to provide you with the highest standards in quality and performance.
Check that the following items have all been included with your motherboard. If
anything listed here is damaged or missing, contact your retailer. All are included
in the Retail Box.
One (1) Supermicro Mainboard
One (1) ribbon cable for IDE devices (CBL-036L-02)
One (1) fl oppy ribbon cable (CBL-022)
One (1) Supermicro CD containing drivers and utilities
One (1) User's/BIOS Manual
One (1) Ultra 320 SCSI User's Manual (*X7DBR-8+ only)
1-1
Page 8
X7DBR-8+/X7DBR-i+ User's Manual
Contacting Super Micro
Headquarters
Address: Super Micro Computer, Inc.
980 Rock Ave.
San Jose, CA 95131 U.S.A.
Tel: +1 (408) 503-8000
Fax: +1 (408) 503-8008
Email: marketing@supermicro.com (General Information)
support@supermicro.com (Technical Support)
Web Site: www.supermicro.com
Europe
Address: Super Micro Computer B.V.
Het Sterrenbeeld 28, 5215 ML
's-Hertogenbosch, The Netherlands
Tel: +31 (0) 73-6400390
Fax: +31 (0) 73-6416525
Email: sales@supermicro.nl (General Information)
support@supermicro.nl (Technical Support)
rma@supermicro.nl (Customer Support)
Asia-Pacifi c
Address: Super Micro, Taiwan
4F, No. 232-1 Liancheng Road
Chung-Ho 235, Taipei Hsien, Taiwan, R.O.C.
Tel: +886-(2) 8226-3990
Fax: +886-(2) 8226-3991
Web Site: www.supermicro.com.tw
Technical Support:
Email: support@supermicro.com.tw
Tel: 886-2-8228-1366, ext.132 or 139
1-2
Page 9
Chapter 1: Introduction
Figure 1-1. X7DBR-8+/X7DBR-i+ Image
(*Note: The drawings and pictures shown in this manual were based on
the latest PCB Revision available at the time of publishing of the manual. The
motherboard you’ve received may or may not look exactly the same as the
graphics shown in the manual.)
1-3
Page 10
X7DBR-8+/X7DBR-i+ User's Manual
Figure 1-2. X7DBR-8+/X7DBR-i+ Motherboard Layout
(not drawn to scale)
UID-
Switch
KB
JKB
MS
JMS
USB0/1
JUSB1
COM1
JCOM1
GLAN1
JLAN1
GLAN2
JLAN2
VGA
J15
LVD/SE
U320
SCSI Chann. B
JA2
JCOM2
J34
J4
JUID2
J9B2
Bank4
J9B1
J33
J3
Bank3
J8B3
J8B2
J32
J2
Bank2
J8B1
J7B3
J31
J1
Bank1
J7B2
J7B1
UPER X7DBR-8/i+
S
Slot7
SE8C
Slot6
JPG1
GLAN
CTRLR
VGA
CTRLR
SIMSO
DIMM
DIMM 4C (Bank 4)
DIMM 4B (Bank 4)
DIMM 4A (Bank 4)
DIMM 3D (Bank 3)
DIMM
DIMM 3B (Bank 3)
DIMM 3A (Bank 3)
DIMM 2D (Bank 2)
DIMM 2C (Bank 2)
DIMM 2B (B
DIMM 2A (Bank 2)
DIMM 1D (Bank 1)
DIMM
DIMM 1B (Bank 1)
DIMM 1A
®
JPCIE3
PCI-X 133MHz
Battery
PXH-V
4D (B
3C (Bank 3)
1C (Bank 1)
JI
ank 4)
ank 2)
(Bank 1)
2
2
JI
C2
C1
JPA1
JPA3
JPA2
SCSI
CTRLR
SO 100MHz ZCR1
North Bridge
DA2
JWOL1
JWOR1
WOR
SXB-
Buzzer
WOL
PCI-Ex8
JPCIE1
SMB
J4E3
JPWF
J18
SXB-
PCI-Ex8
J17
SMBus
PWR
J3P
PWR Fail
JAR1
JPCIE2
South
Bridge
USB4
JUSB3
ATX Main
PWR
CPU1
CPU2
USB2/3
JUSB2
JPL1
JPL2
SATA1
SATA0
JPW1
JBT1
JS2
JS1
4-pin
PWR
JPW2
S/IO
SATA3
JS4
SATA2
JS3
8-pin
PWR
JCF1
J7
SATA5
SATA4
JWF1
BIOS
JPW3
JS6
JS5
FP Control
JUID1
JOH1
JP1
Fan1
Fan2
Fan3
Fan4
Fan5
IDE1
Compact Flash
J22
JIDE1
JIDE2
U320 LVD/SE
Channel A
JA1
JA1
JWD
JL1
JF1
SPKPW LED
JD1
Floppy
DA1
Notes:
1. Jumpers not indicated are for test purposes only.
2. See Chapter 2 for detailed information on jumpers, I/O ports and
JF1 front panel connections.
3. " " indicates the location of Pin 1.
4. SCSI is for the X7DBR-8+ only.
5. For Compact Card to work properly, please enable JCF1 by putting cap on it
and connect JWF1 to a power supply.
6. SE8C is a connector specially designed for 2U riser cards only. It supports
PCI-Express cards through special 2U riser cards only.
1-4
Page 11
Chapter 1: Introduction
Quick Reference ( X7DBR-8+/X7DBR-i+)
Jumper Description Default Setting
J3P 3rd PWR Failure Detect
JBT1 CMOS Clear See Chapter 2
JCF1 Compact Card Master/Slave Select On (Master)
2
JI
C1/JI2C2 SMBBus to PCI-E Slots Off (Disabled)
JPA1 (X7DBR-8+)SCSI Controller Enable Pins 1-2 (Enabled)
JPA2, JPA3 SCSI CHA(JPA2),CHB(JPA3)Term.En Off (Enabled) (X7DBR-8+)
JPG1 VGA Enable Pins 1-2 (Enabled)
JPL1/ JPL2 GLAN1/GLAN2 Enable Pins 1-2 (Enabled)
JWD Watch Dog Pins 1-2 (Reset)
Connector Description
ATX PWR (JPW1) Primary 24-Pin ATX PWR Connector
Aux. PWR/CPU PWR +12V 4-pin PWR (JWP2)/+12V 8-pin PWR(JPW3)
Buzzer Internal Speaker
Chassis Intrusion (JL1) Chassis Intrusion Header
COM1/COM2 COM1(JCOM1)/COM2(JCOM2) Serial Port Connectors
Compact PWR (JWF1) Compact Card PWR Connector (*Used if JCF1 is on.)
DA1/DA2 SCSI Channel A/B Activity LED Indicators(See Chapt.2)
DIMM#1A-DIMM#4D Memory DDR2 Fully Buffered (FBD) Slots
FAN 1-5 Fans 1-5 (CPU Fans/Chassis Fans)
Floppy (J22) Floppy Disk Drive Connector
FP CTRL (JF1) Front Control Panel Connector
GLAN 1/2 (JLAN1/2) G-bit Ethernet Ports
IDE1/IDE2 (*Note) IDE1 Hard Drive (JIDE1)/Compact Flash Card (JIDE2)
OH LED (JOH1) Overheat LED
JAR1 Alarm Reset Enable
JPWF Power Supply Failure Connector (See Chapter 2)
JPCIE1, JPCIE2 PCI-Exp. x8 Slots
JPCIE3 (Slot7) SE8C Slot (See Note 6 on Page 1-4)
JUID1, JUID2 Universal Idenfi cation Switches 1 & 2
PCI-X (Slot6) PCI-X 133MHz Slot
PWR LED/SPKR (JD1) PWR LED(pins1-3)/SpeakerHeader (pins 4-7)
PWR SMB (J17) Power System Management (I
SATA0-SATA5 (JS1-6) Intel SATA 0-5 Connectors
SCSI Chan. A/B (JA1/JA2)SCSI Channel A/Channel B Connectors (*X7DBR-8+)
SMB (J18) System Management Bus Header
SIMSO SIM SO-DIMM IPMI Slot
SO ZCR1 Zero Channel RAID Card Slot
USB 0/1,USB 2/3,USB4 Back Panel USB 0/1, Front Panel USB 2/3, FP USB4
VGA (J15) VGA Connector
WOL (JWOL1) Wake-on-LAN Header
WOR (JWOR) Wake-on-Ring Header
1-5
Off (Disabled)
2
C) Header
Page 12
X7DBR-8+/X7DBR-i+ User's Manual
Motherboard Features
CPU
• Dual Intel
®
64-bit Xeon LGA 771 dual core processors at a front side bus
speed of 667 MHz/1.066 GHz/1.333 GHz
Memory
• 16 240-pin DIMM sockets with support up to 64 GB DDR2 Fully Buffered
(FBD) ECC 667/533 Memory (*See Section 2-3 in Chapter 2 for DIMM Slot
Population.)
Chipset
• Intel 5000P chipset, including: the 5000P Memory Control Hub (MCH), the
Enterprise South Bridge 2 (ESB2), and the I/O subsystem (PXHV).
Expansion Slots
• Three PCI-Express slots (*three slots at x8@4GB/sec.)
• One 64-bit PCI-X slot (*One PCI-X-133 MHz slot: Slot 6)
BIOS
• 8 Mb Phoenix
®
Flash ROM
• DMI 2.3, PCI 2.2, ACPI 1.0/2.0, Plug and Play (PnP), SMBIOS 2.3 and USB
Keyboard support
PC Health Monitoring
• Onboard voltage monitors for CPU cores, chipset voltage, +1.8V, +3.3V, +5V,
+12V, −12V, +3.3V Standby, +5V standby and VBAT
• Fan status monitor with fi rmware control
• CPU/chassis temperature monitors
• Low noise fan speed control
• Environmental temperature monitor and control
• Platform Environment Control Interface (PECI) ready
2
• I
C temperature sensing logic
• Thermal Monitor 2 (TM2) support
• CPU slow-down on temperature overheat
• CPU thermal trip support for processor protection, power LED
• Power-up mode control for recovery from AC power loss
• Auto-switching voltage regulator for CPU cores
• System overheat/Fan Fail LED Indicator and control
• Chassis intrusion detection
• System resource alert via Supero Doctor III
1-6
Page 13
Chapter 1: Introduction
ACPI Features
• Slow blinking LED for suspend state indicator
• Main switch override mechanism
• ACPI Power Management
• Power-on mode for power recovery
Onboard I/O
• Six SATA ports (supporting RAID0, RAID1, RAID10 and RAID5)
• One SIMSO IPMI socket (AOC-SIMSO)
• One SOZCR socket (AOC-SOZCR1)
• Two Giga-bit LAN ports with IOAT Technology
• One EIDE Ultra DMA/100 bus master interface
• One IDE w/Compact Flash Card supported
• One fl oppy port interface
• Two COM ports(1 header, 1 port)
• Up to fi ve USB 2.0 (Universal Serial Bus) (2 ports, 3 Headers)
• ATI ES1000 16MB Graphic Controller
• Super I/O: Winbond W83627HG w/Hardware Monitor support: W83793G
Other
• Internal/external modem ring-on
• Wake-on-LAN (WOL)
• Wake-on-Ring (WOR)
• Console redirection
• Onboard Fan Speed Control by Thermal Management via BIOS
CD/Diskette Utilities
• BIOS fl ash upgrade utility and device drivers
Dimensions
• ATX Ext. 13.68" (L) x 13.00" (W) (347.47mm x 330.2mm)
1-7
Page 14
X7DBR-8+/X7DBR-i+ User's Manual
J12
SO_ZCR
SCSI
7902
JPCIE2
PCI-E_X4_SLOT_L
JPCIX1
PCI-X_SLOT_L
VGA
CONN
JPCIE1
ISL6307
PCI-E_X4_SLOT_L
PCIX-133
PCIX-133
PXH-V
PCI-X 133
VGA
CTRLR
VRM
PCI-EXP X8
PCI-EXP X8
JPCIE3
PCI-EXP X8
PCI-E_X8_SLOT_R
PCI-EXP X4
PCI 32/33MMZ
PROCESSOR#2
1067/1333
MT/S
PORT
#4,5
PORT
#6,7
PORT
#2
PORT
#1,2
PORT
#0
PCIX
PCI-33
MCH
PORT PORT
PCIE X4
PCIE X4
PORT PORT
#4 #3
ESB2
PROCESSOR#1
1067/1333
MT/S
FBD CHNL0
FBD CHNL1
FBD CHNL2
FBD CHNL3
#0#3
PCIE X4
ATA 100
3.0 Gb/S
USB 2.0
VRM
ISL6307
BRANCH0
#0-3
#0-3
FBD DIMM
IDE CONN
#5
#4
#3
#2
#1
#0
SATA
#4
#3
#2
#1
#0
USB
BRANCH1
#0-3
#0-3
#0-3
FBD DIMM
FBD DIMM
#0-3
#0-3
#0-3
FBD DIMM
SIO
HG
MS
KB
LPC
COM1
COM2
TPM1.2
HW MONITOR
W83793G
FRONT PANEL
SIMSO
CONN
SYSTEM POWER
RJ45
RJ45
Gb LAN FWH
GILGAL
W83627
FDD
Figure 1-9. Block Diagram of the 5000P Chipset
Note: This is a general chipset block diagram. Please see the previous Motherboard
Features pages for details on the features of each motherboard.
1-8
Page 15
Chapter 1: Introduction
1-2 Chipset Overview
Built upon the functionality and the capability of the 5000P chipset, the X7DBR-
8+/X7DBR-i+ motherboard provides the performance and feature set required for
dual processor-based servers with confi guration options optimized for communica-
tions, presentation, storage, computation or database applications. The 5000P
chipset supports a single or dual Dempsey 64-bit dual core processor(s) with front
side bus speeds of up to 1.333 GHz. The chipset consists of the 5000P Memory
Controller Hub (MCH), the Enterprise South Bridge 2 (ESB2), and the I/O subsys-
tem (PXHV).
The 5000P MCH chipset is designed for symmetric multiprocessing across two
independent front side bus interfaces. Each front side bus uses a 64-bit wide, 1333
MHz data bus that transfers data at 10.7 GB/sec. The MCH chipset connects up
to 16 Fully Buffered DIMM modules, providing up to 64 GB of DDR2 FBD ECC
memory. The MCH chipset also provides three x8 PCI-Express and one x4 ESI
interface to the ESB2. In addition, the 5000P chipset offers a wide range of RAS
features, including memory interface ECC, x4/x8 Single Device Data Correction,
CRC, parity protection, memory mirroring and memory sparing.
Xeon Dual Core Processor Features
Designed to be used with conjunction of the 5000P chipset, the Xeon Dual Core
Processor provides a feature set as follows:
The Xeon Dual Core Processor
*L1 Cache Size: Instruction Cache (32KB/16KB), Data Cache (32KB/24KB)
*L2 Cache Size: 4MB/2MB (per core)
*Data Bus Transfer Rate: 8.5 GB/s
*Package: FC-LGA6/FC-LGA4, 771 Lands
1-9
Page 16
X7DBR-8+/X7DBR-i+ User's Manual
1-3 Special Features
Recovery from AC Power Loss
BIOS provides a setting for you to determine how the system will respond when AC
power is lost and then restored to the system. You can choose for the system to
remain powered off (in which case you must hit the power switch to turn it back on) or
for it to automatically return to a power- on state. See the Power Lost Control setting
in the Advanced section to change this setting. (*Note: Default: Last State).
1-4 PC Health Monitoring
This section describes the PC health monitoring features of the X7DBR-8+/X7DBR-
i+. All have an onboard System Hardware Monitor chip that supports PC health
monitoring.
Onboard Voltage Monitors for CPU Cores, Memory, Chipset,
+1.8V, +3.3V, +5V, +12V, −12V, +3.3V Standby, +5V standby and
VBAT
An onboard voltage monitor will scan these voltages continuously. Once a
voltage becomes unstable, a warning is given or an error message is sent to the
screen. Users can adjust the voltage thresholds to defi ne the sensitivity of the
voltage monitor.
Fan Status Monitor with Firmware Control
The PC health monitor can check the RPM status of the cooling fans. The onboard
CPU and chassis fans are controlled by Thermal Management via BIOS (under
Hardware Monitoring in the Advanced Setting).
Environmental Temperature Control
The thermal control sensor monitors the CPU temperature in real time and will turn
on the thermal control fan whenever the CPU temperature exceeds a user-defi ned
threshold. The overheat circuitry runs independently from the CPU. Once it detects
that the CPU temperature is too high, it will automatically turn on the thermal fan
control to prevent any overheat damage to the CPU. The onboard chassis thermal
circuitry can monitor the overall system temperature and alert users when the chas-
sis temperature is too high.
CPU Overheat LED and Control
This feature is available when the user enables the CPU overheat warning function
in the BIOS. This allows the user to defi ne an overheat temperature. When this tem-
perature is exceeded, both the overheat fan and the warning LED are triggered.
System Resource Alert
This feature is available when used with Supero Doctor III in the Windows OS
environment or used with Supero Doctor II in Linux. SDIII is used to notify the
user of certain system events. For example, if the system is running low on virtual
1-10
Page 17
Chapter 1: Introduction
memory and there is insuffi cient hard drive space for saving the data, you can be
alerted of the potential problem.
1-5 ACPI Features
ACPI stands for Advanced Confi guration and Power Interface. The ACPI specifi -
cation defi nes a fl exible and abstract hardware interface that provides a standard
way to integrate power management features throughout a PC system, including its
hardware, operating system and application software. This enables the system to
automatically turn on and off peripherals such as CD-ROMs, network cards, hard
disk drives and printers. This also includes consumer devices connected to the PC
such as VCRs, TVs, telephones and stereos.
In addition to enabling operating system-directed power management, ACPI
provides a generic system event mechanism for Plug and Play and an operating
system-independent interface for confi guration control. ACPI leverages the Plug
and Play BIOS data structures while providing a processor architecture-independent
implementation that is compatible with Windows 2000, Windows XP and Windows
2003 Server Operating Systems.
Slow Blinking LED for Suspend-State Indicator
When the CPU goes into a suspend state, the chassis power LED will start blinking
to indicate that the CPU is in suspend mode. When the user presses any key, the
CPU will wake-up and the LED will automatically stop blinking and remain on.
Main Switch Override Mechanism
When an ATX power supply is used, the power button can function as a system
suspend button to make the system enter a SoftOff state. The monitor will be
suspended and the hard drive will spin down. Pressing the power button again
will cause the whole system to wake-up. During the SoftOff state, the ATX power
supply provides power to keep the required circuitry in the system alive. In case
the system malfunctions and you want to turn off the power, just press and hold
the power button for 4 seconds. This option can be set in the Power section of
the BIOS Setup routine.
External Modem Ring-On
Wake-up events can be triggered by a device such as the external modem ringing
when the system is in the SoftOff state. Note that external modem ring-on can only
be used with an ATX 2.01 (or above) compliant power supply.
Wake-On-LAN (WOL)
Wake-On-LAN is defi ned as the ability of a management application to remotely
power up a computer that is powered off. Remote PC setup, up-dates and asset
tracking can occur after hours and on weekends so that daily LAN traffi c is kept to
a minimum and users are not interrupted. The motherboard has a 3-pin header
(WOL) to connect to the 3-pin header on a Network Interface Card (NIC) that has
WOL capability. Wake-On-LAN must be enabled in BIOS. Note that Wake-On-LAN
can only be used with an ATX 2.01 (or above) compliant power supply.
1-11
Page 18
X7DBR-8+/X7DBR-i+ User's Manual
1-6 Power Supply
As with all computer products, a stable power source is necessary for proper and
reliable operation. It is even more important for processors that have high CPU
clock rates.
The X7DBR-8+/X7DBR-i+ can only accommodate 24-pin ATX power supplies.
Although most power supplies generally meet the specifi cations required by the
CPU, some are inadequate. In addition, the 12V 4-pin and the 12V 8-pin power
connections are also required to ensure adequate power supply to the system.
Also your power supply must supply 1.5A for the Ethernet ports.
It is strongly recommended that you use a high quality power supply that meets ATX
power supply Specifi cation 2.01 or above. It must also be SSI compliant (info at
http://www.ssiforum.org/). Additionally, in areas where noisy power transmission is
present, you may choose to install a line fi lter to shield the computer from noise. It
is recommended that you also install a power surge protector to help avoid problems
caused by power surges.
1-7 Super I/O
The disk drive adapter functions of the Super I/O chip include a fl oppy disk drive
controller that is compatible with industry standard 82077/765, a data separator,
write pre-compensation circuitry, decode logic, data rate selection, a clock genera-
tor, drive interface control logic and interrupt and DMA logic. The wide range of
functions integrated onto the Super I/O greatly reduces the number of components
required for interfacing with fl oppy disk drives. The Super I/O supports 360 K, 720
K, 1.2 M, 1.44 M or 2.88 M disk drives and data transfer rates of 250 Kb/s, 500 Kb/s
or 1 Mb/s.It also provides two high-speed, 16550 compatible serial communication
ports (UARTs), one of which supports serial infrared communication. Each UART in-
cludes a 16-byte send/receive FIFO, a programmable baud rate generator, complete
modem control capability and a processor interrupt system. Both UARTs provide
legacy speed with baud rate of up to 115.2 Kbps as well as an advanced speed
with baud rates of 250 K, 500 K, or 1 Mb/s, which support higher speed modems.
The Super I/O supports one PC-compatible printer port (SPP), Bidirectional Printer
Port (BPP) , Enhanced Parallel Port (EPP) or Extended Capabilities Port (ECP).
The Super I/O provides functions that comply with ACPI (Advanced Confi guration
and Power Interface), which includes support of legacy and ACPI power manage-
ment through an SMI or SCI function pin. It also features auto power management
to reduce power consumption.
The IRQs, DMAs and I/O space resources of the Super I/O can fl exibly adjust
to meet ISA PnP requirements, which support ACPI and APM (Advanced Power
Management).
1-12
Page 19
Chapter 2: Installation
Chapter 2
Installation
2-1 Static-Sensitive Devices
Electric-Static-Discharge (ESD) can damage electronic com ponents. To prevent
damage to your system board, it is important to handle it very carefully. The following
measures are generally suffi cient to protect your equipment from ESD.
Precautions
• Use a grounded wrist strap designed to prevent static discharge.
• Touch a grounded metal object before removing the board from the antistatic
bag.
• Handle the board by its edges only; do not touch its components, peripheral
chips, memory modules or gold contacts.
• When handling chips or modules, avoid touching their pins.
• Put the motherboard and peripherals back into their antistatic bags when not in
use.
• For grounding purposes, make sure your computer chassis provides excellent
conductivity between the power supply, the case, the mounting fasteners and
the motherboard.
• Use only the correct type of onboard CMOS battery as specifi ed by the manu-
facturer. Do not install the onboard battery upside down to avoid possible explo-
sion.
Unpacking
The motherboard is shipped in antistatic packaging to avoid static damage. When
unpacking the board, make sure the person handling it is static protected.
2-1
Page 20
X7DBR-8+/X7DBR-i+ User's Manual
2-2 Processor and Heatsink Fan Installation
When handling the processor package, avoid placing
direct pressure on the label area of the fan.
(*Notes: 1. Always connect the power cord last and always remove it before adding,
removing or changing any hardware components. Make sure that you install the
processor into the CPU socket before you install the CPU heatsink.
2. Intel's boxed Xeon CPU package contains the CPU fan and heatsink assembly.
If you buy a CPU separately, make sure that you use only Intel-certifi ed multi-di-
rectional heatsink and fan.
3. Make sure to install the motherboard into the chassis before you install the CPU
heatsink and fan.)
4. When purchasing an LGA 771 CPU or when receiving a motherboard with an LGA
771 CPU pre-installed, make sure that the CPU plastic cap is in place and none of
the CPU pins are bent; otherwise, contact the retailer immediately.
5. Refer to the MB Features Section for more details on CPU support.
!
Installation of the LGA771 Processor
1. Press the socket clip to release
the load plate, which covers the CPU
socket, from its locking position.
2. Gently lift the socket clip to open
the load plate.
Socket Clip
Load Plate
Load Plate
2-2
Page 21
Chapter 2: Installation
3. Use your thumb and your index
fi nger to hold the CPU at the North
Center Edge and the South Center
Edge of the CPU.
4. Align CPU Pin1 (the CPU corner
marked with a triangle) against the
socket corner that is marked with a
triangle cutout.
5. Align the CPU key that is the
semi-circle cutout below a gold dot
against the socket key, the notch on
the same side of the triangle cutout
on the socket.
6. Once aligned, carefully lower the
CPU straight down to the socket.
(**Do not drop the CPU on the
socket. Do not move the CPU hori-
zontally or vertically. Do not rub the
CPU against the surface or against
any pins of the socket to avoid dam-
age to the CPU or the socket.)
Socket Key
(Socket Notch)
CPU Key (semi-
circle cutout)
below the circle.
Corner with a
triangle cutout
North Center Edge
South Center Edge
gold dot
CPU Pin1
7. With the CPU inside the socket,
inspect the four corners of the CPU
to make sure that the CPU is prop-
erly installed.
8. Use your thumb to gently push the
socket clip down to the clip lock.
9. If the CPU is properly installed
into the socket, the plastic cap will
be automatically released from the
load plate when the clip is pushed in
the clip lock. Remove the plastic cap
from the motherboard.
!
(*Warning: Please keep the
plastic cap. The motherboard and the
CPU must be shipped with the plas-
tic cap properly installed to protect
the CPU pins. Shipment without the
CPU plastic cap properly installed
will void the warranty.)
Socket clip
CPU in the CPU socket
Plastic cap
is released
from the
load plate
if the CPU
is properly
installed.
2-3
Page 22
X7DBR-8+/X7DBR-i+ User's Manual
Installation of the Heatsink
CEK Heatsink Installation
1. Do not apply any thermal grease to
the heatsink or the CPU die-the required
amount has already been applied.
2. Place the heatsink on top of the
CPU so that the four mounting holes
are aligned with those on the retention
mechanism.
3. Screw in two diagonal screws (ie the
#1 and the #2 screws) until just snug (-do
not fully tighten the screws to avoid pos-
sible damage to the CPU.)
4. Finish the installation by fully tightening
all four screws.
CEK Passive Heatsink
Screw#1 Screw#2
Screw#1
To Un-install the Heatsink
(Warning: We do not recommend
that the CPU or the heatsink be
!
removed. However, if you do need
to uninstall the heatsink, please
follow the instructions below to
uninstall the heatsink to prevent
damage done to the CPU or the
CPU socket.)
Screw#2
2-4
Page 23
1. Unscrew and remove the heatsink
screws from the motherboard in the
sequence as show in the picture on the
right.
2. Hold the heatsink as show in the picture on the right and gently wiggle the
heatsink to loosen it from the CPU. (Do
not use excessive force when wiggling
the heatsink!!)
3. Once the heatsink is loosened, remove
the heatsink from the CPU socket.
Chapter 2: Installation
4. Clean the surface of the CPU and
the heatsink to get rid of the old thermal
grease. Reapply the proper amount of
thermal grease on the surface before you
re-install the CPU and the heatsink.
Mounting the Motherboard in the Chassis
All motherboards have standard mounting holes to fi t different types of chas-
sis. Make sure that the locations of all the mounting holes for both motherboard
and chassis match. Make sure that the metal standoffs click in or are screwed in
tightly. Then, use a screwdriver to secure the motherboard onto the motherboard
tray. (*Note: some components are very close to the mounting holes. Please take
precautionary measures to prevent damage done to these components when you
install the motherboard to the chassis.)
2-5
Page 24
X7DBR-8+/X7DBR-i+ User's Manual
2-3 Installing DIMMs
Note: Check the Supermicro web site for recommended memory modules.
CAUTION
Exercise extreme care when installing or removing DIMM
modules to prevent any possible damage. Also note that the
memory is interleaved to improve performance (see step 1).
DIMM Installation (See Figure 2-2)
1. Insert the desired number of DIMMs into the memory slots, starting with DIMM
#1A. The memory scheme is interleaved so you must install two modules
at a time, beginning with DIMM #1A, then DIMM #2A and so on. (*See the
Memory Installation Table Below.)
2. Insert each DIMM module vertically into its slot. Pay attention to the notch along
the bottom of the module to prevent inserting the DIMM module incorrectly.
3. Gently press down on the DIMM module until it snaps into place in the slot.
Repeat for all modules (see step 1 above).
Memory Support
The X7DBR-8+/X7DBR-i+ supports up to 64 GB fully buffered (FBD) ECC DDR2
533/667 in 16 DIMMs. Populating DIMM modules with pairs of memory modules
of the same size and same type will result in Interleaved Memory which will
increase memory performance.
*Note 1: Due to OS limitations, some operating systems may not show more than
4 GB of memory.
Optimized DIMM Population Configurations
Branch 0 Branch 1
Number of
DIMMs
2 DIMMs 1A --- --- --- 2A --- --- --- --- --- --- --- --- --- --- --4 DIMMs 1A --- --- --- 2A --- --- --- 3A --- --- --- 4A --- --- --6 DIMMs 1A 1B --- --- 2A 2B --- --- 3A --- --- --- 4A --- --- --8 DIMMs 1A 1B --- --- 2A 2B --- --- 3A 3B --- --- 4A 4B --- --10 DIMMs 1A 1B 1C --- 2A 2B 2C --- 3A 3B --- --- 4A 4B --- --12 DIMMs 1A 1B 1C --- 2A 2B 2C --- 3A 3B 3C --- 4A 4B 4C --14 DIMMs 1A 1B 1C 1D 2A 2B 2C 2D 3A 3B 3C --- 4A 4B 4C --16 DIMMs 1A 1B 1C 1D 2A 2B 2C 2D 3A 3B 3C 3D 4A 4B 4C 4D
Bank 1
(Channel 0)
Bank 2
(Channel 1)
Bank 3
(Channel 2)
Bank 4
(Channel 3)
(*Notes: i. DIMM slot# specified: DIMM slot to be populated; “---“: DIMM slot not
to be populated. ii. Both FBD 533 MHz and 667MHz DIMMs are supported;
however, you need to use the memory modules of the same speed and of the
same type on a motherboard. iii. Interleaved memory is supported when pairs
of DIMM modules are installed. For best performance, please install memory
modules of the same speed and same type in both Branch 0 and Branch 1. iv.
For memory to work properly, you need to follow the restrictions listed above. )
2-6
Page 25
Chapter 2: Installation
*Note 2: Due to memory allocation to system devices, memory remaining avail-
able for operational use will be reduced when 4 GB of RAM is used. The reduction
in memory availability is disproportional. (Refer to the Memory Availability Table
below for details.)
Possible System Memory Allocation & Availability
System Device Size Physical Memory
Firmware Hub fl ash memory
(System BIOS)
Local APIC 4 KB 3.99
Area Reserved for the chipset 2 MB 3.99
I/O APIC (4 Kbytes) 4 KB 3.99
PCI Enumeration Area 1 256 MB 3.76
PCI Express (256 MB) 256 MB 3.51
PCI Enumeration Area 2 (if
needed) -Aligned on 256-MB
boundary-
VGA Memory 16 MB 2.85
TSEG 1 MB 2.84
Memory available to BIOS,
OS, applications
1 MB 3.99
512 MB 3.01
Remaining (-Available)
(4 GB Total System Memory)
2.84
Figure 2-2. Installing and Removing DIMMs
2 FBD
®
UPER X7DBR-8/i+
S
To Remove:
Use your thumbs to
gently push the release tabs near both
ends of the module.
This should release
it from the slot.
JA1
To Install: Insert module vertically and press down until it
snaps into place. Pay attention to the alignment notch at
the bottom.
2 FBD Slot
2-7
Page 26
X7DBR-8+/X7DBR-i+ User's Manual
2-4 Control Panel Connectors/IO Ports
The I/O ports are color coded in conformance with the PC 99 specifi cation. See
Figure 2-3 below for the colors and locations of the various I/O ports.
A. Back Panel Connectors/IO Ports
4
®
UPER X7DBR-8/i+
S
2
1
JA1
3
5
7
6
8 9
Figure 2-3. Back Panel I/O Port Locations and Defi nitions
Back Panel Connectors
1. Keyboard (Purple)
2. PS/2 Mouse (Green)
3. Back Panel USB Port 0
4. Back Panel USB Port 1
5. COM Port 1 (Turquoise)
6. Gigabit LAN 1
7. Gigabit LAN 2
8. VGA Port (Blue)
9. SCSI (Channel B)
(*See Section 2-5 for details.)
2-8
Page 27
Chapter 2: Installation
B. Front Control Panel
JF1 contains header pins for various buttons and indicators that are normally located
on a control panel at the front of the chassis. These connectors are designed specifi -
cally for use with Supermicro server chassis. See Figure 2-4 for the descriptions of
the various control panel buttons and LED indicators. Refer to the following section
for descriptions and pin defi nitions.
Figure 2-4. JF1 Header Pins
1920
Ground
NMI
®
UPER X7DBR-8/i+
S
Power LED
HDD LED
NIC1 LED
NIC2 LED
OH/Fan Fail LED
1
JA
PWR Fail LED
X
Ground
Ground
X
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Reset
PWR
2
1
Reset Button
Power Button
2-9
Page 28
X7DBR-8+/X7DBR-i+ User's Manual
C. Front Control Panel Pin Defi nitions
NMI Button
The non-maskable interrupt button
header is located on pins 19 and 20
of JF1. Refer to the table on the right
for pin defi nitions.
Power LED
The Power LED connection is located
on pins 15 and 16 of JF1. Refer to the
table on the right for pin defi nitions.
NMI Button
Pin Defi nitions (JF1)
Pin# Defi nition
19 Control
20 Ground
Power LED
Pin Defi nitions (JF1)
Pin# Defi nition
15 +5V
16 Ground
A. NMI
B. PWR LED
UID-
Switch
Bank4
KB
MS
USB0/1
Bank3
COM1
Bank2
Bank1
UPER X7DBR-8/i+
S
Slot7
GLAN2
A
VG
n. B
SI Chan
SC
/SE
LVD
320
U
JCOM2
VGA
CTRLR
Slot6
JPG1
GLAN
CTRLR
SE8C
SIMSO
GLAN1
®
JPCIE3
PCI-X 133MHz
Battery
PXH-V
DIMM 4D (Bank 4)
DIMM 4C (Bank 4)
DIMM 4B (Bank 4)
DIMM 4A (Bank 4)
DIMM 3D (Bank 3)
DIMM 3C (Bank 3)
DIMM 3B (Bank 3)
DIMM 3A (Bank 3)
DIMM 2D (Bank 2)
DIMM 2C (Bank 2)
DIMM 2B (Bank 2)
DIMM 2A (Bank 2)
DIMM 1D (Bank 1)
DIMM 1C (Bank 1)
DIMM 1B (Bank 1)
DIMM 1A (Bank 1)
2
2
JI
C
2
J
I
C
1
JPA1
3
2
A
JP
JPA
SCSI
CTRLR
SO 100MH
z ZCR1
North Bridge
DA2
WOR
1920
4-pin
8-pin
ATX Main
PWR
SMBus
PWR
JPWF
1
PWR Fail
R
JA
CPU1
CPU2
SXB-
SXB-
PCI-Ex8
PCI-Ex8
Buzzer
South
Bridge
SMB
USB4
USB2/3
J4E3
WOL
PWR
PWR
JPL1
JPL2
SATA1
SATA0
JBT1
S/IO
SATA3
SATA2
Pin 1
JWF1
JCF1
J7
B
IO
SATA
SATA4
FP Control
JUID1
JOH1
Compact Flash
S
5
JWD
JL1
UIDSwitch
JP1
Fan1
Fan2
Fan3
Fan4
Fan5
E1
ID
U320 LVD/SE
Channel A
JA1
B
SPKPW LED
OH/Fan Fail LED
Floppy
DA1
Ground
Power LED
HDD LED
NIC1 LED
NIC2 LED
PWR Fail LED
Ground
Ground
NMI
A
X
X
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Reset
Reset Button
Power Button
PWR
2
1
2-10
Page 29
Chapter 2: Installation
HDD LED
The HDD LED connection is located
on pins 13 and 14 of JF1. Attach the
hard drive LED cable here to display
disk activity (for any hard drives on
the system, including SAS, Serial ATA
and IDE). See the table on the right
for pin defi nitions.
NIC1/NIC2 LED Indicators
The NIC (Network Interface Control-
ler) LED connection for GLAN port1 is
located on pins 11 and 12 of JF1 and
the LED connection for GLAN Port2
is on Pins 9 and 10. Attach the NIC
LED cables to display network activity.
Refer to the table on the right for pin
defi nitions.
HDD LED
Pin Defi nitions (JF1)
Pin# Defi nition
13 +5V
14 HD Active
GLAN1/2 LED
Pin Defi nitions (JF1)
Pin# Defi nition
9/11 Vcc
10/12 PWR Fail
A. HDD LED
B. NIC1 LED
C. NIC2 LED
itch
UID-
Sw
Bank4
KB
MS
USB0/1
Bank3
COM1
Bank2
Bank1
UPER
S
Slot7
GLAN1
Slot6
JPG1
GLAN2
GLAN
CTRLR
VGA
VGA
CTRLR
LVD/SE
U320
SCSI Chann. B
SIMSO
JCOM2
SE8C
JPCIE3
PCI-X 133MHz
Battery
PXH-V
®
DIMM 4D (Bank 4)
DIMM 4C (Bank 4)
DIMM 4B (Bank 4)
DIMM 4A (Bank 4)
DIMM 3D (Bank 3)
DIMM 3C (Bank 3)
DIMM 3B (Bank 3)
DIMM 3A (Bank 3)
DIMM 2D (Bank 2)
DIMM 2C (Bank 2)
DIMM 2B (Bank 2)
DIMM 2A (Bank 2)
DIMM 1D (Bank 1)
DIMM 1C (Bank 1)
DIMM 1B (Bank 1)
DIMM 1A (Bank 1)
X7DBR-8/i+
2
2
JI
C2
JI
C1
JPA1
JPA3
JPA2
SCSI
CTRLR
SO 100MHz ZC
North Bridge
DA2
R1
4-pin
JPL1
JPL2
SATA1
SATA0
JBT1
S/IO
SATA3
SATA2
PWR
Pin 1
J7
8-pin
PWR
JWF1
JCF1
SATA5
SATA4
BIOS
FP Control
UIDSwitch
JUID1
JOH1
JP1
Fan1
Fan2
IDE1
Compact Flash
Channel A
JWD
J
L
1
SPKPW LED
Fan3
Fan4
Fan5
Floppy
U320 LVD/SE
JA1
DA1
Ground
X
Power LED
HDD LED
A
B
NIC1 LED
NIC2 LED
C
OH/Fan Fail LED
PWR Fail LED
Ground
Ground
1920
NMI
X
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Reset
Reset Button
Power Button
PWR
2
1
ATX Main
SMBus
PWR
PWR
JPWF
PWR Fail
JAR1
CPU1
CPU2
SXB-
SXB-
PCI-Ex8
PCI-Ex8
Buzzer
South
Bridge
SMB
USB4
WOR
WOL
USB2/3
J4E3
2-11
Page 30
X7DBR-8+/X7DBR-i+ User's Manual
Overheat/Fan Fail LED (OH)
Connect an LED to the OH/Fan Fail
connection on pins 7 and 8 of JF1 to
provide advanced warning of chassis
overheating or fan failure. Refer to
the table on the right for pin defi ni-
tions.
Power Fail LED
The Power Fail LED connection is
located on pins 5 and 6 of JF1. Re-
fer to the table on the right for pin
defi nitions.
OH/Fan Fail LED
Pin Defi nitions (JF1)
Pin# Defi nition
7 Vcc
8 Ground
OH/Fan Fail Indicator
Status
State Defi nition
Off Normal
On Overheat
Flash-
Fan Fail
ing
PWR Fail LED
Pin Defi nitions (JF1)
Pin# Defi nition
5 Vcc
6 Ground
A. OH/Fan Fail LED
B. PWR Supply Fail
Bank4
Bank3
Bank2
Bank1
UPER
Slot7
SE8C
Slot6
PCI-X 133MHz
JPG1
GLAN
CTRLR
PXH-V
SIMSO
DIMM 4D (Bank 4)
DIMM 4C (Bank 4)
DIMM 4B (Bank 4)
DIMM 4A (Bank 4)
DIMM 3D (Bank 3)
DIMM 3C (Bank 3)
DIMM 3B (Bank 3)
DIMM 3A (Bank 3)
DIMM 2D (Bank 2)
DIMM 2C (Bank 2)
DIMM 2B (Bank 2)
DIMM 2A (Bank 2)
DIMM 1D (Bank 1)
DIMM 1C (Bank 1)
DIMM 1B (Bank 1)
DIMM 1A (Bank 1)
®
X7DBR-8/i+
JPCIE3
Battery
UID-
Switch
KB
MS
USB0/1
COM1
GLAN1
GLAN2
VGA
LVD/SE
U320
SCSI Chann. B
JCOM2
VGA
CTRLR
S
2
JI
JI
C1
JPA1
JPA3
JPA2
SO 100MHz ZC
2
C2
SCSI
CTRLR
North Bridge
DA2
R1
4-pin
JPL1
JPL2
SATA1
SATA0
JBT1
S/IO
SATA3
SATA2
PWR
8-pin
PWR
Pin 1
JWF1
JCF1
J7
BIO
SATA5
SATA4
FP Control
JUID1
JOH1
Compact Flash
S
JWD
J
L1
UIDSwitch
JP1
Fan1
Fan2
Fan3
Fan4
Fan5
IDE1
U320 LVD/SE
Channel A
JA1
SPKPW LED
Floppy
DA1
Ground
X
Power LED
HDD LED
NIC1 LED
NIC2 LED
OH/Fan Fail LED
A
PWR Fail LED
B
Ground
Ground
ATX Main
SMBus
PWR
PWR
JPWF
PWR Fail
JAR1
CPU1
CPU2
SXB-
SXB-
PCI-Ex8
PCI-Ex8
Buzzer
South
Bridge
SMB
USB4
WOR
WOL
USB2/3
J4E3
1920
NMI
X
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Reset
Reset Button
Power Button
PWR
2
1
2-12
Page 31
Reset Button
Chapter 2: Installation
The Reset Button connection is located
on pins 3 and 4 of JF1. Attach it to the
hardware reset switch on the computer
case. Refer to the table on the right for
pin defi nitions.
Power Button
The Power Button connection is located
on pins 1 and 2 of JF1. Momentarily
contacting both pins will power on/off
the system. This button can also be
confi gured to function as a suspend but-
ton (with a setting in BIOS - see Chapter
4). To turn off the power when set to
suspend mode, press the button for at
least 4 seconds. Refer to the table on
the right for pin defi nitions.
Reset Button
Pin Defi nitions (JF1)
Pin# Defi nition
3 Reset
4 Ground
Power Button
Pin Defi nitions (JF1)
Pin# Defi nition
1 Signal
2 +3V Standby
A. Reset Button
B. PWR Button
itch
UID-
Sw
Bank4
KB
MS
USB0/1
Bank3
COM1
Bank2
Bank1
UPER
S
Slot7
VGA
VGA
CTRLR
LVD/SE
U320
SCSI Chann. B
JCOM2
Slot6
JPG1
GLAN
CTRLR
SE8C
SIMSO
JPCIE3
PCI-X 133MHz
PXH-V
GLAN1
GLAN2
DIMM 4D (Bank 4)
DIMM 4C (Bank 4)
DIMM 4B (Bank 4)
DIMM 4A (Bank 4)
DIMM 3D (Bank 3)
DIMM 3C (Bank 3)
DIMM 3B (Bank 3)
DIMM 3A (Bank 3)
DIMM 2D (Bank 2)
DIMM 2C (Bank 2)
DIMM 2B (Bank 2)
DIMM 2A (Bank 2)
DIMM 1D (Bank 1)
DIMM 1C (Bank 1)
DIMM 1B (Bank 1)
DIMM 1A (Bank 1)
®
X7DBR-8/i+
JI
Battery
2
2
JI
C2
C1
JPA1
JPA3
JPA2
SCSI
CTRLR
SO 100MHz ZC
North Bridge
DA2
R1
4-pin
JPL1
JPL2
SATA1
SATA0
JBT1
S/IO
SATA3
SATA2
PWR
8-pin
PWR
Pin 1
JWF1
JCF1
J7
BIOS
SATA5
SATA4
FP Control
UIDSwitch
JUID1
JOH1
JP1
Fan1
Fan2
IDE1
Compact Flash
Channel A
JWD
J
L
1
SPKPW LED
Fan3
Fan4
OH/Fan Fail LED
Fan5
Floppy
U320 LVD/SE
JA1
DA1
Ground
X
Power LED
HDD LED
NIC1 LED
NIC2 LED
PWR Fail LED
Ground
Ground
ATX Main
SMBus
PWR
PWR
JPWF
PWR Fail
JAR1
CPU1
CPU2
SXB-
SXB-
PCI-Ex8
PCI-Ex8
Buzzer
South
Bridge
SMB
USB4
WOR
WOL
USB2/3
J4E3
1920
NMI
X
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Reset
Reset Button
A
Power Button
PWR
2
1
B
2-13
Page 32
X7DBR-8+/X7DBR-i+ User's Manual
2-5 Connecting Cables
ATX Power Connector
There are a 24-pin main power supply
connector(JPW1) and an 8-pin CPU
PWR connector (JPW3) on the moth-
erboard. These power connectors
meet the SSI EPS 12V specifi cation.
The 4-pin 12V PWR supply is required
to provide adequate power to the sys-
tem. See the table on the right for pin
defi nitions for connector (JPW1). For
the 8-pin PWR (JPW3), please refer
to the item listed below.
Processor Power Connector
In addition to the Primary ATX power
connector (above), the 12V 8-pin CPU
PWR connector at JPW3 must also
be connected to your power supply.
See the table on the right for pin
defi nitions.
A
UID-
Switch
KB
MS
USB0/1
COM1
Bank4
Bank3
Bank2
Bank1
UPER X7DBR-8/i+
S
Slot7
GLAN1
Slot6
JPG1
GLAN2
GLAN
CTRLR
VGA
VGA
CTRLR
LVD/SE
U320
SCSI Chann. B
SIMSO
JCOM2
®
SE8C
JPCIE3
PCI-X 133MHz
Battery
PXH-V
DIMM 4D (Bank 4)
DIMM 4C (Bank 4)
DIMM 4B (Bank 4)
DIMM 4A (Bank 4)
DIMM 3D (Bank 3)
DIMM 3C (Bank 3)
DIMM 3B (Bank 3)
DIMM 3A (Bank 3)
DIMM 2D (Bank 2)
DIMM 2C (Bank 2)
DIMM 2B (Bank 2)
DIMM 2A (Bank 2)
DIMM 1D (Bank 1)
DIMM 1C (Bank 1)
DIMM 1B (Bank 1)
DIMM 1A (Bank 1)
2
2
JI
C2
JI
C1
JPA1
JPA3
JPA2
SCSI
CTRLR
SO 100MHz ZCR1
North Bridge
DA2
WOR
WOL
SXB-
Buzzer
PCI-Ex8
SMB
JPWF
SXB-
J4E3
SMBus
PWR
JAR1
PCI-Ex8
South
Bridge
USB4
PWR Fail
USB2/3
ATX Main
PWR
CPU1
CPU2
JPL1
JPL2
SATA1
SATA0
JBT1
S/IO
SATA3
SATA2
ATX Power 20-pin Connector
Pin Defi nitions
Pin# Defi nition Pin # Defi nition
13 +3.3V 1 +3.3V
14 -12V 2 +3.3V
15 COM 3 COM
16 PS_ON 4 +5V
17 COM 5 COM
18 COM 6 +5V
19 COM 7 COM
20 Res (NC) 8 PWR_OK
21 +5V 9 5VSB
22 +5V 10 +12V
23 +5V 11 +12V
24 COM 12 +3.3V
Required Connection
12V 4-pin Power Con-
Pin Defi nitions
Pins Defi nition
1 and 2 Ground
3 and 4 +12V
Required Connection
12V 8-pin Power CPU
C
4-pin
PWR
8-pin
PWR
B
FP Control
UIDSwitch
JUID1
JOH1
JP1
Fan1
Connector
Pin Defi nitions
Pins Defi nition
1 through 4 Ground
5 through 8 +12V
A. 24-pin ATX PWR
Fan2
SPKPW LED
B. 8-pin Processor PWR
C. 4-pin PWR
Fan3
Fan4
JWF1
Fan5
JCF1
IDE1
Compact Flash
Floppy
J7
BIOS
SATA5
SATA4
JWD
JL1
U320 LVD/SE
Channel A
JA1
DA1
nector
2-14
Page 33
Chapter 2: Installation
Universal Serial Bus (USB)
There are fi ve USB 2.0 (Universal
Serial Bus) ports/headers on the
motherboard. Two of them are Back
Panel USB ports (USB#0/1:JUSB1),
and the other are Front Panel USB
headers (USB#2/3:JUSB2, USB#4:
JUSB3). See the tables on the right
for pin defi nitions.
Chassis Intrusion
A Chassis Intrusion header is located
at JL1. Attach the appropriate cable
from the chassis to inform you of a
chassis intrusion when the chassis is
opened.
Back Panel USB
(USB0/1)
Pin# Defi nitions
1 +5V
2PO-
3PO+
4 Ground
5N/A
Front Panel USB
(USB4)
Pin# Defi nitions
1 +5V
2PO-
3PO+
4 Ground
5Key
Chassis Intrusion
Pin Defi nitions (JL1)
Pin# Defi nition
1 Intrusion Input
2 Ground
Front Panel USB
(USB2/3)
Pin# Defi nition
1 Vcc
2 Data-
3 Data+
4 Ground
5NA
UID-
Switch
KB
MS
USB0/1
COM1
Bank4
Bank3
A
Bank2
Bank1
UPER X7DBR-8/i+
S
Slot7
GLAN1
Slot6
JPG1
GLAN2
GLAN
CTRLR
VGA
VGA
CTRLR
LVD/SE
U320
SCSI Chann. B
SIMS
JCOM2
®
SE8C
JPCIE3
PCI-X 133MHz
Battery
PXH-V
O
DIMM 4D (Bank 4)
DIMM 4C (Bank 4)
DIMM 4B (Bank 4)
DIMM 4A (Bank 4)
DIMM 3D (Bank 3)
DIMM 3C (Bank 3)
DIMM 3B (Bank 3)
DIMM 3A (Bank 3)
DIMM 2D (Bank 2)
DIMM 2C (Bank 2)
DIMM 2B (Bank 2)
DIMM 2A (Bank 2)
DIMM 1D (Bank 1)
DIMM 1C (Bank 1)
DIMM 1B (Bank 1)
DIMM 1A (Bank 1)
2
2
JI
C2
JI
C1
JPA1
JPA3
JPA2
SCSI
CTRLR
SO 100MHz ZCR1
North Bridge
DA2
WOR
WOL
SXB-
Buzzer
PCI-Ex8
SMB
J4E3
JPWF
SXB-
SMBus
PWR
JAR1
PCI-Ex8
South
Bridge
C
USB4
PWR Fail
B
USB2/3
ATX Main
PWR
CPU1
CPU2
JPL1
JPL2
SATA1
SATA0
JBT1
4-pin
PWR
S/IO
SATA3
SATA2
J7
8-pin
PWR
JWF1
JCF1
BIOS
SATA5
SATA4
FP Control
UIDSwitch
JUID1
JOH1
JP1
Fan1
Fan2
Fan3
Fan4
Fan5
IDE1
Compact Flash
U320 LVD/SE
Channel A
JA1
JWD
DA1
JL1
A. Backpanel USB 0-1
B. Front Panel USB 2-3
C. Front Panel USB 4
D. Chassis Intrusion
SPKPW LED
Floppy
D
2-15
Page 34
X7DBR-8+/X7DBR-i+ User's Manual
Fan Headers
The X7DBR-8+/X7DBR-i+ has five chas-
sis/system fan headers (Fan1 to Fan5.) See
the table on the right for pin defi nitions. (*The
onboard fan speeds are controlled by Thermal
Management via BIOS Hardware Monitor in the
Advanced Setting
. Note: Default: Disabled.)
Fan Header
Pin Defi nitions
Pin# Defi nition
1 Ground
2 +12V
3 Tachometer
UID-
Switch
KB
MS
USB0/1
COM1
Bank4
Bank3
Bank2
Bank1
UPER X7DBR-8/i+
S
Slot7
GLAN1
Slot6
JPG1
GLAN2
GLAN
CTRLR
VGA
VGA
CTRLR
LVD/SE
U320
SCSI Chann. B
SIMSO
JCOM2
®
SE8C
JPCIE3
PCI-X 133MHz
Battery
PXH-V
DIMM 4D (Bank 4)
DIMM 4C (Bank 4)
DIMM 4B (Bank 4)
DIMM 4A (Bank 4)
DIMM 3D (Bank 3)
DIMM 3C (Bank 3)
DIMM 3B (Bank 3)
DIMM 3A (Bank 3)
DIMM 2D (Bank 2)
DIMM 2C (Bank 2)
DIMM 2B (Bank 2)
DIMM 2A (Bank 2)
DIMM 1D (Bank 1)
DIMM 1C (Bank 1)
DIMM 1B (Bank 1)
DIMM 1A (Bank 1)
2
2
JI
C2
JI
C1
JPA1
JPA3
JPA2
SCSI
CTRLR
SO 100MHz ZCR1
North Bridge
DA2
WOR
WOL
SXB-
Buzzer
PCI-Ex8
SMB
J4E3
JPWF
SXB-
SMBus
PWR
JAR1
PCI-Ex8
South
Bridge
USB4
PWR Fail
USB2/3
ATX Main
PWR
CPU1
CPU2
JPL1
JPL2
SATA1
SATA0
JBT1
4-pin
PWR
S/IO
SATA3
SATA2
J7
8-pin
PWR
JWF1
JCF1
BIOS
SATA5
SATA4
FP Control
UIDSwitch
JUID1
JOH1
JP1
Fan1
Fan2
Fan3
Fan4
Fan5
IDE1
Compact Flash
U320 LVD/SE
Channel A
JA1
JWD
DA1
JL1
SPKPW LED
Floppy
A. Fan 1
B. Fan 2
C. Fan 3
D. Fan 4
A
E. Fan 5
B
C
D
E
2-16
Page 35
Chapter 2: Installation
ATX PS/2 Keyboard and
PS/2 Mouse Ports
The ATX PS/2 keyboard and the PS/2
mouse ports are located at JKM and
JMS. See the table on the right for pin
defi nitions. (The mouse port is above
the keyboard port. See the table on
the right for pin defi nitions.)
Serial Ports
COM1 is a connector located on the
IO Backpanel and COM2 is a header
located at JCOM2. See the table on
the right for pin defi nitions.
PS/2 Keyboard and
Mouse Port Pin
Defi nitions
Pin# Defi nition
1 Data
2NC
3 Ground
4 VCC
5Clock
6NC
Serial Port Pin Defi nitions
(COM1/COM2)
Pin # Defi nition Pin # Defi nition
1 CD 6 DSR
2RD 7 RTS
3 TD 8 CTS
4DTR 9 RI
5 Ground 10 NC
UID-
Switch
KB
MS
USB0/1
COM1
Bank4
A
B
Bank3
C
Bank2
Bank1
UPER X7DBR-8/i+
S
Slot7
GLAN1
Slot6
JPG1
GLAN2
GLAN
CTRLR
VGA
VGA
CTRLR
LVD/SE
U320
SCSI Chann. B
D
SIMS
JCOM2
®
SE8C
JPCIE3
PCI-X 133MHz
Battery
PXH-V
O
DIMM 4D (Bank 4)
DIMM 4C (Bank 4)
DIMM 4B (Bank 4)
DIMM 4A (Bank 4)
DIMM 3D (Bank 3)
DIMM 3C (Bank 3)
DIMM 3B (Bank 3)
DIMM 3A (Bank 3)
DIMM 2D (Bank 2)
DIMM 2C (Bank 2)
DIMM 2B (Bank 2)
DIMM 2A (Bank 2)
DIMM 1D (Bank 1)
DIMM 1C (Bank 1)
DIMM 1B (Bank 1)
DIMM 1A (Bank 1)
2
2
JI
C2
JI
C1
JPA1
JPA3
JPA2
SCSI
CTRLR
SO 100MHz ZCR1
North Bridge
DA2
WOR
WOL
SXB-
Buzzer
PCI-Ex8
SMB
J4E3
JPWF
SXB-
SMBus
PWR
JAR1
PCI-Ex8
South
Bridge
USB4
PWR Fail
USB2/3
ATX Main
PWR
CPU1
CPU2
JPL1
JPL2
SATA1
SATA0
JBT1
4-pin
PWR
S/IO
SATA3
SATA2
J7
8-pin
PWR
JWF1
JCF1
BIOS
SATA5
SATA4
(Pin 10 is available on COM2
only. NC: No Connection.)
A. Keyboard
FP Control
UIDSwitch
JUID1
JOH1
JP1
Fan1
Fan2
Fan3
Fan4
Fan5
IDE1
Compact Flash
U320 LVD/SE
Channel A
JA1
JWD
DA1
JL1
SPKPW LED
Floppy
B. Mouse
C. COM1
D. COM2
2-17
Page 36
X7DBR-8+/X7DBR-i+ User's Manual
Wake-On-Ring
The Wake-On-Ring header is desig-
nated JWOR. This function allows
your computer to receive and be
"woken up" by an incoming call to the
modem when the system is in sus-
pend state. See the table on the right
for pin defi nitions. You must have a
Wake-On-Ring card and cable to use
this feature.
Wake-On-LAN
The Wake-On-LAN header is located
at JWOL1 on the motherboard. See
the table on the right for pin defi ni-
tions. (You must also have a LAN
card with a Wake-On-LAN connector
and cable to use this feature.)
Wake-On-Ring
Pin Defi nitions
Pin# Defi nition
1 Ground
2 Wake-up
Wake-On-LAN
Pin Defi nitions
Pin# Defi nition
1 +5V Standby
2 Ground
3 Wake-up
UID-
Switch
KB
MS
USB0/1
COM1
GLAN1
GLAN2
VGA
LVD/SE
U320
SCSI Chann. B
JCOM2
UPER
S
Slot6
JPG1
GLAN
CTRLR
VGA
CTRLR
Bank4
Bank3
Bank2
Bank1
Slot7
SE8C
SIMS
DIMM 4D (Bank 4)
DIMM 4C (Bank 4)
DIMM 4B (Bank 4)
DIMM 4A (Bank 4)
DIMM 3D (Bank 3)
DIMM 3C (Bank 3)
DIMM 3B (Bank 3)
DIMM 3A (Bank 3)
DIMM 2D (Bank 2)
DIMM 2C (Bank 2)
DIMM 2B (Bank 2)
DIMM 2A (Bank 2)
DIMM 1D (Bank 1)
DIMM 1C (Bank 1)
DIMM 1B (Bank 1)
DIMM 1A (Bank 1)
®
X7DBR-8/i+
JPCIE3
PCI-X 133MHz
Battery
PXH-V
O
2
2
JI
C2
JI
C1
JPA1
JPA3
JPA2
SCSI
CTRLR
SO 100MHz ZCR1
North Bridge
DA2
A
WOR
WOL
SXB-
Buzzer
B
PCI-Ex8
SMB
J4E3
JPWF
SXB-
SMBus
PWR
JAR1
PCI-Ex8
South
Bridge
USB4
PWR Fail
USB2/3
ATX Main
PWR
CPU1
CPU2
JPL1
JPL2
SATA1
SATA0
JBT1
4-pin
PWR
S/IO
SATA3
SATA2
J7
8-pin
PWR
JWF1
JCF1
BIOS
SATA5
SATA4
FP Control
UIDSwitch
JUID1
JOH1
JP1
Fan1
Fan2
Fan3
Fan4
Fan5
IDE1
Compact Flash
U320 LVD/SE
Channel A
JA1
JWD
DA1
JL1
A. WOR
B. WOL
SPKPW LED
Floppy
2-18
Page 37
GLAN 1/2 (Giga-bit Ethernet
Ports)
Two G-bit Ethernet ports are desig-
nated JLAN1 and JLAN2 on the IO
backplane. This port accepts RJ45
type cables.
Power LED/Speaker
Chapter 2: Installation
GLAN1 GLAN2
On the JD1 header, pins 1-3 are for
a power LED and pins 4-7 are for the
speaker.. See the table on the right
for speaker pin definitions. Note:
The speaker connector pins are for
use with an external speaker. If you
wish to use the onboard speaker, you
should close pins 6-7 with a jumper.
UID-
KB
MS
USB0/1
COM1
A
GLAN1
GLAN2
VGA
LVD/SE
U320
SCSI Chann. B
Switch
Bank4
Bank3
Bank2
Bank1
®
UPER X7DBR-8/i+
S
Slot7
SE8C
JPCIE3
Slot6
PCI-X 133MHz
JPG1
Battery
GLAN
CTRLR
PXH-V
VGA
CTRLR
O
SIMS
JCOM2
DIMM 4D (Bank 4)
DIMM 4C (Bank 4)
DIMM 4B (Bank 4)
DIMM 4A (Bank 4)
DIMM 3D (Bank 3)
DIMM 3C (Bank 3)
DIMM 3B (Bank 3)
DIMM 3A (Bank 3)
DIMM 2D (Bank 2)
DIMM 2C (Bank 2)
DIMM 2B (Bank 2)
DIMM 2A (Bank 2)
DIMM 1D (Bank 1)
DIMM 1C (Bank 1)
DIMM 1B (Bank 1)
DIMM 1A (Bank 1)
2
2
JI
C2
JI
C1
JPA1
JPA3
JPA2
SCSI
CTRLR
SO 100MHz ZCR1
North Bridge
DA2
WOR
WOL
SXB-
Buzzer
PCI-Ex8
SMB
J4E3
JPWF
SXB-
SMBus
PWR
PCI-Ex8
USB4
JAR1
South
Bridge
PWR Fail
USB2/3
ATX Main
PWR
CPU1
CPU2
JPL1
JPL2
SATA1
SATA0
JBT1
4-pin
PWR
S/IO
SATA3
SATA2
Speaker Connector
Pin Setting Defi nition
Pins 6-7 Internal Speaker
Pins 4-7 External Speaker
8-pin
PWR
FP Control
UIDSwitch
JUID1
JOH1
JP1
Fan1
Fan2
SPKPW LED
B
Fan3
Fan4
JWF1
Fan5
JCF1
IDE1
Compact Flash
Floppy
J7
BIOS
SATA5
SATA4
Channel A
JWD
JL1
U320 LVD/SE
JA1
DA1
A. GLAN1/2
B. PWR LED/Speaker
2-19
Page 38
X7DBR-8+/X7DBR-i+ User's Manual
Power Fault (PWR Supply
Failure)
Connect a cable from your power
supply to the Power Failure header
(JPWF) to provide warnings of power
supply failure. This warning signal is
passed through the PWR_LED pin
to indicate of a power failure on the
chassis. See the table on the right
for pin defi nitions.
Alarm Reset
PWR Supply Fail LED
Pin Defi nitions
Pin# Defi nition
1 PWR 1: Fail
2 PWR 2: Fail
3 PWR 3: Fail
4 Signal: Alarm Reset
Note: This feature is only available when using
Supermicro redundant power supplies.
If three power supplies are installed
and Alarm Reset (JAR1) is enabled,
the system will notify you when any
of the three power modules fails.
Connect JAR1 to a micro-switch to
enable you to turn off the alarm that
is activated when a power module
fails. See the table on the right for
pin defi nitions.
UID-
Switch
KB
MS
USB0/1
COM1
Bank4
Bank3
Bank2
Bank1
UPER X7DBR-8/i+
S
Slot7
GLAN1
Slot6
JPG1
GLAN2
GLAN
CTRLR
VGA
VGA
CTRLR
LVD/SE
U320
SCSI Chann. B
SIMSO
JCOM2
®
SE8C
JPCIE3
PCI-X 133MHz
Battery
PXH-V
DIMM 4D (Bank 4)
DIMM 4C (Bank 4)
DIMM 4B (Bank 4)
DIMM 4A (Bank 4)
DIMM 3D (Bank 3)
DIMM 3C (Bank 3)
DIMM 3B (Bank 3)
DIMM 3A (Bank 3)
DIMM 2D (Bank 2)
DIMM 2C (Bank 2)
DIMM 2B (Bank 2)
DIMM 2A (Bank 2)
DIMM 1D (Bank 1)
DIMM 1C (Bank 1)
DIMM 1B (Bank 1)
DIMM 1A (Bank 1)
2
2
JI
C2
JI
C1
JPA1
JPA3
JPA2
SCSI
CTRLR
SO 100MHz ZCR1
North Bridge
DA2
WOR
WOL
SXB-
Buzzer
PCI-Ex8
SMB
J4E3
A
JPWF
B
SXB-
SMBus
PWR
JAR1
PCI-Ex8
South
Bridge
USB4
PWR Fail
USB2/3
CPU1
CPU2
ATX Main
PWR
SATA1
SATA0
JPL2
JPL1
JBT1
4-pin
PWR
S/IO
SATA3
SATA2
J7
Pin Setting Defi nition
Pin 1 Ground
Pin 2 +5V
8-pin
PWR
FP Control
UIDSwitch
JUID1
JOH1
JP1
Fan1
Fan2
SPKPW LED
Fan3
Fan4
JWF1
Fan5
JCF1
IDE1
Compact Flash
Floppy
U320 LVD/SE
Channel A
BIOS
JA1
SATA5
JW
D
DA1
SATA4
JL1
Alarm Reset
A. Power Fault
B. Alarm Reset
2-20
Page 39
Chapter 2: Installation
Overheat LED/Fan Fail
(JOH1)
The JOH1 header is used to connect
an LED to provide warnings of chas-
sis overheating. This LED will blink
to indicate a fan failure. Refer to the
table on right for pin defi nitions.
SMB
A System Management Bus header
is located at J18. Connect the ap-
propriate cable here to utilize SMB on
your system.
Overheat LED
Pin Defi nitions
Pin# Defi nition
1 5vDC
2 OH Active
OH/Fan Fail LED
State Message
Solid Overheat
Blinking Fan Fail
SMB Header
Pin Defi nitions
Pin# Defi nition
1 Data
2 Ground
3Clock
4 No Connection
KB
MS
USB0/1
COM1
GLAN1
GLAN2
SCSI Chann. B
UID-
Switch
Bank4
Bank3
Bank2
Bank1
UPER X7DBR-8/i+
S
Slot7
SE8C
JPCIE3
Slot6
PCI-X 133MHz
JPG1
Battery
GLAN
CTRLR
VGA
PXH-V
SIMSO
LVD/SE
U320
JCOM2
VGA
CTRLR
DIMM 4D (Bank 4)
DIMM 4C (Bank 4)
DIMM 4B (Bank 4)
DIMM 4A (Bank 4)
DIMM 3D (Bank 3)
DIMM 3C (Bank 3)
DIMM 3B (Bank 3)
DIMM 3A (Bank 3)
DIMM 2D (Bank 2)
DIMM 2C (Bank 2)
DIMM 2B (Bank 2)
DIMM 2A (Bank 2)
DIMM 1D (Bank 1)
DIMM 1C (Bank 1)
DIMM 1B (Bank 1)
DIMM 1A (Bank 1)
®
2
JI
C1
JPA3
JPA2
SO 100MHz ZCR1
JI
JPA1
2
C2
SCSI
CTRLR
North Bridge
DA2
WOR
WOL
SXB-
Buzzer
PCI-Ex8
SMB
J4E3
JPWF
SXB-
SMBus
PWR
JAR1
PCI-Ex8
South
Bridge
B
USB4
PWR Fail
USB2/3
ATX Main
PWR
CPU1
CPU2
JPL1
JPL2
SATA1
SATA0
JBT1
SATA2
4-pin
PWR
S/IO
SATA3
J7
8-pin
PWR
JWF1
JCF1
BIOS
SATA5
SATA4
FP Control
UID-
JUID1
JOH1
JP1
Flash
IDE1
Compact
Channel A
JWD
JL1
h
Switc
A
Fan1
Fan2
SPKPW LED
Fan3
Fan4
Fan5
Floppy
U320 LVD/SE
JA1
DA1
A. OH/Fan Fail LED
B. SMB Header
2-21
Page 40
X7DBR-8+/X7DBR-i+ User's Manual
Power SMB (I2 C) Connector
Power SMB (I2 C) Connector (J17)
monitors the status of PWR Supply,
Fan and system temperature. See the
table on the right for pin defi nitions.
VGA Connector
A VGA connector (J15) is located next
to the GLAN2 port on the IO backplane.
Refer to the board layout below for
the location.
PWR SMB
Pin Defi nitions
Pin# Defi nition
1Clock
2 Data
3 PWR Fail
4 Ground
5 +3.3V
KB
MS
USB0/1
COM1
GLAN1
GLAN2
SCSI Chann. B
UID-
Switch
Bank4
Bank3
Bank2
Bank1
UPER X7DBR-8/i+
S
Slot7
SE8C
JPCIE3
Slot6
PCI-X 133MHz
JPG1
Battery
GLAN
CTRLR
B
VGA
PXH-V
SIMSO
LVD/SE
U320
JCOM2
VGA
CTRLR
DIMM 4D (Bank 4)
DIMM 4C (Bank 4)
DIMM 4B (Bank 4)
DIMM 4A (Bank 4)
DIMM 3D (Bank 3)
DIMM 3C (Bank 3)
DIMM 3B (Bank 3)
DIMM 3A (Bank 3)
DIMM 2D (Bank 2)
DIMM 2C (Bank 2)
DIMM 2B (Bank 2)
DIMM 2A (Bank 2)
DIMM 1D (Bank 1)
DIMM 1C (Bank 1)
DIMM 1B (Bank 1)
DIMM 1A (Bank 1)
®
2
JI
JI
C1
JPA3
JPA2
SO 100MHz ZCR1
2
C2
JPA1
SCSI
CTRLR
North Bridge
DA2
WOR
WOL
SXB-
Buzzer
PCI-Ex8
SMB
J4E3
JPWF
SXB-
A
SMBus
PWR
PWR Fail
JAR1
PCI-Ex8
South
Bridge
USB4
USB2/3
ATX Main
PWR
CPU1
CPU2
JPL1
JPL2
SATA1
SATA0
JBT1
4-pin
PWR
S/IO
SATA3
SATA2
J7
8-pin
PWR
JWF1
JCF1
BIOS
SATA5
SATA4
FP Control
UIDSwitc
JUID1
JOH1
JP1
Fan2
Flash
IDE1
Compact
Channel A
JWD
JL1
A. PWR SMB
B. VGA
h
Fan1
SPKPW LED
Fan3
Fan4
Fan5
Floppy
U320 LVD/SE
JA1
DA1
2-22
Page 41
Chapter 2: Installation
Compact Flash Card PWR
Connector
A Compact Flash Card Power Connector is
located at JWFR. For the Compact Flash
Card or the Compact Flash Jumper (JCF1)
to work properly, you will need to connect
a power cable to JWFR fi rst. Refer to the
board layout below for the location.
Unit Identifi cation Switches
There are two Unit Identification (UID)
Switches on the motherboard. The Front
Panel UID Switch (JUID1) is connected to
the Front Control Panel. The Back Panel
(BP) UID Switch (JUID2) is located next to
DIMM#4D. When you push the UID Switch
(JUID1) on the Front Control Panel, both
BP UID and FP UID Indicators will be lit.
Push the UID Switch again to turn off both
Indicators. These UID Indicators provide
easy identifi cation of a system unit that may
be in need of service.
Compact Flash Card PWR
Connector
Jumper Defi nition
On Power On
Off Power Off
KB
MS
USB0/1
COM1
GLAN1
GLAN2
SCSI Chann. B
C
UID-
Switch
Bank4
Bank3
Bank2
Bank1
UPER X7DBR-8/i+
S
Slot7
SE8C
JPCIE3
Slot6
PCI-X 133MHz
JPG1
Battery
GLAN
CTRLR
VGA
PXH-V
SIMSO
LVD/SE
U320
JCOM2
VGA
CTRLR
DIMM 4D (Bank 4)
DIMM 4C (Bank 4)
DIMM 4B (Bank 4)
DIMM 4A (Bank 4)
DIMM 3D (Bank 3)
DIMM 3C (Bank 3)
DIMM 3B (Bank 3)
DIMM 3A (Bank 3)
DIMM 2D (Bank 2)
DIMM 2C (Bank 2)
DIMM 2B (Bank 2)
DIMM 2A (Bank 2)
DIMM 1D (Bank 1)
DIMM 1C (Bank 1)
DIMM 1B (Bank 1)
DIMM 1A (Bank 1)
®
2
JI
C1
JPA3
JPA2
SO 100MHz ZCR1
JI
JPA1
2
C2
SCSI
CTRLR
North Bridge
DA2
WOR
WOL
SXB-
Buzzer
PCI-Ex8
SMB
J4E3
JPWF
SXB-
SMBus
PWR
JAR1
PCI-Ex8
South
Bridge
USB4
PWR Fail
USB2/3
ATX Main
PWR
CPU1
CPU2
JPL1
JPL2
SATA1
SATA0
JBT1
SATA3
SATA2
4-pin
8-pin
PWR
PWR
FP Control
Connector
B. Front Panel UID
A. Compact Flash PWR
UID-
h
Switc
B
JUID1
JOH1
JP1
Fan1
Switch (JUID1)
C. Back Panel UID
Switch (JUID2)
Fan2
SPKPW LED
Fan3
Fan4
A
JWF1
Fan5
JCF1
Flash
IDE1
Compact
Floppy
J7
S/IO
BIOS
SATA5
SATA4
JWD
JL1
U320 LVD/SE
Channel A
JA1
DA1
2-23
Page 42
X7DBR-8+/X7DBR-i+ User's Manual
2-6 Jumper Settings
Explanation of
Jumpers
To modify the operation of the
motherboard, jumpers can be used
to choose between optional settings.
Jumpers create shorts between two
pins to change the function of the
connector. Pin 1 is identifi ed with a
square solder pad on the printed circuit
board. See the motherboard layout
pages for jumper locations.
Note: On two pin jumpers, "Closed"
means the jumper is on and "Open"
means the jumper is off the pins.
Connector
Pins
Jumper
Cap
Setting
3 2 1
3 2 1
Pin 1-2 short
GLAN Enable/Disable
JPL1/JPL2 enable or disable the
GLAN Port1/GLAN Port2 on the
motherboard. See the table on the
right for jumper settings. The default
setting is enabled.
SE8C
JPCIE3
PCI-X 133MHz
Battery
B
PXH-V
DIMM 4D (Bank 4)
DIMM 4C (Bank 4)
DIMM 4B (Bank 4)
DIMM 4A (Bank 4)
DIMM 3D (Bank 3)
DIMM 3C (Bank 3)
DIMM 3B (Bank 3)
DIMM 3A (Bank 3)
DIMM 2D (Bank 2)
DIMM 2C (Bank 2)
DIMM 2B (Bank 2)
DIMM 2A (Bank 2)
DIMM 1D (Bank 1)
DIMM 1C (Bank 1)
DIMM 1B (Bank 1)
DIMM 1A (Bank 1)
®
2
JI
JI
C1
JPA3
JPA2
SO 100MHz ZCR1
2
C2
JPA1
SCSI
CTRLR
North Bridge
DA2
WOR
WOL
SXB-
Buzzer
PCI-Ex8
SMB
J4E3
JPWF
SXB-
PCI-Ex8
KB
MS
USB0/1
COM1
GLAN1
GLAN2
SCSI Chann. B
UID-
Switch
Bank4
Bank3
Bank2
Bank1
UPER X7DBR-8/i+
S
Slot7
Slot6
JPG1
GLAN
CTRLR
A
VGA
VGA
CTRLR
LVD/SE
U320
SIMSO
JCOM2
SMBus
PWR
JAR1
South
Bridge
USB4
PWR Fail
USB2/3
ATX Main
PWR
CPU1
CPU2
JPL1
JPL2
SATA1
SATA0
JBT1
4-pin
PWR
S/IO
SATA3
SATA2
GLAN Enable
Pin# Defi nition
1-2 Enabled (*default)
2-3 Disabled
8-pin
PWR
FP Control
UID-
h
Switc
JUID1
JOH1
JP1
Fan1
Fan2
SPKPW LED
Fan3
Fan4
JWF1
Fan5
JCF1
Flash
IDE1
Compact
Floppy
J7
BIOS
SATA5
SATA4
JWD
JL1
U320 LVD/SE
Channel A
JA1
DA1
A. GLAN Port1 Enable
B. GLAN Port2 Enable
2-24
Page 43
Chapter 2: Installation
CMOS Clear
JBT1 is used to clear CMOS. Instead of pins, this "jumper" consists of contact
pads to prevent the accidental clearing of CMOS. To clear CMOS, use a metal
object such as a small screwdriver to touch both pads at the same time to short
the connection. Always remove the AC power cord from the system before clear-
ing CMOS. Note: For an ATX power supply, you must completely shut down the
system, remove the AC power cord and then short JBT1 to clear CMOS.
Watch Dog Enable/Disable
JWD controls the Watch Dog function. Watch
Dog is a system monitor that can reboot the sys-
tem when a software application hangs. Pins
1-2 will cause WD to reset the system if an ap-
plication hangs. Pins 2-3 will generate a non-
maskable interrupt signal for the application that
hangs. See the table on the right for jumper
settings. Watch Dog must also be enabled in
BIOS.
4-pin
UID-
Switch
KB
MS
USB0/1
COM1
GLAN1
GLAN2
VGA
LVD/SE
U320
SCSI Chann. B
JCOM2
VGA
CTRL
S
JPG1
GLAN
CTRLR
R
Bank4
Bank3
Bank2
Bank1
UPER
Slot7
SE8C
JPCIE3
Slot6
PCI-X 133MHz
PXH-V
SIMSO
DIMM 4D (Bank 4)
DIMM 4C (Bank 4)
DIMM 4B (Bank 4)
DIMM 4A (Bank 4)
DIMM 3D (Bank 3)
DIMM 3C (Bank 3)
DIMM 3B (Bank 3)
DIMM 3A (Bank 3)
DIMM 2D (Bank 2)
DIMM 2C (Bank 2)
DIMM 2B (Bank 2)
DIMM 2A (Bank 2)
DIMM 1D (Bank 1)
DIMM 1C (Bank 1)
DIMM 1B (Bank 1)
DIMM 1A (Bank 1)
®
X7DBR-8
JI
Battery
2
JI
C1
JPA3
JPA2
SO 100M
2
C2
JPA1
SCSI
CTRLR
Hz
/i+
ZCR1
North Bridge
DA2
WOR
WOL
SXB-
Buzzer
PCI-Ex8
SM
J4E3
JPWF
SXB-
B
SMBus
PWR
JAR1
PCI-Ex8
A
South
Bridge
USB4
PWR Fail
USB2/3
ATX Main
PW
CPU1
CPU2
R
SATA1
SATA0
JPL2
JPL1
JBT1
PWR
S/IO
SATA3
SATA2
J7
8-pin
PWR
JWF1
JCF1
B
BIOS
SATA5
SATA4
Watch Dog
Jumper Settings (JWD)
Jumper Setting Defi nition
Pins 1-2 Reset
Pins 2-3 NMI
Open Disabled
A. Clear CMOS
B. Watch Dog Enable
FP Control
UIDSwitch
JUID1
JOH1
JP1
Fan1
Fan2
SPKPW LED
Fan3
Fan4
Fan5
IDE1
Compact Flash
Floppy
U320 LVD/SE
Channel A
JA1
JWD
DA1
JL1
(*default)
2-25
Page 44
X7DBR-8+/X7DBR-i+ User's Manual
SCSI Controller Enable/
Disable
Jumper JPA1 is used to enable or dis-
able the Adaptec SCSI controller. The
default setting is on pins 1-2 to enable
SCSI. See the table on the right for
jumper settings.
SCSI Termination Enable/
Disable
Jumpers JPA2/JPA3 are used to enable
or disable termination for SCSI Channel
A (JPA2) and Channel B (JPA3) con-
nectors. The default setting is open to
enable termination. See the table on the
right for jumper settings.
SCSI Enable/Disable
Jumper Settings
Jumper Setting Defi nition
*Pins 1-2 (Default) Enabled
Pins 2-3 Disabled
SCSI Term. Enable/Disable
Jumper Settings
Jumper Setting Defi nition
*Open (default) Enabled
Closed Disabled
*Note: In order for the SCSI drives to
function properly, please do not change
the default setting (enabled) set by the
manufacturer.
UID-
Switch
KB
MS
USB0/1
COM1
GLAN1
GLAN2
VGA
LVD/SE
U320
SCSI Chann. B
JCOM2
S
JPG1
GLAN
CTRLR
VGA
R
CTRL
Bank4
Bank3
Bank2
Bank1
UPER
Slot7
SE8C
Slot6
PCI-X 133MHz
PXH-V
SIMSO
DIMM 4D (Bank 4)
DIMM 4C (Bank 4)
DIMM 4B (Bank 4)
DIMM 4A (Bank 4)
DIMM 3D (Bank 3)
DIMM 3C (Bank 3)
DIMM 3B (Bank 3)
DIMM 3A (Bank 3)
DIMM 2D (Bank 2)
DIMM 2C (Bank 2)
DIMM 2B (Bank 2)
DIMM 2A (Bank 2)
DIMM 1D (Bank 1)
DIMM 1C (Bank 1)
DIMM 1B (Bank 1)
DIMM 1A (Bank 1)
®
X7DBR-8
JPCIE3
Battery
C
2
JI
C1
JPA3
B
SO 100M
JPA2
JI
/i+
2
C2
JPA1
SCSI
CTRLR
Hz
A
ZCR1
North Bridge
DA2
WOR
WOL
SXB-
Buzzer
PCI-Ex8
SM
J4E3
SMBus
PWR
JPWF
PWR Fail
JAR1
SXB-
PCI-Ex8
South
Bridge
B
USB4
USB2/3
ATX Main
PW
CPU1
CPU2
R
SATA1
SATA0
JPL2
JPL1
JBT1
4-pin
PWR
S/IO
SATA3
SATA2
J7
8-pin
PWR
JWF1
JCF1
BIOS
SATA5
SATA4
FP Control
UIDSwitch
JUID1
JOH1
JP1
Fan1
Fan2
Fan3
Fan4
Fan5
IDE1
Compact Flash
U320 LVD/SE
Channel A
JA1
JWD
DA1
JL1
A. SCSI Enable
B. SCSI Channel A Termi-
nation Enable
C. SCSI Channel B Termi-
nation Enable
SPKPW LED
Floppy
2-26
Page 45
Chapter 2: Installation
3rd PWR Supply PWR Fault
Detect (J3P)
The system can notify you in the event
of a power supply failure. This feature
available when three power supply units
are installed in the chassis with one act-
ing as a backup. If you only have one
or two power supply units installed, you
should disable this (the default setting)
with J3P to prevent false alarms.
VGA Enable/Disable
JPG1 allows you to enable or disable the
VGA port. The default position is on pins
1 and 2 to enable VGA. See the table
on the right for jumper settings.
3rd PWR Supply PWR Fault
Jumper Settings
Jumper Setting Defi nition
Closed Enabled
Open Disabled (*Default)
VGA Enable/Disable
Jumper Settings
Both Jumpers Defi nition
*Pins 1-2 Enabled
Pins 2-3 Disabled
UID-
Switch
KB
MS
USB0/1
COM1
GLAN1
GLAN2
VGA
LVD/SE
U320
SCSI Chann. B
JCOM2
VGA
CTRL
S
JPG1
GLAN
CTRLR
R
Bank4
Bank3
Bank2
Bank1
UPER
Slot7
SE8C
JPCIE3
Slot6
PCI-X 133MHz
B
PXH-V
SIMSO
DIMM 4D (Bank 4)
DIMM 4C (Bank 4)
DIMM 4B (Bank 4)
DIMM 4A (Bank 4)
DIMM 3D (Bank 3)
DIMM 3C (Bank 3)
DIMM 3B (Bank 3)
DIMM 3A (Bank 3)
DIMM 2D (Bank 2)
DIMM 2C (Bank 2)
DIMM 2B (Bank 2)
DIMM 2A (Bank 2)
DIMM 1D (Bank 1)
DIMM 1C (Bank 1)
DIMM 1B (Bank 1)
DIMM 1A (Bank 1)
®
X7DBR-8
JI
Battery
2
JI
C1
JPA3
JPA2
SO 100M
2
C2
JPA1
SCSI
CTRLR
Hz
/i+
ZCR1
North Bridge
DA2
WOR
WOL
SXB-
Buzzer
PCI-Ex8
SM
J4E3
A. 3rd PWR Fail
4-pin
JPL2
JPL1
JBT1
PWR
S/IO
SATA3
SATA2
J7
8-pin
PWR
JWF1
JCF1
BIOS
SATA5
SATA4
FP Control
UIDSwitch
JUID1
JOH1
JP1
Fan1
Fan2
Fan3
Fan4
Fan5
IDE1
Compact Flash
U320 LVD/SE
Channel A
JA1
JWD
JL1
SPKPW LED
Floppy
DA1
ATX Main
A
PWR Fail
USB2/3
CPU1
CPU2
R
PW
SATA1
SATA0
SMBus
PWR
JPWF
JAR1
SXB-
PCI-Ex8
South
Bridge
B
USB4
B. VGA Enabled
2-27
Page 46
X7DBR-8+/X7DBR-i+ User's Manual
I2C Bus to PCI Slots 1/2
JI2C1/JI2C2 allow you to enable I2C
Bus to PCI-X/PCI-E slots. See the table
on the right for jumper settings. The
default setting is Disabled.
Compact Flash Master/Slave
Select
A Compact Flash Master (Primary)/Slave
(Secondary) Select Jumper is located
at JCF1. Close this jumper to enable
Compact Flash Card. For the Compact
Flash Card or the Compact Flash Jumper
(JCF1) to work properly, you will need to
connect the Compact Flash Card power
cable to JWF1 fi rst. Refer to the board
layout below for the location.
I2C Bus to PCI Slots
Jumper Settings
Jumper Defi nition
1-2 Enabled
Off Disabled (De-
fault)
Compact Flash Card Master/
Slave Select
Jumper Defi nition
Open Slave (Secondary)
Closed Master (Primary)
UID-
Switch
KB
MS
USB0/1
COM1
GLAN1
GLAN2
VGA
LVD/SE
U320
SCSI Chann. B
JCOM2
DIMM 4D (Bank 4)
DIMM 4C (Bank 4)
SE8C
SIMSO
DIMM 4B (Bank 4)
DIMM 4A (Bank 4)
DIMM 3D (Bank 3)
DIMM 3C (Bank 3)
DIMM 3B (Bank 3)
DIMM 3A (Bank 3)
DIMM 2D (Bank 2)
DIMM 2C (Bank 2)
DIMM 2B (Bank 2)
DIMM 2A (Bank 2)
DIMM 1D (Bank 1)
DIMM 1C (Bank 1)
DIMM 1B (Bank 1)
DIMM 1A (Bank 1)
®
JPCIE3
PCI-X 133MHz
Battery
PXH-V
A
JI
Bank4
Bank3
Bank2
Bank1
UPER X7DBR-8/i+
S
Slot7
Slot6
JPG1
GLAN
CTRLR
VGA
CTRLR
B
2
2
JI
C2
C1
JPA1
JPA3
JPA2
SCSI
CTRLR
SO 100MHz ZCR1
North Bridge
DA2
WOR
WOL
SXB-
Buzzer
PCI-Ex8
SMB
J4E3
JPWF
SXB-
SMBus
PWR
PWR Fail
JAR1
PCI-Ex8
South
Bridge
USB4
USB2/3
ATX Main
PWR
CPU1
CPU2
JPL1
JPL2
SATA1
SATA0
JBT1
4-pin
PWR
S/IO
SATA3
SATA2
J7
8-pin
PWR
JWF1
JCF1
C
BIOS
SATA5
SATA4
FP Control
UIDSwitch
JUID1
JOH1
JP1
IDE1
Compact Flash
Channel A
JWD
JL1
A. JI2C1
B. JI2C2
C. Compact Flash Master/
Slave Select
Fan1
Fan2
SPKPW LED
Fan3
Fan4
Fan5
Floppy
U320 LVD/SE
JA1
DA1
2-28
Page 47
Chapter 2: Installation
2-7 Onboard Indicators
GLAN LEDs
There are two GLAN ports on the moth-
erboard. Each Gigabit Ethernet LAN port
has two LEDs. The green LED indicates
activity, while the other LED may be
green, amber or off to indicate the speed
of the connection. See the tables at right
for more information.
Activity
LED
Link
LED
GLAN Activity Indicator
LED Color Defi nition
Off No Activity or 10 Mbps
Blinking Active
GLAN Link (Speed) Indicator
LED Color Defi nition
Off No Connection or 10 Mbps
Green 100 Mbps
Amber 1 Gbps
UID-
Switch
KB
MS
USB0/1
COM1
A
GLAN1
GLAN2
B
VGA
LVD/SE
U320
SCSI Chann. B
JCOM2
DIMM 4D (Bank 4)
DIMM 4C (Bank 4)
SE8C
PCI-X 133MHz
SIMSO
DIMM 4B (Bank 4)
DIMM 4A (Bank 4)
DIMM 3D (Bank 3)
DIMM 3C (Bank 3)
DIMM 3B (Bank 3)
DIMM 3A (Bank 3)
DIMM 2D (Bank 2)
DIMM 2C (Bank 2)
DIMM 2B (Bank 2)
DIMM 2A (Bank 2)
DIMM 1D (Bank 1)
DIMM 1C (Bank 1)
DIMM 1B (Bank 1)
DIMM 1A (Bank 1)
®
JPCIE3
Battery
PXH-V
Bank4
Bank3
Bank2
Bank1
UPER X7DBR-8/i+
S
Slot7
Slot6
JPG1
GLAN
CTRLR
VGA
CTRLR
2
JI
C1
JPA3
SO 100MH
JPA2
JI
JPA1
2
C2
SCSI
CTRLR
z ZCR1
North Bridge
DA2
WOR
WOL
SXB-
Buzzer
PCI-Ex8
SMB
J4E3
JPWF
SXB-
SMBus
PWR
JAR1
PCI-Ex8
South
Bridge
USB4
PWR Fail
USB2/3
ATX Main
PWR
CPU1
CPU2
JPL1
JPL2
SATA1
SATA0
JBT1
SATA3
SATA2
4-pin
8-pin
PWR
PWR
FP Control
UIDSwitch
JUID1
JOH1
JP1
Fan1
Fan2
SPKPW LED
Fan3
Fan4
JWF1
Fan5
JCF1
IDE1
Compact Flash
Floppy
J7
S/IO
BIOS
SATA5
SATA4
JWD
JL1
U320 LVD/SE
Channel A
JA1
DA1
A. GLAN Port1 LEDs
B. GLAN Port2 LEDs
2-29
Page 48
X7DBR-8+/X7DBR-i+ User's Manual
Onboard SCSI Activity LED
Indicators (*X7DBR-8+ only)
There are two Onboard SCSI Activity LED
indicators on the X7DBR-8+. DA1 indicates
the activity status of SCSI Channel A and
DA2 indicates the activity status of Chan-
nel B.
UID-
Switch
KB
MS
USB0/1
COM1
GLAN1
GLAN2
VGA
LVD/SE
U320
SCSI Chann. B
JCOM2
DIMM 4D (Bank 4)
DIMM 4C (Bank 4)
Bank4
Bank3
Bank2
Bank1
DIMM 4B (Bank 4)
DIMM 4A (Bank 4)
DIMM 3D (Bank 3)
DIMM 3C (Bank 3)
DIMM 3B (Bank 3)
DIMM 3A (Bank 3)
DIMM 2D (Bank 2)
DIMM 2C (Bank 2)
DIMM 2B (Bank 2)
DIMM 2A (Bank 2)
DIMM 1D (Bank 1)
DIMM 1C (Bank 1)
DIMM 1B (Bank 1)
DIMM 1A (Bank 1)
®
UPER X7DBR-8/i+
S
VGA
CTRLR
Slot6
JPG1
GLAN
CTRLR
Slot7
SIMSO
SE8C
PCI-X 133MHz
PXH-V
JPCIE3
Battery
JI
2
2
JI
C2
C1
JPA1
JPA3
JPA2
SCSI
CTRLR
SO 100MHz ZCR1
North Bridge
DA2
B
WOR
WOL
SXB-
Buzzer
PCI-Ex8
SMB
J4E3
JPWF
SXB-
SMBus
PWR
PWR Fail
JAR1
PCI-Ex8
South
Bridge
USB4
USB2/3
ATX Main
PWR
CPU1
CPU2
JPL1
JPL2
SATA1
SATA0
JBT1
4-pin
PWR
S/IO
SATA3
SATA2
J7
8-pin
PWR
JWF1
JCF1
BIOS
SATA5
SATA4
FP Control
UIDSwitch
JUID1
JOH1
JP1
IDE1
Compact Flash
Channel A
JWD
JL1
Fan1
Fan2
SPKPW LED
Fan3
Fan4
Fan5
Floppy
U320 LVD/SE
JA1
A
DA1
A. SCSI Channel A Activ-
ity LED
B. SCSI Channel B Activ-
ity LED
2-30
Page 49
Chapter 2: Installation
2-8 Floppy Drive, Hard Disk Drive, SIMSO-DIMM IPMI,
Zero Channel RAID Card and SCSI Connections
Note the following when connecting the fl oppy and hard disk drive cables:
• The fl oppy disk drive cable has seven twisted wires.
• A red mark on a wire typically designates the location of pin 1.
• A single fl oppy disk drive ribbon cable has two connectors to provide for two
fl oppy disk drives. The connector with twisted wires always connects to drive
A, and the connector that does not have twisted wires always connects to drive
B.
Floppy Connector
The fl oppy connector is located at
J22. See the table below for pin
defi nitions.
Floppy Drive Connector
Pin Defi nitions (Floppy)
Pin# Defi nition Pin # Defi nition
1 Ground 2 FDHDIN
3 Ground 4 Reserved
5 Key 6 FDEDIN
7 Ground 8 Index
9 Ground 10 Motor Enable
11 Ground 12 Drive Select B
13 Ground 14 Drive Select B
15 Ground 16 Motor Enable
17 Ground 18 DIR
19 Ground 20 STEP
21 Ground 22 Write Data
23 Ground 24 Write Gate
25 Ground 26 Track 00
27 Ground 28 Write Protect
29 Ground 30 Read Data
31 Ground 32 Side 1 Select
33 Ground 34 Diskette
®
UPER X7DBR-8/i+
S
A. Floppy Port
A
JA1
2-31
Page 50
X7DBR-8+/X7DBR-i+ User's Manual
SIMSO Slot
There is a SIM SO-DIMM IPMI
Slot on the motherboard. Refer
to the layout below for the
location of SIMSO slot.
Zero Channel RAID
Card Slot
There is a Zero Channel RAID
Card Slot on the motherboard.
Refer to the layout below for
the location of the ZCR card
socket.
Bank4
Bank3
Bank2
Bank1
UPER
Slot7
SE8C
JPCIE3
Slot6
PCI-X 133MHz
Battery
PXH-V
A
SIMSO
DIMM 4D (Bank 4)
DIMM 4C (Bank 4)
DIMM 4B (Bank 4)
DIMM 4A (Bank 4)
DIMM 3D (Bank 3)
DIMM 3C (Bank 3)
DIMM 3B (Bank 3)
DIMM 3A (Bank 3)
DIMM 2D (Bank 2)
DIMM 2C (Bank 2)
DIMM 2B (Bank 2)
DIMM 2A (Bank 2)
DIMM 1D (Bank 1)
DIMM 1C (Bank 1)
DIMM 1B (Bank 1)
DIMM 1A (Bank 1)
®
X7DBR-8/i+
2
JI
C1
JPA3
JPA2
SO 100MHz ZCR1
JI
2
C2
JPA1
SCSI
CTRLR
B
North Bridge
DA2
WOR
JPWF
SXB-
PCI-Ex8
Buzzer
SMB
J4E3
WOL
UID-
Switch
KB
MS
USB0/1
COM1
GLAN1
GLAN2
VGA
LVD/SE
U320
SCSI Chann. B
JCOM2
VGA
CTRLR
S
JPG1
GLAN
CTRLR
SXB-
SMBus
PWR
JAR1
PCI-Ex8
South
Bridge
USB4
PWR Fail
USB2/3
ATX Main
PWR
CPU1
CPU2
JPL2
SATA1
SATA0
4-pin
8-pin
PWR
PWR
FP Control
UIDSwitch
JUID1
JOH1
JP1
Fan1
Fan2
SPKPW LED
Fan3
Fan4
JWF1
Fan5
JCF1
pact Flash
IDE1
Com
Floppy
JBT1
J7
JPL1
S/IO
SATA3
SATA2
BIOS
SATA5
SATA4
JWD
JL1
U320 LVD/SE
Channel A
JA1
DA1
A. SIMSO Slot
B. SOZCR1 Socket
2-32
Page 51
Chapter 2: Installation
IDE Connectors
There are two IDE Connectors (JIDE1:
Blue, JIDE2: White) on the mother-
board. The blue IDE connector (JIDE1)
is designated as the Primary IDE Drive.
The white IDE connector (JIDE2) is des-
ignated as the Secondary IDE Drive,
reserved for Compact Flash Card use
only. (See the note below.) See the
table on the right for pin defi nitions.
*Note: JIDE2 (the white slot) is reserved
for Compact Flash Card only. Do not
use it for other devices. If JIDE2 is
populated with a Compact Flash Card,
JIDE1 (the blue slot) will be available for
one device only. For the Compact Flash
Card to work properly, you will need to
connect a power cable to JWF1 fi rst.
IDE Drive Connectors
Pin Defi nitions
Pin# Defi nition Pin # Defi nition
1 Reset IDE 2 Ground
3 Host Data 7 4 Host Data 8
5 Host Data 6 6 Host Data 9
7 Host Data 5 8 Host Data 10
9 Host Data 4 10 Host Data 11
11 Host Data 3 12 Host Data 12
13 Host Data 2 14 Host Data 13
15 Host Data 1 16 Host Data 14
17 Host Data 0 18 Host Data 15
19 Ground 20 Key
21 DRQ3 22 Ground
23 I/O Write 24 Ground
25 I/O Read 26 Ground
27 IOCHRDY 28 BALE
29 DACK3 30 Ground
31 IRQ14 32 IOCS16
33 Addr1 34 Ground
35 Addr0 36 Addr2
37 Chip Select 0 38 Chip Select 1
39 Activity 40 Ground
UID-
Switch
KB
MS
USB0/1
COM1
GLAN1
GLAN2
VGA
LVD/SE
U320
SCSI Chann. B
JCOM2
DIMM 4D (Bank 4)
DIMM 4C (Bank 4)
®
SE8C
JPCIE3
PCI-X 133MHz
Battery
PXH-V
DIMM 4B (Bank 4)
DIMM 4A (Bank 4)
DIMM 3D (Bank 3)
DIMM 3C (Bank 3)
DIMM 3B (Bank 3)
DIMM 3A (Bank 3)
DIMM 2D (Bank 2)
DIMM 2C (Bank 2)
DIMM 2B (Bank 2)
DIMM 2A (Bank 2)
DIMM 1D (Bank 1)
DIMM 1C (Bank 1)
DIMM 1B (Bank 1)
DIMM 1A (Bank 1)
Bank4
Bank3
Bank2
Bank1
UPER X7DBR-8/i+
S
Slot7
Slot6
JPG1
GLAN
CTRLR
VGA
CTRLR
SIMSO
2
2
JI
C2
JI
C1
JPA1
JPA3
JPA2
SCSI
CTRLR
SO 100MHz ZCR1
North Bridge
DA2
WOR
WOL
SXB-
Buzzer
PCI-Ex8
SMB
J4E3
JPWF
SXB-
SMBus
PWR
PWR Fail
JAR1
PCI-Ex8
South
Bridge
USB4
USB2
ATX Main
PWR
CPU1
CPU2
/3
JPL1
JPL2
SATA1
SATA0
JBT1
SATA3
SATA2
4-pin
8-pin
PWR
PWR
FP Control
UIDSwitch
JUID1
JOH1
JP1
Fan1
A. IDE#1
B. Compact Flash Card
Fan2
SPKPW LED
Fan3
Fan4
A
B
JWF1
BIOS
Fan5
IDE1
Compact Flash
U320 LVD/SE
Channel A
JA1
JWD
DA1
JL1
Floppy
JCF1
J7
S/IO
SATA5
SATA4
2-33
Page 52
X7DBR-8+/X7DBR-i+ User's Manual
Ultra320 SCSI Drive Connector
Ultra 320 SCSI
Connectors (*X7DBR8+ only)
There are two SCSI
connectors on the
motherboard. SCSI
Channel A is located at
JA1, and SCSI Channel B
is located at JA2. Refer
to the table below for the
pin defi nitions of the Ultra
320 SCSI connectors
located at JA1 and JA2.
A. SCSI Channel A
B. SCSI Channel B
Pin# Defi nition Pin # Defi nition
1 +DB (12) 35 -DB (12)
2 +DB (13) 36 -DB (13)
3 +DB (14) 37 -DB (14)
4 +DB (15) 38 -DB (15)
5 +DB (P1) 39 -DB (P1)
6 +DB (0) 40 -DB (0)
7 +DB (1) 41 -DB (1)
8 +DB (2) 42 -DB (2)
9 +DB (3) 43 -DB (3)
10 +DB (4) 44 -DB (4)
11 +DB (5) 45 -DB (5)
12 +DB (6) 46 -DB (6)
13 +DB (7) 47 -DB (7)
14 +DB (P) 48 -DB (P)
15 Ground 49 Ground
16 DIFFSENS 50 Ground
17 TERMPWR 51 TERMPWR
18 TERMPWR 52 TERMPWR
19 Reserved 53 Reserved
20 Ground 54 Ground
21 +ATN 55 -ATN
22 Ground 56 Ground
23 +BSY 57 -BSY
24 +ACK 58 -ACK
25 +RST 59 -RST
26 +MSG 60 -MSG
27 +SEL 61 -SEL
28 +C/D 62 -C/D
29 +REQ 63 -REQ
30 +I/O 64 -I/O
31 +DB (8) 65 -DB (8)
32 +DB (9) 66 -DB (9)
33 +DB (10) 67 -DB (10)
34 +DB (11) 68 -DB (11)
Pin Defi nitions (J28)
®
X7DBR-8/i+
UPER
S
B
A
1
JA
2-34
Page 53
Chapter 3: Troubleshooting
Chapter 3
Troubleshooting
3-1 Troubleshooting Procedures
Use the following procedures to troubleshoot your system. If you have followed all
of the procedures below and still need assistance, refer to the ‘Technical Support
Procedures’ and/or ‘Returning Merchandise for Service’ section(s) in this chapter.
Note: Always disconnect the power cord before adding, changing or installing
any hardware components.
Before Power On
1. Make sure that there are no short circuits between the motherboard and chas-
sis.
2. Disconnect all ribbon/wire cables from the motherboard, including those for the
keyboard and mouse.
3. Remove all add-on cards.
4. Install one CPU (making sure it is fully seated) and connect the chassis speaker
and the power LED to the motherboard. (Check all jumper settings as well.)
5. Use only the correct type of CMOS onboard battery as recommended by the
Manufacturer. Do not install the onboard battery upside down to avoid pos-
sible explosion.
No Power
1. Make sure that there are no short circuits between the motherboard and chas-
sis.
2. Verify that all jumpers are set to their default positions.
3. Check that the 115V/230V switch on the power supply is properly set.
4. Turn the power switch on and off to test the system.
5. The battery on your motherboard may be old. Check to verify that it still supplies
~3VDC. If it does not, replace it with a new one.
No Video
1. If the power is on but you have no video, remove all the add-on cards and
memory modules.
2. Use the speaker to determine if any beep codes exist. Refer to the Appendix
for details on beep codes.
Losing the System’s Setup Confi guration
1. Ensure that you are using a high quality power supply. A poor quality power
supply may cause the system to lose the CMOS setup information. Refer to
3-1
Page 54
X7DBR-8+/X7DBR-i+ User's Manual
Section 1-6 for details on recommended power supplies.
2. The battery on your motherboard may be old. Check to verify that it still supplies
~3VDC. If it does not, replace it with a new one.
3. If the above steps do not fi x the Setup Confi guration problem, contact your
vendor for repairs.
NOTE
If you are a system integrator, VAR or OEM, a POST diagnostics
card is recommended. For I/O port 80h codes, refer to App. B.
Memory Errors
1. Make sure the DIMM modules are properly and fully installed.
2. Determine if different speeds of DIMMs have been installed and verify that the
BIOS setup is confi gured for the fastest speed of RAM used. It is recom-
mended to use the same RAM speed for all DIMMs in the system.
3. Make sure you are using the correct type of DDR2 FBD (Fully Buffered) ECC
533/667 SDRAM (*recommended by the manufacturer.)
4. Check for bad DIMM modules or slots by swapping a single module between
four slots and noting the results.
5. Make sure all memory modules are fully seated in their slots. To install memory
modules, begin with Branch 1, then Branch 2, and so on (see Page 2-6).
3-2 Technical Support Procedures
Before contacting Technical Support, please take the following steps. Also, note
that as a motherboard manufacturer, Super Micro does not sell directly to end-us-
ers, so it is best to fi rst check with your distributor or reseller for troubleshooting
services. They should know of any possible problem(s) with the specifi c system
confi guration that was sold to you.
1. Please go through the ‘Troubleshooting Procedures’ and 'Frequently Asked
Question' (FAQ) sections in this chapter or see the FAQs on our web site
(
http://www.supermicro.com/support/faqs/) before contacting Techni-
cal Support.
2. BIOS upgrades can be downloaded from our web site at
(http://www.supermicro.com/support/bios/)
Note: Not all BIOS can be fl ashed depending on the modifi cations to the boot
block code.
3-2
Page 55
Chapter 3: Troubleshooting
3. If you still cannot resolve the problem, include the following information when
contacting Super Micro for technical support:
• Motherboard model and PCB revision number
• BIOS release date/version (this can be seen on the initial display when your
system fi rst boots up)
•System confi guration
An example of a Technical Support form is on our web site at
(http://www.supermicro.com/support/contact.cfm).
4. Distributors: For immediate assistance, please have your account number ready
when placing a call to our technical support department. We can be reached
by e-mail at support@supermicro.com or by fax at: (408) 503-8000, option
2.
3-3 Frequently Asked Questions
Question: What are the various types of memory that my motherboard can
support?
Answer: The X7DBR-8+/X7DBR-i+ has sixteen 240-pin DIMM slots that support
DDR2 FBD ECC 533/667 SDRAM modules. It is strongly recommended that you
do not mix memory modules of different speeds and sizes.
Question: How do I update my BIOS?
Answer: It is recommended that you do not upgrade your BIOS if you are expe-
riencing no problems with your system. Updated BIOS fi les are located on our
web site at
warning message and the info on how to update your BIOS on our web site. Also,
check the current BIOS revision and make sure it is newer than your BIOS before
downloading. Select your motherboard model and download the BIOS fi le to your
computer. Unzip the BIOS fi les onto a bootable fl oppy and reboot your system.
Follow the Readme.txt to continue fl ashing the BIOS.
(
prevent possible system boot failure!)
Question: What's on the CD that came with my motherboard?
http://www.supermicro.com/support/bios/. Please check our BIOS
*Warning: Do not shut down or reset the system while updating BIOS to
Answer: The supplied compact disc has quite a few drivers and programs that will
greatly enhance your system. We recommend that you review the CD and install the
applications you need. Applications on the CD include chipset drivers for Windows
and security and audio drivers.
3-3
Page 56
X7DBR-8+/X7DBR-i+ User's Manual
3-4 Returning Merchandise for Service
A receipt or copy of your invoice marked with the date of purchase is required be-
fore any warranty service will be rendered. You can obtain service by calling your
vendor for a Returned Merchandise Authorization (RMA) number. When returning
to the manufacturer, the RMA number should be prominently displayed on the
outside of the shipping carton, and mailed prepaid or hand-carried. Shipping and
handling charges will be applied for all orders that must be mailed when service
is complete.
This warranty only covers normal consumer use and does not cover damages in-
curred in shipping or from failure due to the alternation, misuse, abuse or improper
maintenance of products.
During the warranty period, contact your distributor fi rst for any product problems.
3-4
Page 57
Chapter 4: BIOS
Chapter 4
BIOS
4-1 Introduction
This chapter describes the Phoenix BIOS™ Setup utility for the X7DBR-8+/X7DBR-
i+. The Phoenix ROM BIOS is stored in a fl ash chip and can be easily upgraded
using a fl oppy disk-based program.
Note: Due to periodic changes to the BIOS, some settings may have been added or
deleted and might not yet be recorded in this manual. Please refer to the Manual
Download area of the Supermicro web site <http://www.supermicro.com> for any
changes to the BIOS that may not be refl ected in this manual.
System BIOS
The BIOS is the Basic Input Output System used in all IBM® PC, XT™, AT®, and
®
PS/2
compatible computers. The Phoenix BIOS stores the system parameters,
types of disk drives, video displays, etc. in the CMOS. The CMOS memory requires
very little electrical power. When the computer is turned off, a backup battery pro-
vides power to the CMOS Logic, enabling it to retain system parameters. Each time
the computer is powered on the computer is confi gured with the values stored in
the CMOS Logic by the system BIOS, which gains control at boot up.
How To Change the Confi guration Data
The CMOS information that determines the system parameters may be changed by
entering the BIOS Setup utility. This Setup utility can be accessed by pressing the
<Delete> key at the appropriate time during system boot. (See below.)
Starting the Setup Utility
Normally, the only visible POST (Power On Self Test) routine is the memory test. As
the memory is being tested, press the <Delete> key to enter the main menu of the
BIOS Setup utility. From the main menu, you can access the other setup screens,
such as the Security and Power menus. Beginning with Section 4-3, detailed de-
scriptions are given for each parameter setting in the Setup utility.
Warning: Do not shut down or reset the system while updating BIOS
to prevent possible boot failure.
4-1
Page 58
X7DBR-8+/X7DBR-i+ User's Manual
4-2 Running Setup
*Default settings are in bold text unless otherwise noted.
The BIOS setup options described in this section are selected by choosing
the appropriate text from the main BIOS Setup screen. All displayed text is
described in this section, although the screen display is often all you need to
understand how to set the options (see next page).
When you fi rst power on the computer, the Phoenix BIOS™ is immediately acti-
vated.
While the BIOS is in control, the Setup program can be activated in one of two
ways:
1. By pressing <Delete> immediately after turning the system on, or
2. When the message shown below appears briefl y at the bottom of the screen
during the POST (Power On Self-Test), press the <Delete> key to activate the
main Setup menu:
Press the <Delete> key to enter Setup
4-3 Main BIOS Setup
ʳ
All main Setup options are described in this section. The main BIOS Setup screen
is displayed below.
Use the Up/Down arrow keys to move among the different settings in each menu.
Use the Left/Right arrow keys to change the options for each setting.
Press the <Esc> key to exit the CMOS Setup Menu. The next section describes in
detail how to navigate through the menus.
Items that use submenus are indicated with the
press the <Enter> key to access the submenu.
icon. With the item highlighted,
4-2
Page 59
Main BIOS Setup Menu
Chapter 4: BIOS
Main Setup Features
System Time
To set the system date and time, key in the correct information in the appropriate
fi elds. Then press the <Enter> key to save the data.
System Date
Using the arrow keys, highlight the month, day and year fi elds, and enter the correct
data. Press the <Enter> key to save the data.
BIOS Date
This fi eld displays the date when this version of BIOS was built.
Legacy Diskette A
This setting allows the user to set the type of fl oppy disk drive installed as diskette A.
The options are Disabled, 360Kb 5.25 in, 1.2MB 5.25 in, 720Kb 3.5 in, 1.44/1.25MB,
3.5 in and 2.88MB 3.5 in.
4-3
Page 60
X7DBR-8+/X7DBR-i+ User's Manual
IDE Channel 0 Master/Slave, IDE Channel 1 Master/Slave, SATA
Port2 and SATA Port3
These settings allow the user to set the parameters of IDE Channel 0 Master/
Slave, IDE Channel 1 Master/Slave, IDE Channel 2 Master, IDE Channel 3
Master slots. Hit <Enter> to activate the following sub-menu screen for detailed
options of these items. Set the correct confi gurations accordingly. The items
included in the sub-menu are:
Type
Selects the type of IDE hard drive. The options are Auto, (which allows the BIOS
to automatically determine the hard drive's capacity, number of heads, etc.), a
number from 1-39 to select a predetermined type of hard drive, CDROM and
ATAPI Removable. The option "User" will allow the user to enter the parameters
of the HDD installed at this connection. The option "Auto" will allow the BIOS to
automatically confi gure the parameters of the HDD installed at the connection.
Choose the option 1-39 to select a predetermined HDD type. Select CDROM if a
CDROM drive is installed. Select ATAPI if a removable disk drive is installed.
4-4
Page 61
Chapter 4: BIOS
CHS Format
The following items will be displayed by the BIOS:
TYPE: This item displays the type of IDE or SATA Device.
Cylinders: This item indicates the status of Cylinders.
Headers: This item indicates the number of headers.
Sectors: This item displays the number of sectors.
Maximum Capacity: This item displays the maximum storage capacity of the
system.
LBA Format
The following items will be displayed by the BIOS:
Total Sectors: This item displays the number of total sectors available in the
LBA Format.
Maximum Capacity: This item displays the maximum capacity in the LBA
Format.
Multi-Sector Transfers
This item allows the user to specify the number of sectors per block to be
used in multi-sector transfer. The options are Disabled, 4 Sectors, 8 Sectors,
and 16 Sectors.
LBA Mode Control
This item determines whether the Phoenix BIOS will access the IDE Channel 0
Master Device via the LBA mode. The options are Enabled and Disabled.
32 Bit I/O
This option allows the user to enable or disable the function of 32-bit data transfer.
The options are Enabled and Disabled.
Transfer Mode
This option allows the user to set the transfer mode. The options are Standard,
Fast PIO1, Fast PIO2, Fast PIO3, Fast PIO4, FPIO3/DMA1 and FPIO4/DMA2.
Ultra DMA Mode
This option allows the user to select Ultra DMA Mode. The options are Disabled,
Mode 0, Mode 1, Mode 2, Mode 3, Mode 4, and Mode 5.
4-5
Page 62
X7DBR-8+/X7DBR-i+ User's Manual
Parallel ATA
This setting allows the user to enable or disable the function of Parallel ATA. The
options are Disabled and Enabled.
Serial ATA
This setting allows the user to enable or disable the function of Serial ATA. The
options are Disabled and Enabled.
Native Mode Operation
Select the native mode for ATA. The options are: Serial ATA, Both, and Auto.
SATA Controller Mode
Select Compatible to allow the SATA and PATA drives to be automatically-detected
and be placed in the Legacy Mode by the BIOS. Select Enhanced to allow the
SATA and PATA drives to be to be automatically-detected and be placed in the
Native IDE Mode. (*Note: The Enhanced mode is supported by the Windows
2000 OS or a later version.)
When the SATA Controller Mode is set to "Enhanced", the following items will
display:
Serial ATA (SATA) RAID Enable
Select Enable to enable Serial ATA RAID Functions. (*For the Windows OS
environment, use the RAID driver if this feature is set to Enabled. When this item
is set to Enabled, the item: "ICH RAID Code Base" will be available for you to select
either Intel or Adaptec Host RAID fi rmware. If this item is set to Disabled, the item-
SATA AHCI Enable will be available.) The options are Enabled and Disabled.
ICH RAID Code Base
Select Intel to enable Intel's SATA RAID fi rmware. Select Adaptec to use Adaptec's
HostRAID fi rmware. The options are Intel and Adaptec.
SATA AHCI
Select Enable to enable the function of Serial ATA Advanced Host Interface. (*Take
caution when using this function. This feature is for advanced programmers only.
The options are Enabled and Disabled.)
4-6
Page 63
Chapter 4: BIOS
System Memory
This display informs you how much system memory is recognized as being present
in the system.
Extended Memory
This display informs you how much extended memory is recognized as being
present in the system.
4-4 Advanced Setup
Choose Advanced from the Phoenix BIOS Setup Utility main menu with the arrow keys.
You should see the following display. The items with a triangle beside them have sub
menus that can be accessed by highlighting the item and pressing <Enter>.
4-7
Page 64
X7DBR-8+/X7DBR-i+ User's Manual
Boot Features
Access the submenu to make changes to the following settings.
QuickBoot Mode
If enabled, this feature will speed up the POST (Power On Self Test) routine by
skipping certain tests after the computer is turned on. The settings are Enabled
and Disabled. If Disabled, the POST routine will run at normal speed.
QuietBoot Mode
This setting allows you to Enable or Disable the graphic logo screen during
boot-up.
POST Errors
Set to Enabled to display POST Error Messages if an error occurs during bootup.
If set to Disabled, the system will continue to boot without displaying any error
messages even when a boot error occurs.
ACPI Mode
Use the setting to determine if you want to employ ACPI (Advanced Confi guration
and Power Interface) power management on your system. The options are
Yes and No.
Power Button Behavior
If set to Instant-Off, the system will power off immediately as soon as the user
hits the power button. If set to 4-sec., the system will power off when the user
presses the power button for 4 seconds or longer. The options are instant-off
and 4-sec override.
Resume On Modem Ring
Select On to “wake your system up” when an incoming call is received by
your modem. The options are On and Off.
Power Loss Control
This setting allows you to choose how the system will react when power returns
after an unexpected loss of power. The options are Stay Off, Power On, and
Last State.
Watch Dog
If enabled, this option will automatically reset the system if the system is not
active for more than 5 minutes. The options are Enabled and Disabled.
Summary Screen
This setting allows you to Enable or Disable the summary screen which displays
the system confi guration during bootup.
4-8
Page 65
Chapter 4: BIOS
Memory Cache
Cache System BIOS Area
This setting allows you to designate a reserve area in the system memory to be
used as a System BIOS buffer to allow the BIOS write (cache) its data into this
reserved memory area. Select "Write Protect" to enable this function, and this
area will be reserved for BIOS ROM access only. Select "Uncached" to disable this
function and make this area available for other devices.
Cache Video BIOS Area
This setting allows you to designate a reserve area in the system memory to be
used as a Video BIOS buffer to allow the BIOS write (cache) its data into this
reserved memory area. Select "Write Protect" to enable the function and this area
will be reserved for Video BIOS ROM access only. Select "Uncached" to disable
this function and make this area available for other devices.
Cache Base 0-512K
If enabled, this feature will allow the data stored in the base memory area: block
0-512K to be cached (written) into a buffer, a storage area in the Static DROM
(SDROM) or to be written into L1, L2 cache inside the CPU to speed up CPU
operations. Select "Uncached" to disable this function. Select "Write Through" to
allow data to be cached into the buffer and written into the system memory at
the same time. Select "Write Protect" to prevent data from being written into the
base memory area of Block 0-512K. Select "Write Back" to allow CPU to write data
back directly from the buffer without writing data to the System Memory for fast
CPU data processing and operation. The options are Uncached, Write Through,
Write Protect, and Write Back.
Cache Base 512K-640K
If enabled, this feature will allow the data stored in the memory area: 512K-640K
to be cached (written) into a buffer, a storage area in the Static DROM (SDROM)
or written into L1, L2, L3 cache inside the CPU to speed up CPU operations.
Select "Uncached" to disable this function. Select "Write Through" to allow data to
be cached into the buffer and written into the system memory at the same time.
Select "Write Protect" to prevent data from being written into the base memory
area of Block 512-640K. Select "Write Back" to allow CPU to write data back
directly from the buffer without writing data to the System Memory for fast CPU
data processing and operation. The options are Uncached, Write Through, Write
Protect, and Write Back.
Cache Extended Memory
If enabled, this feature will allow the data stored in the extended memory area to
be cached (written) into a buffer, a storage area in the Static DROM (SDROM)
or written into L1, L2, L3 cache inside the CPU to speed up CPU operations.
4-9
Page 66
X7DBR-8+/X7DBR-i+ User's Manual
Select "Uncached" to disable this function. Select "Write Through" to allow data
to be cached into the buffer and written into the system memory at the same
time. Select "Write Protect" to prevent data from being written into the base
memory area of Block 0-512K. Select "Write Back" to allow CPU to write data back
directly from the buffer without writing data to the System Memory for fast CPU
data processing and operation. The options are Uncached, Write Through, Write
Protect, and Write Back.
Discrete MTRR Allocation
If enabled, MTRRs (-Memory Type Range Registers) are confi gured as distinct,
separate units and cannot be overlapped. If enabled, the user can achieve better
graphic effects when using a Linux graphic driver that requires the write-combining
confi guration with 4GB or more memory. The options are Enabled and Disabled.
PCI Confi guration
Access the submenu to make changes to the following settings for PCI devices.
Onboard GLAN1/Onboard GLAN2 (Gigabit- LAN) OPROM Confi gure
Enabling this option provides the capability to boot from GLAN. The options are
Disabled and Enabled.
Onboard SCSI OPROM Confi gure
Enabling this option provides the capitally to boot from SCSI HDD. The options
are Disabled and Enabled.
PCI Parity Error Forwarding
The feature allows SERR and PERR errors detected in PCI slots to be sent
(forwarded) to the BIOS DMI Event Log for the user to review. The options are
Enabled and Disabled.
Reset Confi guration Data
If set to Yes, this setting clears the Extended System Confi guration Data- (ESCD)
area. The options are Yes and No.
Frequency for PCI-X#1, MASS (-Mass Data Storage)/ZCR (-Zero
Channel RAID)
This option allows the user to change the bus frequency for the devices installed
in the slot indicated. The options are Auto, PCI 33 MHz, PCI 66 MHz, PCI-X 66
MHz, PCI-X 100 MHz, and PCI-X 133 MHz. (*Note: PCI-X 133MHz is not supported
by ZCR.)
4-10
Page 67
Chapter 4: BIOS
Slot1 PCI-X 133MHz, Slot2 PCI-Exp x8/x4, Slot3 PCI-Exp x4, Slot4
PCI-Exp x8 and Slot5 PCI-Exp x8
Access the submenu for each of the settings above to make changes to the
following:
Option ROM Scan
When enabled, this setting will initialize the device expansion ROM. The options
are Enabled and Disabled.
Enable Master
This setting allows you to enable the selected device as the PCI bus master.
The options are Enabled and Disabled.
Latency Timer
This setting allows you to set the clock rate for Bus Master. A high-priority, high-
throughout device may benefi t from a greater clock rate. The options are Default,
0020h, 0040h, 0060h, 0080h, 00A0h, 00C0h, and 00E0h. For Unix, Novell and
other Operating Systems, please select the option: other. If a drive fails after
the installation of a new software, you might want to change this setting and
try again. A different OS requires a different Bus Master clock rate.
Large Disk Access Mode
This setting determines how large hard drives are to be accessed. The options are
DOS or Other (for Unix, Novelle NetWare and other operating systems).
Advanced Chipset Control
Access the submenu to make changes to the following settings.
*Warning: Take Caution when changing the Advanced settings. Incorrect
values entered may cause system malfunction. Also, a very high DRAM
frequency or incorrect DRAM timing may cause system instability. When this
occurs, revert to the default setting.
SERR Signal Condition
This setting specifi es the ECC Error conditions that an SERR# is to be asserted.
The options are None, Single Bit, Multiple Bit, and Both.
4GB PCI Hole Granularity
This feature allows you to select the granularity of PCI hole for PCI slots. If MTRRs
are not enough, this option may be used to reduce MTRR occupation. The options
are: 256 MB, 512 MB, 1GB and 2GB.
4-11
Page 68
X7DBR-8+/X7DBR-i+ User's Manual
Memory Branch Mode
This option determines how the two memory branches operate. System address
space can either be interleaved between the two branches or Sequential from one
branch to another. Mirror mode allows data correction by maintaining two copies
of data in two branches. Single Channel 0 allows a single DIMM population during
system manufacturing. The options are Interleave, Sequential, Mirroring, and
Single Channel 0.
Branch 0 Rank Sparing
Select enable to enable the sparing feature for Branch 0 Rank. The options are
Enabled and Disabled.
Branch 1 Rank Sparing
Select enable to enable the sparing feature for Branch 0 Rank. The options are
Enabled and Disabled.
Enhanced x8 Detection
Select Enabled to enable Enhanced x8 DRAM UC Error Detection. The options
are Disabled and Enabled.
Crystal Beach Features
This feature, designed to work with Intel's I/O AT (Acceleration) Technology, will
greatly enhance the performance of TOE devices if enabled. (*Note: A TOE device
is a specialized, dedicated processor that is installed on an add-on card or a
network card to handle some or all packet processing of this add-on card. For this
motherboard, the TOE device is built inside the ESB 2 South Bridge chip.) The
options are Enabled and Disabled.
Route Port 80h Cycles to
This feature allows the user to decide which bus to send debug information to.
The options are PCI and LPC.
Clock Spectrum Feature
If Enabled, the BIOS will monitor the level of Electromagnetic Interference caused
by the components and will attempt to decrease the interference whenever needed.
The options are Enabled and Disabled.
Enabling Multi-Media Timer
Select Yes to activate a set of timers that are alternative to the traditional 8254
timers for the OS use. The options are Yes and No.
USB Function
Select Enabled to activate USB devices specifi ed by the user. The settings are
Enabled and Disabled.
Legacy USB Support
This setting allows you to enable support for Legacy USB devices. The settings
are Enabled and Disabled.
4-12
Page 69
Chapter 4: BIOS
Advanced Processor Options
Access the submenu to make changes to the following settings.
CPU Speed
This is a display that indicates the speed of the installed processor.
Frequency Ratio (*Available when supported by the CPU.)
The feature allows the user to set the internal frequency multiplier for the CPU.
The options are: Default, x12, x13, x14, x15, x16, x17 and x18.
Hyperthreading (*Available when supported by the CPU.)
Set to Enabled to use the Hyperthreading Technology, which will result in increased
CPU performance. The options are Disabled and Enabled.
Core-Multi-Processing (*Available when supported by the CPU.)
Set to Enabled to use a processor's Second Core and beyond. (Please refer to
Intel's web site for more information.) The options are Disabled and Enabled.
Machine Checking (*Available when supported by the CPU.)
Set to Enabled to activate the function of Machine Checking and allow the CPU to
detect and report hardware (machine) errors via a set of model-specifi c registers
(MSRs). The options are Disabled and Enabled.
Thermal Management 2 (*Available when supported by the CPU.)
Set to Enabled to use Thermal Management 2 (TM2) which will lower CPU voltage
and frequency when the CPU temperature reaches a predefi ned overheat threshold.
Set to Disabled to use Thermal Manager 1 (TM1), allowing CPU clocking to be
regulated via CPU Internal Clock modulation when the CPU temperature reaches
the overheat threshold.
C1 Enhanced Mode (*Available when supported by the CPU.)
Set to Enabled to enable Enhanced Halt State to lower CPU voltage/frequency to
prevent overheat. The options are Enabled and Disabled. (*Note: please refer
to Intel’s web site for detailed information.)
Execute Disable Bit (*Available when supported by the CPU.)
Set to Enabled to enable Execute Disable Bit and allow the processor to classify
areas in memory where an application code can execute and where it cannot, and
thus preventing a worm or a virus from inserting and creating a fl ood of codes to
overwhelm the processor or damage the system during an attack.
(*Note: this feature is available when your OS and your CPU support the function
of Execute Disable Bit.) The options are Disabled and Enabled. (Note: For more
information regarding hardware/software support for this function, please refer to
Intel's and Microsoft's web sites.)
4-13
Page 70
X7DBR-8+/X7DBR-i+ User's Manual
Adjacent Cache Line Prefetch (*Available when supported by the CPU.)
The CPU fetches the cache line for 64 bytes if this option is set to Disabled. The
CPU fetches both cache lines for 128 bytes as comprised if Enabled. The options
are Disabled and Enabled.
Hardware Prefetcher (*Available when supported by the CPU.)
Set to this option to enabled to enable the hardware components that are used in
conjunction with software programs to prefetch data in order to shorten execution
cycles and maximize data processing effi ciency. The options are Disabled and
Enabled.
PECI Absent Alarm (*Available when supported by the CPU.)
If set to Enabled, the PECI Absent Alarm will be activated if the function of PECI
(Platform Environment Control Interface) is not available for the onboard process(s)
or for the motherboard. The options are Disabled and Enabled.
Intel <R> Virtualization Technology (*Available when supported by
the CPU.)
Select Enabled to use the feature of Virtualization Technology to allow one platform
to run multiple operating systems and applications in independent partitions, creating
multiple "virtual" systems in one physical computer. The options are Enabled and
Disabled. (*Note: If there is any change to this setting, you will need to power off
and restart the system for the change to take effect.) Please refer to Intel’s web
site for detailed information.
Intel EIST Support (*Available when supported by the CPU.)
Select Enabled to use the Enhanced Intel SpeedStep Technology and allows the
system to automatically adjust processor voltage and core frequency in an effort
to reduce power consumption and heat dissipation. The options are Enabled and
Disabled. Please refer to Intel’s web site for detailed information.
I/O Device Confi guration
Access the submenu to make changes to the following settings.
KBC Clock Input
This setting allows you to select clock frequency for KBC. The options are 6MHz,
8MHz, 12MHz, and 16MHz.
Serial Port A
This setting allows you to assign control of serial port A. The options are Enabled
(user defi ned), Disabled, and Auto (BIOS- or OS- controlled).
Base I/O Address
This setting allows you to select the base I/O address for serial port A. The options
are 3F8, 2F8, 3E8, and 2E8.
4-14
Page 71
Chapter 4: BIOS
Interrupt
This setting allows you to select the IRQ (interrupt request) for serial port A. The
options are IRQ3 and IRQ4.
Serial Port B
This setting allows you to assign control of serial port B. The options are Enabled
(user defi ned), Disabled, Auto (BIOS controlled) and OS Controlled.
Mode
This setting allows you to set the type of device that will be connected to serial
port B. The options are Normal and IR (for an infrared device).
Base I/O Address
This setting allows you to select the base I/O address for serial port B. The
options are 3F8, 2F8, 3E8 and 2E8.
Interrupt
This setting allows you to select the IRQ (interrupt request) for serial port B. The
options are IRQ3 and IRQ4.
Floppy Disk Controller
This setting allows you to assign control of the fl oppy disk controller. The options
are Enabled (user defi ned), Disabled, and Auto (BIOS and OS controlled).
Base I/O Address
This setting allows you to select the base I/O address for the Floppy port. The
options are Primary and Secondary.
4-15
Page 72
X7DBR-8+/X7DBR-i+ User's Manual
DMI Event Logging
Access the submenu to make changes to the following settings.
Event Log Validity
This is a display to inform you of the event log validity. It is not a setting.
Event Log Capacity
This is a display to inform you of the event log capacity. It is not a setting.
View DMI Event Log
Highlight this item and press <Enter> to view the contents of the event log.
Event Logging
This setting allows you to Enable or Disable event logging.
ECC Event Logging
This setting allows you to Enable or Disable ECC event logging.
Mark DMI Events as Read
Highlight this item and press <Enter> to mark the DMI events as read.
Clear All DMI Event Logs
Select Yes and press <Enter> to clear all DMI event logs. The options are Yes
and No.
4-16
Page 73
Chapter 4: BIOS
Console Redirection
Access the submenu to make changes to the following settings.
COM Port Address
This item allows you to specify which COM port to direct the remote console to:
Onboard COM A or Onboard COM B. This setting can also be Disabled.
BAUD Rate
This item allows you to set the BAUD rate for console redirection. The options
are 300, 1200, 2400, 9600, 19.2K, 38.4K, 57.6K, and 115.2K.
Console Type
This item allows you to set console redirection type. The options are VT100,
VT100,8bit, PC-ANSI, 7bit, PC ANSI, VT100+,
VT-UTF8 and ASCII.
Flow Control
This item allows you to select the fl ow control option for console redirection. The
options are: None, XON/XOFF, and CTS/RTS.
Console Connection
This item allows you to decide how console redirection is to be connected: either
Direct or Via Modem.
Continue CR after POST
Choose whether to continue with console redirection after the POST routine.
The options are On and Off.
4-17
Page 74
X7DBR-8+/X7DBR-i+ User's Manual
Hardware Monitor Logic
*Note: The Phoenix BIOS will automatically detect the type of CPU(s) and
hardware monitoring chip used on the motherboard and will display the
Hardware Monitoring Screen accordingly. Your Hardware Monitoring Screen
may look like the one shown on this page, on P. 4-19, or on P. 4-20, depending
on the type of CPU(s) and HW Monitoring chip you are using.
CPU Temperature Threshold
This option allows the user to set a CPU temperature threshold that will activate
the alarm system when the CPU temperature reaches this pre-set temperature
threshold. The options are 70
Highlight this and hit <Enter> to see monitor data for the following items:
CPU1 Temperature
CPU1 Second Core Temperature
CPU2 Temperature
CPU2 Second Core Temperature
System Temperature
o
C, 75oC, 80oC and 85oC.
Fan1-Fan5 Speeds: If the feature of Auto Fan Control is enabled, the BIOS will
automatically display the status of the fans indicated in this item.
Fan Speed Control Modes
This feature allows the user to decide how the system controls the speeds of the
onboard fans. The CPU temperature and the fan speed are correlative. When the
CPU on-die temperature increases, the fan speed will also increase, and vice versa.
This option is to “3-pin fan” to allow the fan speed to be controlled by voltage.
Select “Disable” to disable the fan speed control function to allow the onboard
fans to constantly run at full speed (12V). The Options are: 1. Disable, 2. 3-pin
(Server), 3. 3-pin (Workstation).
Voltage Monitoring
The following items will be monitored and displayed:
P12V_VR0
P12V_VR1
FSB VTT
PXHV Vcore
ES2B Vcore
CPU1Vcore
CPU2Vcore
P3V3
4-18
Page 75
Chapter 4: BIOS
Hardware Monitor Logic
CPU Temperature Threshold (*See the Note on Page 4-18.)
This option allows the user to set a CPU temperature threshold that will activate
the alarm system when the CPU temperature reaches this pre-set temperature
threshold. The options are 70
Highlight this and hit <Enter> to see monitor data for the following items:
CPU1 Temperature
CPU1 Second Core
CPU2 Temperature
CPU2 Second Core
System Temperature
Fan1-Fan5 Speeds: If the feature of Auto Fan Control is enabled, the BIOS will
automatically display the status of the fans indicated in this item.
o
C, 75oC, 80oC and 85oC.
Fan Speed Control Modes
This feature allows the user to decide how the system controls the speeds of the
onboard fans. The CPU temperature and the fan speed are correlative. When the
CPU on-die temperature increases, the fan speed will also increase, and vice versa.
This option is to “3-pin fan” to allow the fan speed to be controlled by voltage.
Select “Disable” to disable the fan speed control function to allow the onboard
fans to constantly run at full speed (12V). The Options are: 1. Disable, 2. 3-pin
(Server), 3. 3-pin (Workstation).
Voltage Monitoring
The following items will be monitored and displayed:
Vcore A
Vcore B
-12V
P1V5
+3.3V
+12V
5Vsb
5VDD
P_VTT
Vbat
4-19
Page 76
X7DBR-8+/X7DBR-i+ User's Manual
Hardware Monitor Logic (*See the Note on Page 4-18.)
CPU Temperature Threshold
This option allows the user to set a CPU temperature threshold that will activate
the alarm system when the CPU temperature reaches this pre-set temperature
threshold. The hardcode default setting is 75
o
C.
CPU1 Temperature/CPU1 Second Core
CPU2 Temperature/CPU2 Second Core
Temperature Monitoring (*Available if supported by the CPU)
Highlight this and hit <Enter> to see monitor data for the following PECI (Platform
Environment Control Interface) items:
PECI Agent 1 Temperature
PECI Agent 2 Temperature
PECI Agent 3 Temperature
PECI Agent 4 Temperature
System Temperature
Fan1-Fan5 Speeds: If the feature of Auto Fan Control is enabled, the BIOS will
automatically display the status of the fans indicated in this item.
Fan Speed Control Modes
This feature allows the user to decide how the system controls the speeds of the
onboard fans. The CPU temperature and the fan speed are correlative. When the
CPU on-die temperature increases, the fan speed will also increase, and vice versa.
This option is to “3-pin fan” to allow the fan speed to be controlled by voltage. Select
“Disable” to disable the fan speed control function to allow the onboard fans to
constantly run at full speed (12V). The Options are: 1. Disable, 2. 3-pin (Server),
3. 3-pin (Workstation).
Voltage Monitoring
The following items will be monitored and displayed:
Vcore A:
Vcore B:
-12V
P1V2_NIC_SEN
+3.3V
+12V
5Vsb
5VDD
P_VTT
Vbat
4-20
Page 77
Chapter 4: BIOS
IPMI (The option is available only when an IPMI card is installed
in the system.)
IPMI Specifi cation Version:
This item displays the current IPMI Version.
Firmware Version: This item displays the current Firmware Version.
System Event Logging
Select Enabled to enable IPMI Event Logging. When this function is set to
Disabled, the system will continue to log events received via system interface.
The options are Enabled and Disabled.
Clear System Event Logging
Enabling this function to force the BIOS to clear the system event logs during the
next cold boot. The options are Enabled and Disabled.
Existing Event Log Number
This item displays the number of the existing event log.
Event Log Control
System Firmware Progress
Enabling this function to log POST progress. The options are Enabled and
Disabled.
BIOS POST Errors
Enabling this function to log POST errors. The options are Enabled and
Disabled.
BIOS POST Watch Dog
Set to Enabled to enable POST Watch Dog. The options are Enabled and
Disabled.
4-21
Page 78
X7DBR-8+/X7DBR-i+ User's Manual
OS Boot Watch Dog
Set to Enabled to enable OS Boot Watch Dog. The options are Enabled and
Disabled.
Timer for Loading OS (Minutes)
This feature allows the user to set the time value (in minutes) for the previous
item: OS Boot Watch Dog by keying-in a desired number in the blank. The default
setting is 10 (minutes.) (Please ignore this option when OS Boot Watch Dog is set
to "Disabled".)
Time Out Option
This feature allows the user to determine what action to take in an event of a system
boot failure. The options are No Action, Reset, Power Off and Power Cycles.
System Event Log/System Event Log (List Mode)
These options display the System Event (SEL) Log and System Event (SEL) Log
in List Mode. Items include: SEL (System Event Log) Entry Number, SEL Record
ID, SEL Record Type, Time Stamp, Generator ID, SEL Message Revision, Sensor
Type, Sensor Number, SEL Event Type, Event Description, and SEL Event Data.
4-22
Page 79
Chapter 4: BIOS
Realtime Sensor Data
This feature display information from motherboard sensors, such as temperatures,
fan speeds and voltages of various components.
4-23
Page 80
X7DBR-8+/X7DBR-i+ User's Manual
4-5 Security
Choose Security from the Phoenix BIOS Setup Utility main menu with the arrow
keys. You should see the following display. Security setting options are displayed
by highlighting the setting using the arrow keys and pressing <Enter>. All Security
BIOS settings are described in this section.
Supervisor Password Is:
This displays whether a supervisor password has been entered for the system.
Clear means such a password has not been used and Set means a supervisor
password has been entered for the system.
User Password Is:
This displays whether a user password has been entered for the system. Clear
means such a password has not been used and Set means a user password has
been entered for the system.
Set Supervisor Password
When the item "Set Supervisor Password" is highlighted, hit the <Enter> key. When
prompted, type the Supervisor's password in the dialogue box to set or to change
supervisor's password, which allows access to the BIOS.
Set User Password
When the item "Set User Password" is highlighted, hit the <Enter> key. When
prompted, type the user's password in the dialogue box to set or to change the
user's password, which allows access to the system at boot-up.
4-24
Page 81
Chapter 4: BIOS
Password on Boot
This setting allows you to decide if a password is required for system boot. The
options are Enabled (password required) and Disabled (password not required).
4-6 Boot
Choose Boot from the Phoenix BIOS Setup Utility main menu with the arrow keys.
You should see the following display. See details on how to change the order and
specs of boot devices in the Item Specifi c Help window. All Boot BIOS settings are
described in this section.
Boot List
Candidate
List
Boot Priority Order/Excluded from Boot Orders
The devices included in the boot list section (above) are bootable devices listed in
the sequence of boot order as specifi ed. The boot functions for the devices included
in the candidate list (above) are currently disabled. Use a <+> key or a <-> key to
move the device up or down. Use the <f> key or the <r> key to specify the type of
an USB device, either fi xed or removable. You can select one item from the boot
list and hit the <x> key to remove it from the list of bootable devices (to make its
resource available for other bootable devices). Subsequently, you can select an
item from the candidate list and hit the <x> key to remove it from the candidate
list and put it in the boot list. This item will then become a bootable device. See
details on how to change the priority of boot order of devices in the "Item Specifi c
Help" window.
4-25
Page 82
X7DBR-8+/X7DBR-i+ User's Manual
4-7 Exit
Choose Exit from the Phoenix BIOS Setup Utility main menu with the arrow keys.
You should see the following display. All Exit BIOS settings are described in this
section.
Exit Saving Changes
Highlight this item and hit <Enter> to save any changes you've made and to exit
the BIOS Setup utility.
Exit Discarding Changes
Highlight this item and hit <Enter> to exit the BIOS Setup utility without saving any
changes you may have made.
Load Setup Defaults
Highlight this item and hit <Enter> to load the default settings for all items in the
BIOS Setup. These are the safest settings to use.
Discard Changes
Highlight this item and hit <Enter> to discard (cancel) any changes you've made.
You will remain in the Setup utility.
Save Changes
Highlight this item and hit <Enter> to save any changes you've made. You will
remain in the Setup utility.
4-26
Page 83
Appendix A: BIOS POST Messages
Appendix A
BIOS POST Messages
During the Power-On Self-Test (POST), the BIOS will check for problems. If a prob-
lem is found, the BIOS will activate an alarm or display a message. The following is
a list of such BIOS messages.
Failure Fixed Disk
Fixed disk is not working or not confi gured properly. Check to see if fi xed disk is
attached properly. Run Setup. Find out if the fi xed-disk type is correctly identifi ed.
Stuck key
Stuck key on keyboard.
Keyboard error
Keyboard not working.
Keyboard Controller Failed
Keyboard controller failed test. May require replacing keyboard controller.
Keyboard locked - Unlock key switch
Unlock the system to proceed.
Monitor type does not match CMOS - Run SETUP
Monitor type not correctly identifi ed in Setup
Shadow Ram Failed at offset: nnnn
Shadow RAM failed at offset nnnn of the 64k block at which the error
was detected.
System RAM Failed at offset: nnnn
System RAM failed at offset nnnn of in the 64k block at which the error
was detected.
Extended RAM Failed at offset: nnnn Extended memory not
working or not confi gured properly at offset nnnn.
System battery is dead - Replace and run SETUP
The CMOS clock battery indicator shows the battery is dead. Replace the
battery and run Setup to reconfi gure the system.
A-1
Page 84
X7DBR-8+/X7DBR-i+ User's Manual
System CMOS checksum bad - Default confi guration used
System CMOS has been corrupted or modifi ed incorrectly, perhaps by an
application program that changes data stored in CMOS. The BIOS installed Default
Setup Values. If you do not want these values, enter Setup and enter your own
values. If the error persists, check the system battery or contact your dealer.
System timer error
The timer test failed. Requires repair of system board.
Real time clock error
Real-Time Clock fails BIOS hardware test. May require board repair.
Check date and time settings
BIOS found date or time out of range and reset the Real-Time Clock. May require
setting legal date (1991-2099).
Previous boot incomplete - Default confi guration used
Previous POST did not complete successfully. POST loads default values and
offers to run Setup. If the failure was caused by incorrect values and they are not
corrected, the next boot will likely fail. On systems with control of wait states,
improper Setup settings can also terminate POST and cause this error on the next
boot. Run Setup and verify that the waitstate confi guration is correct. This error is
cleared the next time the system is booted.
Memory Size found by POST differed from CMOS
Memory size found by POST differed from CMOS.
Diskette drive A error
Diskette drive B error
Drive A: or B: is present but fails the BIOS POST diskette tests. Check to see that
the drive is defi ned with the proper diskette type in Setup and that the diskette drive
is attached correctly.
Incorrect Drive A type - run SETUP
Type of fl oppy drive A: not correctly identifi ed in Setup.
Incorrect Drive B type - run SETUP
Type of fl oppy drive B: not correctly identifi ed in Setup.
A-2
Page 85
Appendix A: BIOS POST Messages
System cache error - Cache disabled
RAM cache failed and BIOS disabled the cache. On older boards, check the cache
jumpers. You may have to replace the cache. See your dealer. A disabled cache
slows system performance considerably.
CPU ID:
CPU socket number for Multi-Processor error.
EISA CMOS not writeable
ServerBIOS2 test error: Cannot write to EISA CMOS.
DMA Test Failed
ServerBIOS2 test error: Cannot write to extended DMA (Direct Memory
Access) registers.
Software NMI Failed
ServerBIOS2 test error: Cannot generate software NMI (Non-Maskable
Interrupt).
Fail-Safe Timer NMI Failed
ServerBIOS2 test error: Fail-Safe Timer takes too long.
device Address Confl ict
Address confl ict for specifi ed device.
Allocation Error for: device
Run ISA or EISA Confi guration Utility to resolve resource confl ict for the
specifi ed device.
CD ROM Drive
CD ROM Drive identifi ed.
Entering SETUP ...
Starting Setup program
Failing Bits: nnnn
The hex number nnnn is a map of the bits at the RAM address which failed
the memory test. Each 1 (one) in the map indicates a failed bit. See errors
230, 231, or 232 above for offset address of the failure in System,
Extended, or Shadow memory.
A-3
Page 86
X7DBR-8+/X7DBR-i+ User's Manual
Fixed Disk n
Fixed disk n (0-3) identifi ed.
Invalid System Confi guration Data
Problem with NVRAM (CMOS) data.
I/O device IRQ confl ict
I/O device IRQ confl ict error.
PS/2 Mouse Boot Summary Screen:
PS/2 Mouse installed.
nnnn kB Extended RAM Passed
Where nnnn is the amount of RAM in kilobytes successfully tested.
nnnn Cache SRAM Passed
Where nnnn is the amount of system cache in kilobytes successfully tested.
nnnn kB Shadow RAM Passed
Where nnnn is the amount of shadow RAM in kilobytes successfully
tested.
nnnn kB System RAM Passed
Where nnnn is the amount of system RAM in kilobytes successfully tested.
One or more I2O Block Storage Devices were excluded from the Setup Boot
Menu
There was not enough room in the IPL table to display all installed I2O block-stor-
age devices.
Operating system not found
Operating system cannot be located on either drive A: or drive C:. Enter Setup and
see if fi xed disk and drive A: are properly identifi ed.
Parity Check 1 nnnn
Parity error found in the system bus. BIOS attempts to locate the address and
display it on the screen. If it cannot locate the address, it displays ????. Parity is
a method for checking errors in binary data. A parity error indicates that some data
has been corrupted.
A-4
Page 87
Appendix A: BIOS POST Messages
Parity Check 2 nnnn
Parity error found in the I/O bus. BIOS attempts to locate the address and display it
on the screen. If it cannot locate the address, it displays ????.
Press <F1> to resume, <F2> to Setup, <F3> for previous
Displayed after any recoverable error message. Press <F1> to start the boot
process or <F2> to enter Setup and change the settings. Press <F3> to display the
previous screen (usually an initialization error of an Option ROM, i.e., an add-on
card). Write down and follow the information shown on the screen.
Press <F2> to enter Setup
Optional message displayed during POST. Can be turned off in Setup.
PS/2 Mouse:
PS/2 mouse identifi ed.
Run the I2O Confi guration Utility
One or more unclaimed block storage devices have the Confi guration Request bit
set in the LCT. Run an I2O Confi guration Utility (e.g. the SAC utility).
System BIOS shadowed
System BIOS copied to shadow RAM.
UMB upper limit segment address: nnnn
Displays the address nnnn of the upper limit of Upper Memory Blocks, indicat-
ing released segments of the BIOS which can be reclaimed by a virtual memory
manager.
Video BIOS shadowed
Video BIOS successfully copied to shadow RAM.
A-5
Page 88
X7DBR-8+/X7DBR-i+ User's Manual
Notes
A-6
Page 89
Appendix B: BIOS POST Codes
Appendix B
BIOS POST Codes
This section lists the POST (Power On Self Test) codes for the PhoenixBIOS. POST
codes are divided into two categories: recoverable and terminal.
Recoverable POST Errors
When a recoverable type of error occurs during POST, the BIOS will display an
POST code that describes the problem. BIOS may also issue one of the follow-
ing beep codes:
1 long and two short beeps - video confi guration error
1 repetitive long beep - no memory detected
Terminal POST Errors
If a terminal type of error occurs, BIOS will shut down the system. Before doing
so, BIOS will write the error to port 80h, attempt to initialize video and write the
error in the top left corner of the screen. The following is a list of codes that may
be written to port 80h.
POST Code Description
01h IPMI Initialization
02h Verify Real Mode
03h Disable Non-Maskable Interrupt (NMI)
04h Get CPU type
06h Initialize system hardware
07h Disable shadow and execute code from the ROM.
08h Initialize chipset with initial POST values
09h Set IN POST fl ag
0Ah Initialize CPU registers
0Bh Enable CPU cache
0Ch Initialize caches to initial POST values
0Eh Initialize I/O component
0Fh Initialize the local bus IDE
10h Initialize Power Management
11h Load alternate registers with initial POST values
12h Restore CPU control word during warm boot
13h Reset PCI Bus Mastering devices
14h Initialize keyboard controller
16h 1-2-2-3 BIOS ROM checksum
17h Initialize cache before memory Auto size
B-1
Page 90
X7DBR-8+/X7DBR-i+ User's Manual
POST Code Description
18h 8254 timer initialization
1Ah 8237 DMA controller initialization
1Ch Reset Programmable Interrupt Controller
20h 1-3-1-1 Test DRAM refresh
22h 1-3-1-3 Test 8742 Keyboard Controller
24h Set ES segment register to 4 GB
28h Auto size DRAM
29h Initialize POST Memory Manager
2Ah Clear 512 kB base RAM
2Ch 1-3-4-1 RAM failure on address line xxxx*
2Eh 1-3-4-3 RAM failure on data bits xxxx* of low byte of
memory bus
2Fh Enable cache before system BIOS shadow
32h Test CPU bus-clock frequency
33h Initialize Phoenix Dispatch Manager
36h Warm start shut down
38h Shadow system BIOS ROM
3Ah Auto size cache
3Ch Advanced confi guration of chipset registers
3Dh Load alternate registers with CMOS values
41h Initialize extended memory for RomPilot (optional)
42h Initialize interrupt vectors
45h POST device initialization
46h 2-1-2-3 Check ROM copyright notice
48h Check video confi guration against CMOS
49h Initialize PCI bus and devices
4Ah Initialize all video adapters in system
4Bh QuietBoot start (optional)
4Ch Shadow video BIOS ROM
4Eh Display BIOS copyright notice
4Fh Initialize MultiBoot
50h Display CPU type and speed
51h Initialize EISA board (optional)
52h Test keyboard
54h Set key click if enabled
55h Enable USB devices
58h 2-2-3-1 Test for unexpected interrupts
59h Initialize POST display service
5Ah Display prompt “Press <ESC> to enter SETUP”
5Bh Disable CPU cache
B-2
Page 91
Appendix B: BIOS POST Codes
POST Code Description
5Ch Test RAM between 512 and 640 kB
60h Test extended memory
62h Test extended memory address lines
64h Jump to UserPatch1
66h Confi gure advanced cache registers
67h Initialize Multi Processor APIC
68h Enable external and CPU caches
69h Setup System Management Mode (SMM) area
6Ah Display external L2 cache size
6Bh Load custom defaults (optional)
6Ch Display shadow-area message
70h Display error messages
72h Check for confi guration errors
76h Check for keyboard errors
7Ch Set up hardware interrupt vectors
7Dh Initialize Intelligent System Monitoring (optional)
7Eh Initialize coprocessor if present
80h Disable onboard Super I/O ports and IRQs (optional)
81h Late POST device initialization
82h Detect and install external RS232 ports
83h Confi gure non-MCD IDE controllers
84h Detect and install external parallel ports
85h Initialize PC-compatible PnP ISA devices
86h Re-initialize onboard I/O ports.
87h Confi gure Motherboard Confi gurable Devices
(optional)
88h Initialize BIOS Data Area
89h Enable Non-Maskable Interrupts (NMIs)
8Ah Initialize Extended BIOS Data Area
8Bh Test and initialize PS/2 mouse
8Ch Initialize fl oppy controller
8Fh Determine number of ATA drives (optional)
90h Initialize hard-disk controllers
91h Initialize local-bus hard-disk controllers
92h Jump to UserPatch2
93h Build MPTABLE for multi-processor boards
95h Install CD ROM for boot
96h Clear huge ES segment register
97h Fix up Multi Processor table
98h 1-2 Search for option ROMs and shadow if successful. One
long, two short beeps on checksum failure
B-3
Page 92
X7DBR-8+/X7DBR-i+ User's Manual
POST Code Description
99h Check for SMART Drive (optional)
9Ch Set up Power Management
9Dh Initialize security engine (optional)
9Eh Enable hardware interrupts
9Fh Determine number of ATA and SCSI drives
A0h Set time of day
A2h Check key lock
A4h Initialize typematic rate
A8h Erase <ESC> prompt
AAh Scan for <ESC> key stroke
ACh Enter SETUP
AEh Clear Boot fl ag
B0h Check for errors
B1h Inform RomPilot about the end of POST (optional)
B2h POST done - prepare to boot operating system
B4h 1 One short beep before boot
B5h Terminate QuietBoot (optional)
B6h Check password (optional)
B7h Initialize ACPI BIOS and PPM Structures
B9h Prepare Boot
BAh Initialize SMBIOS
BCh Clear parity checkers
BDh Display MultiBoot menu
BEh Clear screen (optional)
BFh Check virus and backup reminders
C0h Try to boot with INT 19
C1h Initialize POST Error Manager (PEM)
C2h Initialize error logging
C3h Initialize error display function
C4h Initialize system error fl ags
C6h Console redirection init.
C7h Unhook INT 10h if console redirection enabled
C8h Force check (optional)
C9h Extended ROM checksum (optional)
CDh Reclaim console redirection vector
B-4
Page 93
Appendix B: BIOS POST Codes
POST Code Description
D2h Unknown interrupt
D4h Check Intel Branding string
D8h Alert Standard Format initialization
D9h Late init for IPMI
DEh Log error if micro-code not updated properly
The following are for boot block in Flash ROM
POST Code Description
E0h Initialize the chipset
E1h Initialize the bridge
E2h Initialize the CPU
E3h Initialize system timer
E4h Initialize system I/O
E5h Check force recovery boot
E6h Checksum BIOS ROM
E7h Go to BIOS
E8h Set Huge Segment
E9h Initialize Multi Processor
EAh Initialize OEM special code
EBh Initialize PIC and DMA
ECh Initialize Memory type
EDh Initialize Memory size
EEh Shadow Boot Block
EFh System memory test
F0h Initialize interrupt vectors
F1h Initialize Run Time Clock
F2h Initialize video
F3h Initialize System Management Manager
F4h Output one beep
F5h Clear Huge Segment
F6h Boot to Mini DOS
F7h Boot to Full DOS
* If the BIOS detects error 2C, 2E, or 30 (base 512K RAM error), it displays an addi-
tional word-bitmap (xxxx) indicating the address line or bits that failed. For example,
“2C 0002” means address line 1 (bit one set) has failed. “2E 1020" means data bits
12 and 5 (bits 12 and 5 set) have failed in the lower 16 bits. The BIOS also sends
the bitmap to the port-80 LED display. It fi rst displays the checkpoint code, followed
by a delay, the high-order byte, another delay, and then the loworder byte of the error.
It repeats this sequence continuously.
B-5
Page 94
X7DBR-8+/X7DBR-i+ User's Manual
Notes
B-6
Page 95
Appendix C: Intel HostRAID Setup Guidelines
Appendix C
Intel HostRAID Setup Guidelines
After all the hardware has been installed, you must fi rst confi gure Intel's ESB2
SATA RAID* before you install the Windows Operating System and other software
drivers.
Important Notes to the User:
*Note 1: If you do not wish to confi gure onboard SATA RAID functions, please go
directly to Section C-2, Appendix D and Appendix E for Operating System & Other
Software Installation.
*Note 2: This chapter describes RAID Confi guration Instructions for the Intel ESB2
RAID Controller designed for the Windows OS.
C-1 Introduction to Serial ATA and Parallel ATA
To confi gure the SATA RAID functions, you must fi rst use the Intel ESB2 SATA
RAID Utility program to confi gure the RAID Level that you desire before installing
the Windows XP/2000/2003 operating system and other software drivers. (The
necessary drivers are all included on the Supermicro CD that came packaged with
your motherboard.) Note that the current version of the ESB2 SATA RAID Utility
can only support Windows XP/2000/2003 Operating Systems.
Serial ATA (SATA)
Serial ATA (SATA) is a physical storage interface that uses a single cable with a
minimum of four wires to create a point-to-point connection between devices. It is a
serial link, which supports transfer rates up to 3.0 Gbps. Because the serial cables
used in SATA are thinner than the traditional cables used in Parallel ATA (PATA),
SATA systems have better airfl ow and can be installed in smaller chassis than
Parallel ATA. In addition, the cables used in PATA are limited to a length of 40cm,
while Serial ATA cables can be up to one meter in length. Overall, SATA provides
better functionality than PATA.
Introduction to the Intel ESB2 Serial RAID Controller Hub
Located in the South Bridge of the 5000P chipset, the I/O Controller Hub (ESB2)
provides the I/O subsystem with access to the rest of the system. It supports an
1-channel UltraATA/100 Bus Master IDE controller (PATA) and six Serial ATA (SATA)
ports. The ESB2 supports the following PATA and SATA device confi gurations:
Legacy mode and Native mode.
C-1
Page 96
X7DBR-8+/X7DBR-i+ User's Manual
The Intel HostRAID Confi gurations
The following types of Intel's HostRAID confi gurations are supported:
RAID 0 (Data Striping): this writes data in parallel, interleaved ("striped") sections
of two hard drives. Data transfer rate is doubled over using a single disk.
RAID1 (Data Mirroring): an identical data image from one drive is copied to another
drive. The second drive must be the same size or larger than the fi rst drive.
RAID 10 (Striping & Mirroring): RAID 0 and 1 schemes are combined (without parity
information) to get the benefi ts of both.
RAID 5: both data and parity information are striped and mirrored across three or
more hard drives.
The Intel Matrix Storage
The Intel Matrix Storage, supported by the ESB2, allows the user to create RAID
0, RAID 1, RAID 10 and RAID 5 sets by using only six identical hard disk drives.
The Intel Matrix Storage Technology creates two partitions on each hard disk
drive and generate a virtual RAID 0, RAID 1, RAID 10 and RAID 5 sets. It also
allows you the change the HDD partition size without any data.
Confi guring BIOS settings for SATA RAID Functions (Native Mode)
1. Press the <Del> key during system bootup to enter the BIOS Setup Utility.
Note: If it is the fi rst time powering on the system, we recommend you load the
Optimized Default Settings. If you have already done so, please skip to Step 3.
2. Use the arrow keys to select the "Exit" Settings. Once in the "Exit" settings,
Scroll down to select "Load Optimized Default Settings" and press the <Enter>
key. Select "OK" to confi rm the selection. Press the <Enter> key to load the default
settings for the BIOS.
3. Use the arrow keys to select the "Main" section in BIOS.
4. Scroll down to "SATA Controller Mode" and press the <Enter> key to select
"Enhanced"
5. Scroll down to "SATA RAID Enabled" and press <Enter>. Then, select "En-
abled."
6. Scroll down to "Exit". Select "Save and Exit" from the "Exit" menu. Press the
<Enter> key to save the changes and exit the BIOS.
7. Once you've exited the BIOS Utility, the system will re-boot.
8. During the system boot-up, press the <Ctrl> and <I> keys simultaneously to run
the Intel RAID Confi guration Utility when prompted by the following message: Press
<Ctrl> <I> for the Intel RAID Confi guration Utility.
(*Note: The Intel RAID Confi guration Utility is only available for systems
with two or more drives installed. The Intel RAID Utility screen will not
display in systems with one drive installed.)
C-2
Page 97
Appendix C: Intel HostRAID Setup Guidelines
Using the Intel ESB2 SATA RAID Utility Program
1. Creating, Deleting and Resetting RAID Volumes:
a. After the system exits from the BIOS Setup Utility, the system will automatically
reboot. The following screen appears after Power-On Self Test.
b. When you see the above screen, press the <Ctrl> and the <I> keys simultane-
ously to have the main menu of the SATA RAID Utility appear:
(*Note: All graphics and screen shots shown in the manual are for reference only. The screen shots shown in the manual do not imply Supernicro's
endorsement or non-endorsement on any 3rd party's product. Your screens
may or many not look exactly the same as the graphics shown in this
manual.)
C-3
Page 98
X7DBR-8+/X7DBR-i+ User's Manual
Creating a RAID 0 Volume:
a. Select "Create RAID Volume" from the main menu and press the <Enter> key.
The following screen will appear:
b. Specify a name for the RAID 0 set and press the <Tab> key or the <Enter> key
to go to the next fi eld. (You can use the <Esc> key to select the previous menu.)
c. When RAID Level item is highlighted, press the <Up Arrow>, <Down Arrow> keys
to select RAID 0 (Stripe) and hit <Enter>.
d. When the Disks item is highlighted, press <Enter> to select the HDD to confi gure
as RAID. The following pop-up screen (*See Note on Page C-3) displays:
e. Use the <Up Arrow>, <Down Arrow> keys to highlight a drive and press <Space>
to select it. A triangle appears to confi rm the selection of the drive.
f. Use the <Up Arrow>, <Down Arrow> keys to select the stripe size, ranged from
4 KB to 128 KB for the RAID 0 array, and hit <Enter>. (*Note: For a server, please
use a lower stripe size, and for a multimedia system, use a higher stripe size. The
default stripe size is 128 KB.)
g. Press <Enter> when the Create Volume item is highlighted. A warning message
displays.
h. When asked "Are you sure you want to create this volume (Y/N), press "Y" to
create the RAID volume, or type "N" to go back to the Create Volume menu.
C-4
Page 99
Appendix C: Intel HostRAID Setup Guidelines
Creating a RAID 1 Volume:
a. Select "Create RAID Volume" from the main menu and press the <Enter> key.
The following screen will appear:
b. Specify a name for the RAID 1 set and press the <Tab> key or the <Enter> key
to go to the next fi eld. (You can use the <Esc> key to select the previous menu.)
c. When RAID Level item is highlighted, press the <Up Arrow>, <Down Arrow> keys
to select RAID 1 (Mirror) and hit <Enter>.
d. When the Capacity item is highlighted, enter your RAID volume capacity and hit
<Enter>. The default setting is the maximum capacity allowed.
e. Press <Enter> when the Create Volume item is highlighted. A warning message
displays.
f. When asked "Are you sure you want to create this volume (Y/N), press "Y" to
create the RAID volume, or type "N" to go back to the Create Volume menu.
C-5
Page 100
X7DBR-8+/X7DBR-i+ User's Manual
Creating a RAID 10 (RAID 1+ RAID 0):
a. Select "Create RAID Volume" from the main menu and press the <Enter> key.
The following screen will appear:
b. Specify a name for the RAID 10 set and press <Enter>.
c. When RAID Level item is highlighted, use the <Up Arrow>, <Down Arrow> keys
to select RAID 10 (RAID1 + RAID0) and hit <Enter>.
d. When the Stripe Size is highlighted, use the <Up Arrow>, <Down Arrow> keys to
select the stripe size from 4 KB to 128 KB for your RAID 10 and hit <Enter>. The
default setting is 64 KB. (*Note: For a server, please use a lower stripe size, and
for a multimedia system, use a higher stripe size.)
e. When the RAID Volume Capacity item is highlighted, enter your RAID volume
capacity and hit <Enter>. The default setting is the maximum capacity allowed.
f. Press <Enter> when the Create Volume item is highlighted. A warning message
displays.
g. When asked "Are you sure you want to create this volume (Y/N), press "Y" to
create the RAID volume, or type "N" to go back to the Create Volume menu.
C-6
Loading...