Supermicro X7DB3 User Manual

®

SUPER

X7DB3

USER’S MANUAL

Revision 1.1c

The information in this User’s Manual has been carefully reviewed and is believed to be accurate. The vendor assumes no responsibility for any inaccuracies that may be contained in this document, makes no commitment to update or to keep current the information in this manual, or to notify any

person or organization of the updates. Please Note: For the most up-to-date version of this

manual, please see our web site at www.supermicro.com.

Super Micro Computer, Inc. ("Supermicro") reserves the right to make changes to the product described in this manual at any time and without notice. This product, including software, if any, and documentation may not, in whole or in part, be copied, photocopied, reproduced, translated or reduced to any medium or machine without prior written consent.

IN NO EVENT WILL SUPER MICRO COMPUTER, INC. BE LIABLE FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, SPECULATIVE OR CONSEQUENTIAL DAMAGES ARISING FROM THE USE OR INABILITY TO USE THIS PRODUCT OR DOCUMENTATION, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IN PARTICULAR, SUPER MICRO COMPUTER, INC. SHALL NOT HAVE LIABILITY FOR ANY HARDWARE, SOFTWARE, OR DATA STORED OR USED WITH THE PRODUCT, INCLUDING THE COSTS OF REPAIRING, REPLACING, INTEGRATING, INSTALLING OR RECOVERING SUCH HARDWARE, SOFTWARE, OR DATA.

Any disputes arising between manufacturer and customer shall be governed by the laws of Santa Clara County in the State of California, USA. The State of California, County of Santa Clara shall be the exclusive venue for the resolution of any such disputes. Supermicro's total liability for all claims will not exceed the price paid for the hardware product.

FCC Statement: This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the manufacturer’s instruction manual, may cause harmful interference with radio communications. Operation of this equipment in a residential area is likely to cause harmful interference, in which case you will be required to correct the interference at your own expense.

California Best Management Practices Regulations for Perchlorate Materials: This Perchlorate warning applies only to products containing CR (Manganese Dioxide) Lithium coin cells. “Perchlorate Material-special handling may apply. See www.dtsc.ca.gov/hazardouswaste/perchlorate”

WARNING: Handling of lead solder materials used in this product may expose you to lead, a chemical known to the State of California to cause birth defects and other

reproductive harm.

Manual Revision 1.1c

Release Date: Dec. 12, 2008

Unless you request and receive written permission from Supermicro Computer, Inc., you may not copy any part of this document.

Information in this document is subject to change without notice. Other products and companies referred to herein are trademarks or registered trademarks of their respective companies or mark holders.

Printed in the United States of America

Preface

About This Manual

This manual is written for system integrators, PC technicians and

knowledgeable PC users. It provides information for the installation and use of

the

core/dual core processors at a front side bus speed of 1.333 GHz/1.066 GHz/677

MHz. With dual Xeon 64-bit quad core/dual core processors, the 5000P chipset, and

eight DDR2 FBD 667/533 memory modules built-in, the X7DB3 offers substantial

functionality and performance enhancements to the motherboards based on the

quad core/dual core NetBurst microarchitecture while remaining compatible with

the 32-bit based software. Key features include Intel Hyper-Threading Technology,

Virtualization Technology, Hyper Pipelined Technology, Execution Trace Cache,

Thermal Monitor 1/2 (TM1/TM2), Enhanced Intel SpeedStep technology, Advanced

Dynamic Execution, Advanced Transfer Cache, Streaming SIMD Extensions 3

(SSE3) and Extended Memory 64 Technology (EM64T). These features allow the

motherboard to operate at much higher speeds with better power management in

much safer environments than the traditional motherboards. The X7DB3 is ideal for

high performance dual processor (DP) enterprise server/workstation environments.

This product is intended to be professionally installed.

X7DB3 motherboard. The X7DB3 supports dual Intel 64-bit quad

Preface

Manual Organization

Chapter 1 describes the features, speciﬁ cations and performance of the mother-

board and provides detailed information about the chipset.

Chapter 2 provides hardware installation instructions. Read this chapter when

installing the processor, memory modules and other hardware components into

the system. If you encounter any problems, see Chapter 3, which describes

troubleshooting procedures for the video, the memory and the system setup stored

in the CMOS.

Chapter 4 includes an introduction to BIOS and provides detailed information on

running the CMOS Setup utility.

Appendix A provides BIOS POST Codes. Appendix B and Appendix C list the

Windows OS and other software installation instructions.

Conventions Used in the Manual:

Special attention should be given to the following symbols for proper installation and to prevent damage done to the components or injury to yourself:

Danger/Caution: Instructions to be strictly followed to prevent catastrophic

system failure or to avoid bodily injury.

Warning: Important information given to ensure proper system installation or

to prevent damage to the components.

Note: Additional Information given to differentiate various models or to ensure cor-

rect system setup

iii

X7DB3 User's Manual

Table of Contents

Preface

About This Manual ...................................................................................................... iii

Manual Organization ................................................................................................... iii

Conventions Used in the Manual .................................................................................. iii

Chapter 1: Introduction

1-1 Overview ......................................................................................................... 1-1

Checklist ................................................................................................... 1-1

Contacting Supermicro ............................................................................. 1-2

X7DB3 Image ............................................................................. 1-3

X7DB3 Layout ............................................................................ 1-4

Quick Reference ...................................................................................... 1-5

Motherboard Features ................................................................................ 1-6

Intel 5000P Chipset: System Block Diagram ........................................... 1-8

1-2 Chipset Overview ........................................................................................... 1-9

1-3 Special Features ........................................................................................... 1-10

1-4 PC Health Monitoring .................................................................................... 1-10

1-5 ACPI Features .............................................................................................. 1-11

1-6 Power Supply ............................................................................................... 1-12

1-7 Super I/O ........................................................................................................ 1-12

Chapter 2: Installation

2-1 Static-Sensitive Devices ................................................................................. 2-1

Precautions ................................................................................................ 2-1

Unpacking ................................................................................................ 2-1

2-2 Processor and Heatsink Installation ............................................................... 2-2

2-3 Installing DIMMs ............................................................................................. 2-6

2-4 Control Panel Connectors and IO Ports ......................................................... 2-8

A. Back Panel Connectors/IO Ports .............................................................. 2-8

B. Front Control Panel ................................................................................... 2-9

C. Front Control Panel Pin Deﬁ nitions ........................................................ 2-10

NMI Button ............................................................................................. 2-10

Power LED ............................................................................................. 2-10

HDD LED .............................................................................................. 2-11

NIC1/NIC2 LEDs ................................................................................... 2-11

Overheat/Fan Fail LED ......................................................................... 2-12

Power Fail LED ........................................................................................ 2-12

Reset Button ......................................................................................... 2-13

iv

Table of Contents

Power Button .......................................................................................... 2-13

2-5 Connecting Cables ....................................................................................... 2-14

ATX Power Connector .......................................................................... 2-14

Processor Power Connector ................................................................. 2-14

Universal Serial Bus (USB0/1) ................................................................ 2-15

Chassis Intrusion .................................................................................... 2-15

Fan Headers .......................................................................................... 2-16

Keylock ..................................................................................................... 2-16

ATX PS/2 Keyboard and Mouse Ports ..................................................... 2-17

Serial Ports ............................................................................................. 2-17

Wake-On-Ring .......................................................................................... 2-18

Wake-On-LAN .......................................................................................... 2-18

GLAN (Ethernet Ports) ............................................................................. 2-19

Speaker/Power LED Header .................................................................. 2-19

Power Fault .............................................................................................. 2-20

Alarm Reset .............................................................................................. 2-20

Overheat LED/Fan Fail ............................................................................ 2-21

SMB Connector ........................................................................................ 2-21

SMB Power Connector ............................................................................. 2-22

VGA Connector ........................................................................................ 2-22

Compact Flash Card PWR Connector ..................................................... 2-23

SGPIO Headers ....................................................................................... 2-23

2-6 Jumper Settings ............................................................................................ 2-24

Explanation of Jumpers ......................................................................... 2-24

GLAN Enable/Disable ............................................................................ 2-24

Clear CMOS ............................................................................................. 2-25

Watch Dog ................................................................................................ 2-25

SAS Controller Enabled/Disabled ............................................................ 2-26

VGA Enable/Disable ................................................................................. 2-26

3rd PWR Supply PWR Fault .................................................................... 2-27

Compact Flash Master/Slave Enable/Disable .......................................... 2-28

2

I

C Bus to PCI-X-PCI-E Slots .................................................................. 2-28

2-7 Onboard Indicators ....................................................................................... 2-29

GLAN LEDs .............................................................................................. 2-30

Backpanel SAS Activity LED .................................................................... 2-30

Onboard SAS Activity LED ..................................................................... 2-30

2-8 Parallel Port, Floppy, Hard Disk Drive and SIMLP IPMI Connections ......... 2-31

Parallel Port Connector ........................................................................... 2-31

Floppy Connector .................................................................................... 2-32

v

X7DB3 User's Manual

SIMLP IPMI Slot ...................................................................................... 2-32

IDE Connectors ....................................................................................... 2-33

Chapter 3: Troubleshooting

3-1 Troubleshooting Procedures ........................................................................... 3-1

Before Power On ....................................................................................... 3-1

No Power ................................................................................................... 3-1

No Video .................................................................................................. 3-1

Memory Errors ........................................................................................... 3-1

Losing the System’s Setup Conﬁ guration ................................................ 3-2

3-2 Technical Support Procedures ........................................................................ 3-2

3-3 Frequently Asked Questions ........................................................................... 3-3

3-4 Returning Merchandise for Service ................................................................. 3-4

Chapter 4: BIOS

4-1 Introduction ....................................................................................................... 4-1

4-2 Running Setup ................................................................................................. 4-2

4-3 Main BIOS Setup ............................................................................................. 4-2

4-4 Advanced Setup ............................................................................................... 4-7

4-5 Security Setup ............................................................................................... 4-24

4-6 Boot Setup ...................................................................................................... 4-25

4-7 Exit .................................................................................................................. 4-26

Appendices:

Appendix A: BIOS POST Codes ................................................................................ A-1

Appendix B: Installing the Windows OS ..................................................................B-1

Appendix C: Installing Other Software Programs and Drivers...................................C-1

vi

Chapter 1: Introduction

Chapter 1

Introduction

1-1 Overview

Checklist

Congratulations on purchasing your computer motherboard from an acknowledged

leader in the industry. Supermicro boards are designed with the utmost attention to

detail to provide you with the highest standards in quality and performance. Check

that the following items have all been included with your motherboard. If anything

listed here is damaged or missing, contact your retailer.

All the following items are included in the retail box.

One (1) Super Micro Mainboard

•

One (1) ribbon cable for IDE devices (CBL-036L-02)•

One (1) Serial Port cable (CBL-010L-01) •

One (1) USB cable (CBL-083)•

One (1) ﬂ oppy ribbon cable (CBL-022L) •

Two (2) SAS cable (CBL-097L-01)•

Four (4) SATA cables (CBL-044L)•

One (1) I/O backpanel shield (CSE-PT07L)•

One (1) Super Micro CD containing drivers and utilities (CDR-X7)•

One (1) User's/BIOS Manual•

1-1

X7DB3 User's Manual

Contacting Supermicro

Headquarters

Address: Super Micro Computer, Inc.

980 Rock Ave.

San Jose, CA 95131 U.S.A.

Tel: +1 (408) 503-8000

Fax: +1 (408) 503-8008

Email: marketing@supermicro.com (General Information)

support@supermicro.com (Technical Support)

Web Site: www.supermicro.com

Europe

Address: Super Micro Computer, B.V.

Het Sterrenbeeld 28, 5215 ML

's-Hertogenbosch, The Netherlands

Tel: +31 (0) 73-6400390

Fax: +31 (0) 73-6416525

Email: sales@supermicro.nl (General Information)

support@supermicro.nl (Technical Support)

rma@supermicro.nl (Customer Support)

Asia-Paciﬁ c

Address: Super Micro Computer, Inc.

4F, No. 232-1, Liancheng Rd.

Chung-Ho 235, Taipei County

Taiwan, R.O.C.

Tel: +886-(2) 8226-3990

Fax: +886-(2) 8226-3991

Web Site: www.supermicro.com.tw

Technical Support:

Email: support@supermicro.com.tw

Tel: 886-2-8228-1366, ext.132 or 139

1-2

X7DB3 Image

Chapter 1: Introduction

Note: The drawings and pictures shown in this manual were based on the

latest PCB Revision available at the time of publishing of the manual. The

motherboard you’ve received may or may not look exactly the same as the

graphics shown in the manual.

1-3

X7DB3 User's Manual

A

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Notes:

1. Jumpers not indicated are for test purposes only.

2. " " indicates the location of Pin 1.

3. SEPC: Supermicro Enhanced Power Connector, specially designed to support

Supermicro 2U Riser Card only.

4. LE 1 is the 5V Standby Power LED Indicator. When LE1 is off, the system is

off. When the green light is on, the system is on. When the yellow light is on, the

system is off, but the AC power cable is still connected. Make sure to disconnect

the power cable before removing or installing components.

5. For the ZCR card to function properly, be sure to install it in the green slot.

Act#2 SAS2:Act Act#6 SAS6:Act

Act#3 SAS3:Act Act#7 SAS7:Act

1-4

Chapter 1: Introduction

Quick Reference ( X7DB3)

Jumper Description Default Setting

27, J28 I J3P 3rd PWR Failure Detect Open (Disabled)

JBT1 CMOS Clear See Chapter 2

JCF1 Compact Card Master/Slave Select On (Master)

JPG1 VGA Enable Pins 1-2 (Enabled)

JPL1/ JPL2 GLAN1/GLAN2 Enable Pins 1-2 (Enabled)

JPS1 SAS Controller Enable Pins 1-2 (Enabled)

JWD Watch Dog Pins 1-2 (Reset)

Connector Description

ATX PWR (JPW1) Primary 24-Pin ATX PWR Connector

Aux. PWR/CPU PWR +12V 4-pin PWR (JWP2)/+12V 8-pin PWR(JPW3)

ACT#0-ACT#7 SAS Activity LED Indicators (See Page 1-4)

Alarm Reset (JAR) Alarm Reset (*Open: normal)

BP LED Connector(JSLED1) Back Panel Activity LED Connector

Chassis Intrusion (JL1) Chassis Intrusion Header

COM1/COM2 COM1/COM2 Serial Port Connector/Header

Compact PWR(JWF1) Compact Card PWR Connector (*Used if JCF1 is on.)

DIMM#1A-DIMM#4B Memory DDRII Slots

FAN 1-8 Fans 1-8 (CPU Fans/Chassis Fans)

Floppy (J22) Floppy Disk Drive Connector

FP CTRL (JF1) Front Control Panel Connector

GLAN 1/2 (JLAN1/2) G-bit Ethernet Ports

IDE1/IDE2 (*Note) IDE1 Hard Drive (JIDE1)/Compact Flash Card (JIDE2)

Keylock (JK1) Keylock Header

OH LED (JOH1) Overheat LED

Parallel (J21) Parallel (Printer) Port

PSF Power Supply Failure (See Chapter 2)

PWR LED (LE1) PWR LED Indicator (*Note 5 on Pg.1-4)

PWR LED/SPKR (JD1) PWR LED(pins1-3)/SpeakerHeader (pins 4-7)

PWR SMB (J17) Power System Management (I

SATA0-SATA5 Intel SATA 0-5 Connectors

SAS 0-3, SAS 4-7 SAS Connectors 0-3 (JSA1), SAS 4-7 (JSA2)

SGPIO 1/2(J29,J30) Serial General Purpose Input/Output Headers

SMB (J18) System Management Bus Header

Slot 7 SIM Low Proﬁ le IPMI Connector

USB 0/1,USB 2/3, USB4 Back Panel USB 0/1, Front Panel USB 2/3, FP USB4

VGA (J15) VGA Connector

WOL (JWOL) Wake-on-LAN Header

WOR (JWOR) Wake-on-Ring Header

2

C Bus to PCI-X/PCI-E Slots Open (Disabled)

2

C) Header

Note: JIDE2 is for Compact Card Use only. For Compact Card to work properly,

please enable JCF1 by putting cap on it and connect JWF1 to a power supply.

1-5

X7DB3 User's Manual

Motherboard Features

CPU

• Dual Intel

®

64-bit Xeon LGA 771 quad core/dual core processors at a front side

bus speed of 1.333 GHz/1.066 GHz/677 MHz with a system clock speed of

333/267/166 MHz

Memory

• Eight 240-pin DIMM sockets with support up to 32 GB DDR2 Fully Buffered

(FBD) ECC 667/533 Memory (*See Section 2-3 in Chapter 2 for DIMM Slot

Population.)

Chipset

• Intel 5000P chipset, including: the 5000P Memory Control Hub (MCH), the En-

terprise South Bridge 2 (ESB2), and the I/O subsystem (PXH).

Expansion Slots

• Three PCI-Express slots (*two slots at x8@4GB/sec, one slot x4@2GB/sec. on

x8 connector)

• Three 64-bit PCI-X slots (*two PCI-X-133 slots, one PCI-X-100 w/ZCR slot)

• One SPEC slot (*for Supermicro's 2U Active Riser cards)

BIOS

• 8 Mb Phoenix

®

Flash ROM

• DMI 2.3, PCI 2.2, ACPI 1.0, ACPI 2.0, Plug and Play (PnP), SMBBIOS 2.3

PC Health Monitoring

• Onboard voltage monitors for CPU cores, chipset voltage, +1.8V, +3.3V, +5V,

+12V, −12V, +3.3V Standby, and +5V standby

• Fan status monitor with ﬁ rmware control

• CPU/chassis temperature monitors

• CPU fan auto-off in sleep mode

• CPU slow-down on temperature overheat

• CPU thermal trip support for processor protection, power LED

• Power-up mode control for recovery from AC power loss

• Auto-switching voltage regulator for CPU cores

• System overheat/Fan Fail LED Indicator and control

• Chassis intrusion detection

• System resource alert via Supero Doctor III

• Low noise fan speed control

• Pulse Width Modulated (PWM) fan control

2

• I

C temperature sensing monitoring

• Thermal Monitor 2 (TM2) support

1-6

Chapter 1: Introduction

• Intel Virtualization Technology support

• PECI (Platform Enhancement Conﬁ guration Interface) ready

ACPI Features

• Slow blinking LED for suspend state indicator

• Main switch override mechanism

• ACPI Power Management

Onboard I/O

• Adaptec AIC 9410 SAS Controller supports eight SAS ports (RAID 0, 1,10)

• Six SATA 3.0Gbps ports (RAID 0, 1,10, 5 for the Windows OS)

• One ZCR slot supports Supermicro's LPZCR2 Add-on card (*optional for SAS)

• One SIMLP IPMI Slot

• Intel 82563 Gigabit Ethernet controller supporting two Giga-bit LAN ports

• Two EIDE Ultra DMA/100 bus master interfaces supporting one IDE (the blue

slot) and one Compact Flash card (the white slot)

• Two SGPIO (Serial General Purpose Input/Output) headers with support for

ESB2 SATA

• One ﬂ oppy port interface

• Two COM ports (1 header, 1 port)

• One EPP/ECP Parallel Port

• One VGA Port

• PS/2 mouse and PS/2 keyboard ports

• Up to ﬁ ve USB 2.0 (Universal Serial Bus) (2 ports, 3 Headers)

• ATI 16 MB ES1000 Graphic Controller

• Super I/O: Winbond W83627HF w/Hardware Monitor support: W83793,

HECETA

Other

• External modem ring-on

• Wake-on-LAN (WOL)

• Wake-on-Ring (WOR)

• Console redirection

• Onboard Fan Speed Control by Thermal Management via BIOS

CD/Diskette Utilities

• BIOS ﬂ ash upgrade utility and device drivers

Dimensions

• ATX Ext. 12" x 13.05" (304.8 x 331.5 mm)

1-7

X7DB3 User's Manual

J13

#2

J5 #6

PCI - EXP X8 SLOT

SEPC

PCI - EXP

PCI - X 133

PCI 3 3

PCI - EXP X8

PCI -EX

PROCESSOR#2

1333

1067/

/S

MT

PORT #4, 5

PORT #6, 7

P

X8

X4

PORT #0

X8

PORT #1, 2

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PORT PORT

PORT PORT #4 #3

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J9 #4

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FBD CHNL1

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F B D DI MM

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DDR

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PARALLEL

PORT

KUMERAN

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GI L GAL

FDD

SI O

W83627

HF

MS

KB

COM1

COM2

Block Diagram of the 5000P Chipset

Note: This is a general block diagram. Please see the previous Motherboard Features

pages for details on the features of each motherboard.

LPC

1-8

Chapter 1: Introduction

1-2 Chipset Overview

Built upon the functionality and the capability of the 5000P chipset, the X7DB3

motherboard provides the performance and feature set required for dual pro-

cessor-based servers with conﬁ guration options optimized for communications,

presentation, storage, computation and database applications. The 5000P chipset

supports single or dual 64-bit quad core/dual core processor(s) with front side bus

speeds of up to 1.333 GHz/1.066 GHz/677 MHz. The chipset consists of the 5000P

Memory Controller Hub (MCH), the Enterprise South Bridge 2 (ESB2), and the I/O

subsystem (PXH).

The 5000P MCH chipset is designed for symmetric multiprocessing across two inde-

pendent front side bus interfaces. Each front side bus uses a 64-bit wide, 1333 MHz

data bus that transfers data at 10.7 GB/sec. (for a total bandwidth of 21.3GB/sec.).

The MCH chipset connects up to eight Fully Buffered DIMM modules, providing

a total memory bandwidth of 32 GB/s for DDR2 533/667. The MCH chipset also

provides one x8 PCI-Express and one x4 ESI interfaces to the ESB2. In addition,

the 5000P chipset offers a wide range of RAS features, including memory interface

ECC, x4/x8 Single Device Data Correction, CRC, parity protection, memory mirror-

ing and memory sparing.

The Xeon Quad core/dual core Processor Features

Designed to be used with conjunction of the 5000P chipset, the Xeon quad core/dual

core Processor provides a feature set as follows:

The Xeon Quad core/dual core Processors

L1 Cache Size: Instruction Cache (32KB/16KB), Data Cache (32KB/24KB)•

L2 Cache Size: 4MB/2MB (per core)•

*Data Bus Transfer Rate: 8.5 GB/s•

Package: FC-LGA6/FC-LGA4, 771 Lands•

1-9

X7DB3 User's Manual

1-3 Special Features

Recovery from AC Power Loss

BIOS provides a setting for you to determine how the system will respond when

AC power is lost and then restored to the system. You can choose for the system

to remain powered off (in which case you must hit the power switch to turn it back

on), or for it to automatically return to power-on state, or you can also choose for

it to automatically return to the last state prior to power loss. See the Power Lost

Control setting in the Advanced BIOS Setup section (Boot Features) to change

this setting.

1-4 PC Health Monitoring

This section describes the PC health monitoring features of the X7DB3. All have

an onboard System Hardware Monitor chip that supports PC health monitoring. An

onboard voltage monitor will scan the following voltages continuously: +1.5V,+1.8V,

+3.3V, +5V, +12V, −12V, +3.3V Standby, and +5V standby. Once a voltage becomes

unstable, a warning is given or an error message is sent to the screen. Users can

adjust the voltage thresholds to deﬁ ne the sensitivity of the voltage monitor.

Fan Status Monitor with Firmware Control

The PC health monitor can check the RPM status of the cooling fans. The onboard

CPU and chassis fans are controlled by Thermal Management via BIOS (under the

Hardware Monitoring section in the Advanced BIOS Setup section.)

Environmental Temperature Control

The thermal control sensor monitors the CPU temperature in real time and will turn

on the thermal control fan whenever the CPU temperature exceeds a user-deﬁ ned

threshold. The overheat circuitry runs independently from the CPU. Once it detects

that the CPU temperature is too high, it will automatically turn on the thermal fan

control to prevent any overheat damage to the CPU. The onboard chassis thermal

circuitry can monitor the overall system temperature and alert users when the chas-

sis temperature is too high.

CPU Fan Auto-Off in Sleep Mode

The CPU fan activates when the power is turned on. It continues to operate when

the system enters Standby mode. When in sleep mode, the CPU will not run at full

power, thereby generating less heat.

1-10

Chapter 1: Introduction

System Resource Alert

This feature is available when used with Supero Doctor III in the Windows OS en-

vironment or used with Supero Doctor II in Linux. Supero Doctor is used to notify

the user of certain system events. For example, if the system is running low on

virtual memory and there is insufﬁ cient hard drive space for saving the data, you

can be alerted of the potential problem. You can also conﬁ gure Supero Doctor to

provide you with warnings when the system temperature goes beyond a pre-de-

ﬁ ned range.

1-5 ACPI Features

ACPI stands for Advanced Conﬁ guration and Power Interface. The ACPI speciﬁ ca-

tion deﬁ nes a ﬂ exible and abstract hardware interface that provides a standard

way to integrate power management features throughout a PC system, including

its hardware, operating system and application software. This enables the system

to automatically turn on and off peripherals such as CD-ROMs, network cards, hard

disk drives and printers. This also includes consumer devices connected to the PC

such as VCRs, TVs, telephones and stereos.

In addition to enabling operating system-directed power management, ACPI

provides a generic system event mechanism for Plug and Play and an operating

system-independent interface for conﬁ guration control. ACPI leverages the Plug

and Play BIOS data structures while providing a processor architecture-indepen-

dent implementation that is compatible with both Windows 2000 and Windows

Server 2003. This setting is also located in the Advanced BIOS Setup section

(Boot Features).

Slow Blinking LED for Suspend-State Indicator

When the CPU goes into a suspend state, the chassis power LED will start blinking

to indicate that the CPU is in suspend mode. When the user presses any key, the

CPU will wake-up and the LED will automatically stop blinking and remain on.

Main Switch Override Mechanism

When an ATX power supply is used, the power button can function as a system

suspend button to make the system enter a SoftOff state. The monitor will be

suspended and the hard drive will spin down. Pressing the power button again

will cause the whole system to wake-up. During the SoftOff state, the ATX power

supply provides power to keep the required circuitry in the system alive. In case

the system malfunctions and you want to turn off the power, just press and hold

the power button for 4 seconds. This option can be set in the Boot section of the

Advanced BIOS Setup routine.

1-11

X7DB3 User's Manual

External Modem Ring-On

Wake-up events can be triggered by a device such as the external modem ringing

when the system is in the SoftOff state. Note that external modem ring-on can only

be used with an ATX 2.01 (or above) compliant power supply.

Wake-On-LAN (WOL)

Wake-On-LAN is deﬁ ned as the ability of a management application to remotely

power up a computer that is powered off. Remote PC setup, up-dates and asset

tracking can occur after hours and on weekends so that daily LAN trafﬁ c is kept

to a minimum and users are not interrupted. The motherboard has a 3-pin header

(WOL) to connect to the 3-pin header on a Network Interface Card (NIC) that has

WOL capability. In addition, an onboard LAN controller can also support WOL

without any connection to the WOL header. The 3-pin WOL header is to be used

with a LAN add-on card only.

Note: Wake-On-LAN requires an ATX 2.01 (or above) compliant power supply.

1-6 Power Supply

As with all computer products, a stable power source is necessary for proper and

reliable operation. It is even more important for processors that have high CPU

clock rates.

The X7DB3 can only accommodate 24-pin ATX power supplies. Although most

power supplies generally meet the speciﬁ cations required by the CPU, some are

inadequate. In addition, the 12V 4-pin power supply - is also required to ensure

adequate power supply to the system. Also your power supply must supply 1.5A

for the Ethernet ports.

Note: The + 12V 8-pin Aux. Power Connector is always required. Failure to provide

this extra power will result in CPU PWR Failure. See Section 2-5 for details on

connecting the power supply.

It is strongly recommended that you use a high quality power supply that meets

ATX power supply Speciﬁ cation 2.02 or above. It must also be SSI compliant (info

at http://www.ssiforum.org/). Additionally, in areas where noisy power transmission

is present, you may choose to install a line ﬁ lter to shield the computer from noise.

It is recommended that you also install a power surge protector to help avoid prob-

lems caused by power surges.

1-7 Super I/O

The disk drive adapter functions of the Super I/O chip include a ﬂ oppy disk drive

controller that is compatible with industry standard 82077/765, a data separator,

1-12

Chapter 1: Introduction

write pre-compensation circuitry, decode logic, data rate selection, a clock generator,

drive interface control logic and interrupt and DMA logic. The wide range of functions

integrated onto the Super I/O greatly reduces the number of components required

for interfacing with ﬂ oppy disk drives. The Super I/O supports 360 K, 720 K, 1.2

M, 1.44 M or 2.88 M disk drives and data transfer rates of 250 Kb/s, 500 Kb/s or

1 Mb/s. It also provides two high-speed, 16550 compatible serial communication

ports (UARTs. Each UART includes a 16-byte send/receive FIFO, a programmable

baud rate generator, complete modem control capability and a processor interrupt

system. Both UARTs provide legacy speed with baud rate of up to 115.2 Kbps as

well as an advanced speed with baud rates of 250 K, 500 K, or 1 Mb/s, which sup-

port higher speed modems.

The Super I/O supports one PC-compatible printer port (SPP), Bi-directional Printer

Port (BPP), Enhanced Parallel Port (EPP) or Extended Capabilities Port (ECP).

The Super I/O provides functions that comply with ACPI (Advanced Conﬁ guration

and Power Interface), which includes support of legacy and ACPI power manage-

ment through an SMI or SCI function pin. It also features auto power management

to reduce power consumption.

1-13

X7DB3 User's Manual

Notes

1-14

Chapter 2: Installation

Chapter 2

Installation

2-1 Static-Sensitive Devices

Electro-Static-Discharge (ESD) can damage electronic com ponents. To prevent

damage to your system board, it is important to handle it very carefully. The following

measures are generally sufﬁ cient to protect your equipment from ESD.

Precautions

Use a grounded wrist strap designed to prevent static discharge.•

Touch a grounded metal object before removing the board from the antistatic •

bag.

Handle the board by its edges only; do not touch its components, peripheral

•

chips, memory modules or gold contacts.

When handling chips or modules, avoid touching their pins.

•

Put the motherboard and peripherals back into their antistatic bags when not •

in use.

For grounding purposes, make sure your computer chassis provides excellent

•

conductivity between the power supply, the case, the mounting fasteners and

the motherboard.

Use only the correct type of onboard CMOS battery as speciﬁ ed by the

•

manufacturer. Do not install the onboard battery upside down to avoid possible

explosion.

Unpacking

The motherboard is shipped in antistatic packaging to avoid static damage. When

unpacking the board, make sure the person handling it is static protected.

2-1

X7DB3 User's Manual

!

2-2 Processor and Heatsink Fan Installation

When handling the processor package, avoid placing

direct pressure on the label area of the fan.

Notes:

•

Always connect the power cord last and always remove it before adding, re-

moving or changing any hardware components. Make sure that you install the

processor into the CPU socket before you install the CPU heatsink.

Intel's boxed Xeon CPU package contains the CPU fan and heatsink assembly.

•

If you buy a CPU separately, make sure that you use only Intel-certiﬁ ed multi-

directional heatsink and fan.

Make sure to install the motherboard into the chassis before you install the CPU

•

heatsink and fan.)

When purchasing an LGA 771 CPU or when receiving a motherboard with an

•

LGA 771 CPU pre-installed, make sure that the CPU plastic cap is in place and

none of the CPU pins are bent; otherwise, contact the retailer immediately.

Refer to the MB Features Section for more details on CPU support.

•

Installation of the LGA771 Processor

1. Press the socket clip to release

the load plate, which covers the CPU

socket, from its locking position.

2. Gently lift the socket clip to open

the load plate.

Socket Clip

Load Plate

2-2

Chapter 2: Installation

!

3. Use your thumb and your index

ﬁ nger to hold the CPU at the North

Center Edge and the South Center

Edge of the CPU.

4. Align CPU Pin1 (the CPU corner

marked with a triangle) against the

socket corner that is marked with a

triangle cutout.

5. Align the CPU key that is the

semi-circle cutout below a gold dot

against the socket key, the notch on

the same side of the triangle cutout

on the socket.

6. Once aligned, carefully lower the

CPU straight down to the socket.

(Do not drop the CPU on the socke

or move the CPU horizontally or ver-

tically. Do not rub the CPU against

the surface or against any pins of the

socket to avoid damage to the CPU

or the socket.)

Socket Key

(Socket Notch)

CPU Key (semi-

circle cutout)

below the circle.

Corner with a

triangle cutout

North Center Edge

South Center Edge

gold dot

CPU Pin1

7. With the CPU inside the socket,

inspect the four corners of the CPU

to make sure that the CPU is prop-

erly installed.

8. Use your thumb to gently push the

socket clip down to the clip lock.

9. If the CPU is properly installed

into the socket, the plastic cap will

be automatically released from the

load plate when the clip is pushed in

the clip lock. Remove the plastic cap

from the motherboard.

(Warning: Please save the

plastic cap. The motherboard must

be shipped with the plastic cap

properly installed to protect the CPU

socket pins. Shipment without the

plastic cap properly installed will

cause damage to the socket pins.)

Socket clip

CPU in the CPU socket

Plastic cap

is released

from the

load plate

if the CPU

is properly

installed.

2-3

X7DB3 User's Manual

!

Heatsink Installation

CEK Heatsink Installation

1. Do not apply any thermal grease to

the heatsink or the CPU die-the required

amount has already been applied.

2. Place the heatsink on top of the

CPU so that the four mounting holes

are aligned with those on the retention

mechanism.

3. Screw in two diagonal screws (ie the

#1 and the #2 screws) until just snug (-do

not fully tighten the screws to avoid pos-

sible damage to the CPU.)

4. Finish the installation by fully tightening

all four screws.

CEK Passive Heatsink

Screw#1 Screw#2

Screw#1

Screw#4

To Un-install the Heatsink

Warning: We do not recommend

that the CPU or the heatsink be

removed. However, if you do need

to uninstall the heatsink, please

follow the instructions below to

uninstall the heatsink to prevent

damage done to the CPU or the

CPU socket.

2-4

Screw#3

Screw#2

1. Unscrew and remove the heatsink screws

from the motherboard in the sequence as show

in the picture on the right.

2. Hold the heatsink as shown in the picture

on the right and gently wriggle the heatsink to

loosen it from the CPU. (Do not use excessive

force when wriggling the heatsink!!)

3. Once the CPU is loosened, remove the

heatsink from the CPU socket.

4. Clean the surface of the CPU and the

heatsink to get rid of the old thermal grease.

Reapply the proper amount of thermal grease

on the surface before you re-install the CPU

and the heatsink.

Chapter 2: Installation

Mounting the Motherboard in the Chassis

All motherboards have standard mounting holes to ﬁ t different types of chas-

sis. Make sure that the locations of all the mounting holes for both motherboard

and chassis match. Make sure that the metal standoffs click in or are screwed in

tightly. Then, use a screwdriver to secure the motherboard onto the motherboard tray. (Note: some components are very close to the mounting holes. Please take

precautionary measures to prevent damage done to these components when you

install the motherboard to the chassis.)

2-5

X7DB3 User's Manual

2-3 Installing DIMMs

Note: Check the Super Micro web site for recommended memory modules.

CAUTION

Exercise extreme care when installing or removing DIMM

modules to prevent any possible damage. Also note that the

memory is interleaved to improve performance (see step 1).

DIMM Installation (See Figure 2-2)

1. Insert the desired number of DIMMs into the memory slots, starting with DIMM

#1A. The memory scheme is interleaved so you must install two modules at a

time, beginning with DIMM #1A, then DIMM #2A and so on. (Please see the

Memory Installation Table below.)

2. Insert each DIMM module vertically into its slot. Pay attention to the notch along

the bottom of the module to prevent inserting the DIMM module incorrectly.

3. Gently press down on the DIMM module until it snaps into place in the slot.

Repeat for all modules (see step 1 above).

Memory Support

The X7DB3 supports up to 32 GB fully buffered (FBD) ECC DDR2 533/667 in 8

DIMMs. Populating DIMM modules with pairs of memory modules of the same size

and same type will result in Interleaved Memory which will increase memory

performance. Note 1: Due to OS limitations, some operating systems may not show more than

4 GB of memory.

Optimized DIMM Population Configurations

Branch0 Branch1

Number of

DIMMs

2 DIMMs 1A ------ 2A ------ ------ ------ ------ -----4 DIMMs 1A ------ 2A ------ 3A ------ 4A -----6 DIMMs 1A 1B 2A 2B 3A ------ 4A -----8 DIMMs 1A 1B 2A 2B 3A 3B 4A 4B

Bank 1

(Channel 0)

Bank 2

(Channel 1)

Bank 3

(Channel 2)

Bank 4

(Channel 3)

(*Notes: i. DIMM slot# specified: DIMM slot to be populated; “---“: DIMM slot not to be populated. ii. Both FBD 533 MHz and 667MHz DIMMs are supported; however,

you need to use the memory modules of the same speed and of the same type on a

motherboard. iii. Interleaved memory is supported when pairs of DIMM modules are installed. To optimize memory performance, please install pairs of DIMMs in both Branch 0 and Branch 1. iv. For memory to work properly, you need to follow the

restrictions listed above. )

Note 2: Due to memory allocation to system devices, memory remaining available

for operational use will be reduced when 4 GB of RAM is used. The reduction in

memory availability is disproportional. (Refer to the following Memory Availability

Table for details.)

2-6

Possible System Memory Allocation & Availability

Chapter 2: Installation

System Device Size Physical Memory

Remaining (-Available) (4 GB Total System Memory)

Firmware Hub ﬂ ash memory (System

1 MB 3.99

BIOS)

Local APIC 4 KB 3.99

Area Reserved for the chipset 2 MB 3.99

I/O APIC (4 Kbytes) 4 KB 3.99

PCI Enumeration Area 1 256 MB 3.76

PCI Express (256 MB) 256 MB 3.51

PCI Enumeration Area 2 (if needed)

512 MB 3.01

-Aligned on 256-MB boundary-

VGA Memory 16 MB 2.85

TSEG 1 MB 2.84

Memory available to OS and other ap-

2.84

plications

Installing and Removing DIMMs

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DDR2 FBD

To Install: Insert module vertically and press down until it

snaps into place. Pay attention to the alignment notch at the bottom.

Top View of DDR2 FBD Slot

2-7

X7DB3 User's Manual

123

4

5

678

9

2-4 Control Panel Connectors/IO Ports

The I/O ports are color coded in conformance with the PC 99 speciﬁ cation. See

Figure 2-3 below for the colors and locations of the various I/O ports.

A. Back Panel Connectors/IO Ports

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Back Panel Connectors

1. Keyboard (Purple)

2. PS/2 Mouse (Green)

3. Back Panel USB Port 0

4. Back Panel USB Port 1

5. COM Port 1 (Turquoise)

6. VGA Port (Blue)

7. Parallel Port (Printer)

8. Gigabit LAN 1

9. Gigabit LAN 2

(*See Section 2-5 for details.)

2-8

Chapter 2: Installation

B. Front Control Panel

JF1 contains header pins for various buttons and indicators that are normally

located on a control panel at the front of the chassis. These connectors are de-

signed speciﬁ cally for use with Super Micro server chassis. See Figure 2-4 for the

descriptions of the various control panel buttons and LED indicators. Refer to the

following section for descriptions and pin deﬁ nitions.

JF1 Header Pins

1920

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PWR

Reset Button

Power Button

2-9

X7DB3 User's Manual

C. Front Control Panel Pin Deﬁ nitions

NMI Button

The non-maskable interrupt button

header is located on pins 19 and 20

of JF1. Refer to the table on the right

for pin deﬁ nitions.

Power LED

The Power LED connection is located

on pins 15 and 16 of JF1. Refer to the

table on the right for pin deﬁ nitions.

NMI Button

Pin Deﬁ nitions (JF1)

Pin# Deﬁ nition

19 Control

20 Ground

Power LED

Pin Deﬁ nitions (JF1)

Pin# Deﬁ nition

15 +5V

16 Ground

A. NMI

B. PWR LED

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2-10

Chapter 2: Installation

HDD LED

The HDD LED connection is located

on pins 13 and 14 of JF1. Attach the

hard drive LED cable here to display

disk activity (for any hard drives on

the system, including SAS, Serial ATA

and IDE). See the table on the right

for pin deﬁ nitions.

NIC1/NIC2 LED Indicators

The NIC (Network Interface Control-

ler) LED connection for GLAN port1 is

located on pins 11 and 12 of JF1 and

the LED connection for GLAN Port2

is on Pins 9 and 10. Attach the NIC

LED cables to display network activity.

Refer to the table on the right for pin

deﬁ nitions.

HDD LED

Pin Deﬁ nitions (JF1)

Pin# Deﬁ nition

13 +5V

14 HD Active

GLAN1/2 LED

Pin Deﬁ nitions (JF1)

Pin# Deﬁ nition

9/11 Vcc

10/12 Ground

A. HDD LED

B. NIC1 LED

C. NIC2 LED

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D

LE

P

B

S4-7 A S

S0-3

SA

3

A

F

a

n

4

OH/Fan Fail LED

Ground

Power LED

HDD LED

A

B

NIC1 LED

NIC2 LED

C

PWR Fail LED

X

Ground

1920

NMI

X

Vcc

Reset

Reset Button

Power Button

PWR

2

1

PSF

SMBPS

Fan7

2-11

X7DB3 User's Manual

Overheat/Fan Fail LED (OH)

Connect an LED to the OH/Fan Fail

connection on pins 7 and 8 of JF1 to

provide advanced warnings of chassis

overheating or fan failure. Refer to the

table on the right for pin deﬁ nitions.

Power Fail LED

The Power Fail LED connection is

located on pins 5 and 6 of JF1. Re-

fer to the table on the right for pin

deﬁ nitions.

OH/Fan Fail LED

Pin Deﬁ nitions (JF1)

Pin# Deﬁ nition

7 Vcc

8 Ground

OH/Fan Fail Indicator

Status

State Deﬁ nition

Off Normal

On Overheat

Flash-

Fan Fail

ing

PWR Fail LED

Pin Deﬁ nitions (JF1)

Pin# Deﬁ nition

5 Vcc

6 Ground

A. OH/Fan Fail LED

B. PWR Supply Fail

n

i

4-P

Fan5

6

Fan

R

W

M

US

COM

VGA

KB/

ouse

/1

B0

1

Port

Parrallel

JLAN1

GLAN1

GLAN2

S

UPER

l

S

A

VG

LR

TR

C

S

LAN

J

CTRLR

J

S

O

/

I

S

2

M

JCO

P

DIMM

D

I

M

DIMM

DI

M

DIMM

DI

M

DIMM

D

IMM

®

X7DB3

t7

o

SIMLP IPMI

G1

P

J

t6

o

l

S

PCI-Exp x8

t5

o

l

S

x8

-Ex p

PCI

4

t

o

l

S

PCI-Exp x4

D

W

J

t3

o

l

1

PL

2

L

P

t2

o

l

t1

o

l

z

H

M

3

1

X

-

I

C

P

J28 J27

z

H

M

3

1

X

-

I

C

P

R

JWO

z

H

M

0

1

X

-

I

C

P

24-

4

B (Ban k 4)

4

A (B a

3

B (Bank 3)

M

3

A (B a

2

B (Ba

M

2

A (B a

1B (B ank 1

1

A

SEPC

ttery

a

B

R

ZC

WR

P

X

T

A

n

i

P

Buzzer

nk

4

)

n

k

3

)

nk 2)

nk

2

)

(Ba

nk

1

)

l 50

Inte

B

h

t

Nor

S

O

I

B

JK

1

T

A

S

J3P

JAR

Core

ual

on D

Xe

1

U

P

C

Core

ual

D

n

o

Xe

2

U

P

0

idge

r

X

P

SMB

JL1

0

A

T

A

S

C

1

T

JB

SAS CTRLR Adaptec 9410W

J7

4

B

S

U

H

/3

SB2

U

4

5

A

T

A

S

WOL

2

3

A

T

A

S

1

Inte

South B

C

J

W

J

l ES B2

8-pinPWR

1 n a F

FP Control

2 n a F

SPK

PW LED

JP1

LE1

JOH1

F

an

3

n8

Fa

2 O

I P G

h

S

s

1 O

Fla

I

y

t

P G S

1

F

F1

S1

P

J

e

g

id

r

p

1

c

p

a

o

p

l

IDE

F

m o C

on

C

D

LE

P

B

S4-7 A S

S0-3

SA

3

A

JS

F

a

n

4

OH/Fan Fail LED

Ground

X

Power LED

HDD LED

NIC1 LED

NIC2 LED

A

B

PWR Fail LED

Ground

PSF

SMBPS

Fan7

1920

NMI

X

Vcc

Reset

Reset Button

Power Button

PWR

2

1

2-12

Reset Button

Chapter 2: Installation

The Reset Button connection is located

on pins 3 and 4 of JF1. Attach it to the

hardware reset switch on the computer

case. Refer to the table on the right for

pin deﬁ nitions.

Power Button

The Power Button connection is located

on pins 1 and 2 of JF1. Momentarily con-

tacting both pins will power on/off the sys-

tem. This button can also be conﬁ gured

to function as a suspend button (with a

setting in the BIOS - see Chapter 4). To

turn off the power when set to suspend

mode, press the button for at least 4

seconds. Refer to the table on the right

for pin deﬁ nitions.

Reset Button

Pin Deﬁ nitions (JF1)

Pin# Deﬁ nition

3 Reset

4 Ground

Power Button

Pin Deﬁ nitions (JF1)

Pin# Deﬁ nition

1 Signal

2 +3V Standby

A. Reset Button

B. PWR Button

Fan5

6

Fan

KB/

ouse

M

USB 0/1

1

COM

Port

Parrallel

JLAN1

VGA

GLAN1

GLAN2

S

UPER

t7

o

l

S

SIMLP IPMI

G1

P

J

t6

o

l

S

PCI-Exp x8

A

VG

LR

TR

C

t5

o

l

S

PCI

4

t

o

l

S

PCI-Exp x4

D

W

J

t3

o

l

S

-

I

C

P

LAN

1

PL

J

CTRLR

2

L

P

J

t2

o

l

S

-

I

C

P

O

/

I

S

t1

o

l

S

-

I

C

P

2

M

JCO

4-P P

DIMM

D

DIMM

DI

DIMM

D

®

X7DB3

x8

-Ex p

M

3

1

X

J28 J27

M

3

1

X

R

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M

0

1

X

n

i R

W

IM

M

IMM

z

H

z

H

Z

z

H

n

i

P

24-

4B (B ank 4)

4

A (B a

3B (B ank

3

A (B a

2B (B ank

2

A (B a

1B (B ank

1

A (B a

SEPC

ttery

a

B

R

C

WR

P

X

AT

Buzzer

nk

4

)

3)

n

k

3

)

2

)

nk

2

)

1)

nk

1

)

0

l 5

Inte

B

h

t

Nor

S

O

I

B

JK

1

T

A

S

J3P

JAR

Core

ual

on D

Xe

1

U

P

C

Core

ual

D

n

o

Xe

2

U

P

0

idge

r

X

P

SMB

JL1

0

A

T

A

S

C

1

T

JB

SAS CTRLR Adaptec 9410W

J7

4

B

S

U

H

/3

SB2

U

4

5

A

T

A

S

OL

W

3

2

A

T

A

S

1

e

Int

South B

C

J

W

J

l ES B2

8-pinPWR

1 n a F

FP Control

2 n a F

SPK

PW LED

JP1

LE1

JOH1

F

an

3

n8

Fa

2 O

I P

G

h

S

s

1

la

O

F

I

y

OH/Fan Fail LED

t

P

p

1

c

G

p

a

o

S

p

l

IDE

F

m

1

F

o

F1

C

S1

P

J

id

r

on

C

D

LE

P

B

S4-7 A S

e

g

S0-3

SA

3

A

JS

F

a

n

4

Ground

X

Power LED

HDD LED

NIC1 LED

NIC2 LED

PWR Fail LED

Ground

PSF

SMBPS

Fan7

1920

NMI

X

Vcc

Reset

A

Reset Button

B

Power Button

PWR

2

1

2-13

X7DB3 User's Manual

2-5 Connecting Cables

ATX Power Connector

There are a 24-pin main power sup-

ply connector(JPW1) and an 8-pin

CPU PWR connector (JPW3) on the

motherboard. These power connec-

tors meet the SSI EPS 12V speciﬁ ca-

tion. The 4-pin 12V PWR supply is

required to provide adequate power

to the system. See the table on the

right for pin deﬁ nitions. For the 8-pin

PWR (JPW3), please refer to the item

listed below.

Processor Power Connector

In addition to the Primary ATX power

connector (above), the 12V 8-pin CPU

PWR connector at JPW3 must also

be connected to your power supply.

See the table on the right for pin

deﬁ nitions.

KB

Mo

USB0

O

C

G

V

/

se

u

M1

Parrallel

JLAN1

A

GLAN1

GLAN2

CT

I/O

S

JCOM2

1

/

Port

CTRLR

A

L

S

GA

V

N

RL

Fan6

UPE R

lot7

S

lot6

S

lot5

S

lot4

S

t3

o

l

S

L1

P

J

R

L2

P

J

2

t

lo

S

lot1

S

Fan

SIMLP IPMI

1

G

P

J

PCI-Exp x8

C

P

PCI-Exp x4

WD

J

-

I

C

P

-

I

C

P

CI-

P

5

®

X7DB

p

x

I-E

3

13

X

8

J2 J27

3 M

13

X

R

JWO

00

1

X

C

in

P

-

4 PWR

DI

M

DIMM 4

DIMM 3

DIM

M

DIMM

D

IMM

D

IM

DIMM 1

8

x

z

MH

z

H

ZCR

MHz

M

24-Pi

4

B (Bank

A (B

B (

3A

(

2

B (Bank 2)

2

A (Ba

1

B (Bank 1)

A (Bank 1)

3

SEPC

ttery

Ba

ATX PW

n

a

n

B

ank 3

B

a

n

IOS

B

A

4)

k

4)

k

3)

k

2

R

Buzzer

)

00P

50

l

Inte

North Bridge

J

K

1

0

ATA

S

7

n

SMBPS

a

F

JAR

H

X

P

MB

S

J

L

1

ATA

S

1

T

B

J

7

J

ATA

S

T

A

S

PSF

J3P

Xeon Dual Core

C

n

eo

X

SAS CTRLR Adaptec 9410W

SB

U

USB2/

4

5

ATA

S

A2

A3

T

A

S

PU

D

4

ATX Power 24-pin Connector

Pin Deﬁ nitions

Pin# Deﬁ nition Pin # Deﬁ nition

13 +3.3V 1 +3.3V

14 -12V 2 +3.3V

15 COM 3 COM

16 PS_ON 4 +5V

17 COM 5 COM

18 COM 6 +5V

19 COM 7 COM

20 Res (NC) 8 PWR_OK

21 +5V 9 5VSB

22 +5V 10 +12V

23 +5V 11 +12V

24 COM 12 +3.3V

Required Connection

12V 4-pin Power Con-

nector

Pin Deﬁ nitions

Pins Deﬁ nition

1 and 2 Ground

3 and 4 +12V

Required Connection

12V 8-pin Power CPU

Connector

B

8-pinPWR

1

SPK

PW LED

LE1

l Cor e

a

u

2

PU

C

2

SGPIO 1

SGPIO

CF1

J

1

F

W

J

S1

P

J

l ES B 2

e

t

n

I

h Bridge

t

u

o

S

3

WOL

Fa

n3

an

F

lash

act F

Floppy

mp o C

o

C

LED

P

B

7

S4A S

3

S0

SA

SA3

J

Fa

n4

Pin Deﬁ nitions

Pins Deﬁ nition

1 n a

F

1 through 4 Ground

5 through 8 +12V

FP C ontrol

an2 F

A. 24-pin ATX PWR

B. 8-pin Processor PWR

JP1

C. 4-pin PWR

JOH1

8

1

IDE

n

2-14

Chapter 2: Installation

D

Universal Serial Bus (USB)

There are ﬁ ve USB 2.0 (Universal Se-

rial Bus) ports/headers on the moth-

erboard. Two of them are Back Panel

USB ports (USB#0/1:JUSB1), and

the other three are Front Panel USB

headers (USB#2/3:JUSB2, USB#4:

JUSB3). See the tables on the right

for pin deﬁ nitions.

Chassis Intrusion

A Chassis Intrusion header is located

at JL1 on the motherboard. Attach the

appropriate cable from the chassis to

inform you of a chassis intrusion when

the chassis is opened.

Back Panel USB

(USB0/1)

Pin# Deﬁ nitions

1 +5V

2 PO-

3 PO+

4 Ground

5 N/A

Front Panel USB

(USB2/3)

Pin# Deﬁ nition

1 +5V

2 Data-

3 Data+

4 Ground

5NA

Front Panel USB

Pin Deﬁ nitions (USB4)

USB4 Pin # Deﬁ nition

USB5 Pin # Deﬁ nition

1 +5V 1 +5V

2 PO- 2 PO-

3 PO+ 3 PO+

4 Ground 4 Ground

5 Key 5 No connection

Chassis Intrusion

Pin Deﬁ nitions (JL1)

Pin# Deﬁ nition

1 Intrusion Input

2 Ground

KB

Mo

USB0

O

C

G

V

/ se

u

M1

Parrallel

JLAN1

A

GLAN1

GLAN2

C

I/O

S

JCOM2

/

Port

L

1

S

V

CTRLR

N

A

RL

T

GA

F

A

UPE R

lot7

S

lot6

S

lot5

S

lot4

S

3

t

o

l

S

JPL1

R

L2

P

J

2

t

lo

S

lot1

S

Fan

an6

G

P

J

PCI-Exp x8

P

WD

J

C

P

C

P

CI-

P

5

®

X7DB

SIMLP IPMI

1

x

p

x

I-E

C

PCI-Exp x4

3

13

X

-

I

8

J2 J27

3 M

13

X

-

I

R

JWO

00

1

X

in

P

-

4 PWR

DI

M

DIMM 4

DIMM 3

DIM

M

DIMM

D

IMM

D

IM

M

DIMM 1

3

8

z

MH

z

H

ZCR

MHz

24-Pi

4

B (Bank

A (B

B (

3A

(

2

B (Bank 2)

2

A (Ba

1

B (Bank 1

A (Bank 1)

SEPC

ttery

Ba

ATX PW

n

a

B

ank 3)

B

a

B

n

IOS

k

4)

3)

2

N

R

Buzzer

)

50

l

Inte

orth Bridge

J

K

1

ATA

S

A. Backpanel USB 0-1

7

PSF

n

SMBPS

a

F

JAR

J3P

Xeon Dual Core

1

PU

C

l Cor e

a

u

D

n

eo

X

2

PU

00P

B

J

7

J

H

X

P

MB

S

ATA

S

J

L

1

A

S

0

1

ATA

S

C

1

T

SAS CTRLR Adaptec 9410W

C

4

SB

U

USB2/

4

5

ATA

S

A2

A3

T

A

S

l ES B 2

e

t

n

I

t

u

o

S

3

B

WOL

CF1

J

1

F

W

J

P

J

h Bridge

8-pinPWR

LE1

Fa

F

2

SGPIO

ash

1

l

act F

SGPIO

Floppy

mp o C

S1

C

LED

P

B

7

S4A S

3

S0

SA

SA3

J

Fa

n4

B. Front Panel USB 2-3

1 n a F

C. Front Panel USB 4

D. Chassis Intrusion

FP C ontrol

an2 F

SPK

PW LED

JP1

JOH1

n3

8

an

1 E

ID

n

o

2-15

X7DB3 User's Manual

G

F

E

D

H

I

Fan Headers

The X7DB3 has six chassis/system fan head-

ers (Fan1 to Fan6) and two CPU Fans (Fan7

and Fan8). (*Note: Fans#1-4 are 3-pin fans.

Fans#5-8 are 4-pin fans. However, Pins 1-3

of the fan headers are backward compatible

with the traditional 3-pin fans.) See the table on

the right for pin deﬁ nitions. (*The onboard fan

speeds are controlled by Thermal Management

under Hardware Monitoring in the Advanced

Setting in the BIOS

. Note: Default: Disabled,

When using Thermal Management setting,

please use all 3-pin fans or all 4-pin fans on

the motherboard.)

Keylock

The keyboard lock connection is designated

JK1. Utilizing this header allows you to inhibit

any actions made on the keyboard, effectively

"locking" it.

Fan Header

Pin Deﬁ nitions (Fan1-8)

Pin# Deﬁ nition

1 Ground

2 +12V

3 Tachometer

4 PWR Modulation

Keylock

Pin Deﬁ nitions

Pin# Deﬁ nition

1 Ground

2 Keylock R-N

KB

Mo

USB0

COM1

G

V

/

se

u

Parrallel

JLAN1

A

GLAN1

GLAN2

CTR

I/O

S

JCOM2

1

/

Port

CTRLR

A

L

S

GA

V

N

L

F

UPE R

lot7

S

lot6

S

lot5

S

lot4

S

3

t

o

l

S

L1

P

J

R

L2

P

J

2

t

lo

S

lot1

S

Fan

an6

SIMLP IPMI

G

P

J

PCI-Exp x8

P

WD

J

C

P

C

P

CI-

P

4

5

PWR

DIMM

DIMM 4

DIMM 3

D

DIMM

D

DIMM 1

®

X7DB

1

x

p

x

I-E

C

PCI-Exp x4

3

13

X

-

I

8

J2 J27

3 M

13

X

-

I

JWOR

00

1

X

-

MH

M

in

P

I

M

IMM

IM

8

z

H

Hz

24-Pi

4

B (Ba

A (B

B (Bank 3

M

3A

2

B (Ba

2

A (Ba

M

1

B (Bank 1)

A (Ban

3

SEPC

ttery

Ba

ZCR

(

ATX PW

n

a

B

a

B

nk 4)

n

k

4)

n

k

3)

nk 2)

n

k

2

k

1)

IOS

R

)

50

l

Inte

orth Bridge

N

J

K1

AT

S

Buzzer

00P

A0

7

PSF

n

SMBPS

a

F

JAR

J3P

8-pinPWR

Xeon Dual Core

1

PU

C

LE1

e

r

l Co

a

eon Du

X

2

PU

C

2

SGPIO

n

I

S

e

t

u

o

CF1

J

F

W

J

l ES B 2

h Bridge

t

1

SGPIO

1

S1

P

T1

B

J

H

PX

MB

S

J

L

1

A1

AT

S

SAS CTRLR Adaptec 9410W

J7

4

SB

U

3

/

2

B

US

4

5

ATA

S

WOL

ATA3

ATA2

S

F

a

an

F

ash

l

act F

Floppy

mp o C

PLEDC

B

7

S4A S

3

S0

SA

SA3

J

Fa

n4

A. Fan 1

1 n a

A

F

B. Fan 2

C. Fan 3

FP C ontrol

D. Fan 4

B

Fan2

SPK

E. Fan 5

PW LED

F. Fan 6

JP1

G. Fan 7 (CPU Fan 1)

JOH1

H. Fan 8 (CPU Fan 2)

n3

C

I. Keylock

8

1 E

ID

n

o

2-16

Chapter 2: Installation

ATX PS/2 Keyboard and PS/2 Mouse Ports

The ATX PS/2 keyboard and the PS/2

mouse are located at JKM1. See the

table on the right for pin deﬁ nitions.

(The mouse port is above the key-

board port. See the table on the right

for pin deﬁ nitions.)

Serial Ports

COM1 is a connector located on the

IO Backpanel and COM2 is a header

located at JCOM2. See the table on

the right for pin deﬁ nitions.

PS/2 Keyboard and

Mouse Port Pin

Deﬁ nitions

Pin# Deﬁ nition

1 Data

2NC

3 Ground

4 VCC

5 Clock

6NC

Serial Port Pin Deﬁ nitions

(COM1/COM2)

Pin # Deﬁ nition Pin # Deﬁ nition

1 CD 6 DSR

2RD 7RTS

3 TD 8 CTS

4 DTR 9 RI

5 Ground 10 NC

KB

Mo

USB0

C

G

V

u

O

Parrallel

A

GLAN1

GLAN2

JCOM2

/

se

M1

JLAN1

CT

I/O

S

1

/

Port

CTRLR

A

L

A

B

S

GA

V

N

RL

an6

F

UPE R

lot7

S

lot6

S

lot5

S

lot4

S

3

t

o

l

S

JPL1

R

L2

P

J

2

t

lo

S

lot1

S

C

Fan

SIMLP IPMI

1

G

P

J

PCI-Exp x8

C

P

PCI-Exp x4

WD

J

-

I

C

P

-

I

C

P

CI-

P

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(Pin 10 is available on COM2 only. NC: No Connection.)

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PSF

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S

A2

A3

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A

S

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l ES B 2

e

t

n

I

t

u

o

S

3

WOL

CF1

1

F

W

J

S1

P

J

h Bridge

8-pinPWR

SPK

PW LED

LE1

Fa

n3

an

F

GPIO2

h

S

as

l

GPIO1

act F

oppy

S

p

l F

m o C

o

C

LED

P

B

7

SAS4-

3

S0A S

SA3

J

Fa

n4

A. Keyboard/Mouse

1 n a F

B. COM1

C. COM2

FP C ontrol

an2 F

JP1

JOH1

8

1 E

ID

n

2-17

X7DB3 User's Manual

Wake-On-Ring

The Wake-On-Ring header is desig-

nated JWOR. This function allows

your computer to receive and be

awakened by an incoming call to the

modem when the system is in the sus-

pend state. See the table on the right

for pin deﬁ nitions. You must have a

Wake-On-Ring card and cable to use

this feature.

Wake-On-LAN

The Wake-On-LAN header is located

at JWOL on the motherboard. See the

table on the right for pin deﬁ nitions.

(You must also have a LAN card with

a Wake-On-LAN connector and cable

to use this feature.)

Wake-On-Ring Pin Deﬁ nitions

(JWOR)

Pin# Deﬁ nition

1 Ground

2 Wake-up

Wake-On-LAN

Pin Deﬁ nitions

(JWOL)

Pin# Deﬁ nition

1 +5V Standby

2 Ground

3 Wake-up

KB

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3

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Bridge

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8-pinPWR

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FP C ontrol

2

Fan

SPK

PW LED

JP1

LE1

JOH1

Fa

n3

an8

F

2

SGPIO

ash

1

l

1 E

act F

SGPIO

1

ID

Floppy

mp o C

n

o

C

PLED

B

7

S4A S

3

S0

SA

3

A

S

J

Fa

n4

A. WOR

B. WOL

2-18

GLAN 1/2 (Giga-bit Ethernet Ports)

Chapter 2: Installation

Two G-bit Ethernet ports are desig-

nated JLAN1 and JLAN2 on the IO

backplane. This port accepts RJ45

type cables.

Power LED/Speaker

On the JD1 header, pins 1-3 are for

a power LED and pins 4-7 are for the

speaker. See the table on the right

for speaker pin definitions. Note:

The speaker connector pins are for

use with an external speaker. If you

wish to use the onboard speaker, you

should close pins 6-7 with a jumper.

GLAN1

Speaker Connector

Pin Setting Deﬁ nition

Pins 6-7 Internal Speaker

Pins 4-7 External Speaker

GLAN2

JLAN1

S

A

UPE R

®

X7DB

A. GLAN1/2

B. PWR LED/Speaker

B

3

2-19

X7DB3 User's Manual

Power Fault (PWR Supply Failure)

Connect a cable from your power

supply to the Power Fail (PSF) header

(JP3) to provide warnings of power

supply failure. This warning signal is

passed through the PWR_LED pin

to indicate of a power failure on the

chassis. See the table on the right for

pin deﬁ nitions.

Alarm Reset

PWR Supply Fail LED

Pin Deﬁ nitions

Pin# Deﬁ nition

1 PWR 1: Fail

2 PWR 2: Fail

3 PWR 3: Fail

4 Signal: Alarm Reset

Note: This feature is only available when using

Super Micro redundant power supplies.

If three power supplies are installed

and Alarm Reset (JAR) is enabled, the

system will notify you when any of the

three power modules fails. Connect

JAR to a micro-switch to enable you

to turn off the alarm that is activated

when a power module fails. See the

table on the right for pin deﬁ nitions.

in

P

-

4

5

n

a

KB

Mo

USB0/1

O

C

A

G

V

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/ se

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Port

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Alarm Reset

Pin Setting Deﬁ nition

Pin 1 Ground

Pin 2 +5V

8-pinPWR

LE1

ore

C

2 O

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SGP 1 O

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CF1

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1

JWF

JPS1

l ES B 2

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t

u

o

S

Fa

h las

py p

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o

p

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m o C

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B

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3

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A

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Fa

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2 n a F

SPK

PW LED

JP1

JOH1

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8

an

F

1 E

ID

n

o

C

A. Power Fault

B. Alarm Reset

2-20

Chapter 2: Installation

Overheat LED/Fan Fail (JOH1)

The JOH1 header is used to connect

an LED to provide warnings of chas-

sis overheating. This LED will blink

to indicate a fan failure. Refer to the

table on right for pin deﬁ nitions.

SMB

A System Management Bus header is

located at J18. Connect the appropri-

ate cable here to utilize SMB on your

system.

Overheat LED

Pin Deﬁ nitions

Pin# Deﬁ nition

1 5vDC

2 OH Active

OH/Fan Fail LED

State Message

Solid Overheat

Blinking Fan Fail

SMB Header

Pin Deﬁ nitions

Pin# Deﬁ nition

1 Data

2 Ground

3 Clock

4 No Connection

KB

Mo

USB0

O

C

G

V

/

se

u

1

/

M1

Port

Parrallel

JLAN1

A

GLAN1

GLAN2

L

C

I/O

S

JCOM2

S

UPE R

GA

V

R

TRL

C

N

A

R

L

R

T

in

P

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5

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an6

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mp o C

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o

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S4A S

3

S0

SA

SA3

J

Fa

n4

A. OH/Fan Fail LED

1 n a F

B. SMB

FP C ontrol

n2 a F

JP1

A

JOH1

8

2-21

X7DB3 User's Manual

Power SMB (I2 C) Connector

Power SMB (I2 C) Connector (J17)

monitors the status of PWR supply,

fan and system temperature. See the

table on the right for pin deﬁ nitions.

VGA Connector

A VGA connector (JG1) is located next

to COM1 port on the IO backplane.

Refer to the board layout below for

the location.

PWR SMB

Pin Deﬁ nitions

Pin# Deﬁ nition

1 Clock

2 Data

3 PWR Fail

4 Ground

5 +3.3V

KB

u

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USB0/1

M1

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Parrallel

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GLAN1

GLAN2

S

J

/

se

Port

JLAN1

L

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I/O

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S

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A

R

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lot4

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t

lo

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DIMM 4

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J7

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P

B

M

S

ATA

S

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1

0

ATA

S

C

2

SGPIO

T1

SAS CTRLR Adaptec 9410W

4

SB

U

3

USB2/

4

5

ATA

S

WOL

A2

A3

AT

S

1

SGPIO

CF1

J

1

JWF

JPS1

l ES B 2

nte

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Bridge

h

t

u

o

S

Fa

an

F

lash

act F

Floppy

mp o C

o

C

D

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B

7

S4A S

3

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SA

3

A

S

J

Fa

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1 n a F

FP C ontrol

an2 F

JP1

JOH1

n3

8

1 E

ID

n

A. PWR SMB

B. VGA

2-22

Compact Flash Card PWR Connector

A Compact Flash Card Power

Connector is located at JWF1. For the

Compact Flash Card or the Compact

Flash Jumper (JCF1) to work properly,

you will need to connect the Compact

Flash Card power cable to JWF1 ﬁ rst.

Refer to the board layout below for

the location.

Chapter 2: Installation

Compact Flash Card PWR

Connector

Jumper Deﬁ nition

On Compact Flash

Power On

Off Compact Flash

Power Off

SGPIO Headers

There are two SGPIO (Serial General

Purpose Input/Output) headers (J29,

J30) located on the motherboard.

These headers support serial link

interfaces for the onboard ESB2 SATA

connectors. See the table on the right

for pin deﬁ nitions. Refer to the board

layout below for the location.

JLAN1

PWR SMB

Pin Deﬁ nitions

Pin# Deﬁ nition Pin Deﬁ nition

1 *NC 2 *NC

3 Out 4 *NC

5 Ground 6 Load

7 *NC 8 Clock

Note: NC= No Connections

A. Compact Flash PWR

B. SGPIO1

C. SGPIO2

®

3

S

UPE R

X7DB

C

B

A

2-23

X7DB3 User's Manual

Connector

Pins

Jumper

Cap

Setting

2-6 Jumper Settings

Explanation of Jumpers

To modify the operation of the mother-

board, jumpers can be used to choose

between optional settings. Jumpers

create shorts between two pins to

change the function of the connector.

Pin 1 is identiﬁ ed with a square solder

pad on the printed circuit board. See

the motherboard layout pages for

jumper locations. Note: On two pin jumpers, "Closed"

means the jumper is on and "Open"

means the jumper is off the pins.

GLAN Enable/Disable

JPL1/JPL2 enable or disable the

GLAN Port1/GLAN Port2 on the moth-

erboard. See the table on the right for

jumper settings. The default setting

is enabled.

3 2 1

Pin 1-2 short

GLAN Enable

Pin# Deﬁ nition

1-2 Enabled (*default)

2-3 Disabled

KB

u

Mo

USB0/1

M1

O

C

Parrallel

A

G

V

GLAN1

GLAN2

S

J

/

se

JLAN1

I

C

Port

CTRLR

L

CTR

/

O

S

UPE R

GA

V

N

A

R

L

O

2

M

in

P

-

4

5

n

a

F

6

Fan

PWR

DIMM 4

DIMM 3

DIMM

D

IMM

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®

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lot6

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t

lo

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P

L1

P

J

L2

P

J

2

t

lo

S

P

lot1

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P

z

H

3 M

13

X

-

I

C

A

J28 J27

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H

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3

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M

00

1

X

CI-

B (Bank 4)

A (Ban

B

A

2

B (Bank

2

A (Ba

B (Bank 1

A (Ban

SEPC

ttery

Ba

ZCR

24-Pi

(

n

(

B

ATX PWR

k

4)

ank 3)

a

n

k

3)

2

n

k

2)

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1

)

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N

Buzzer

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50

l

orth Bridge

J

K1

0

ATA

S

7

PSF

n

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J3P

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1

PU

C

LE1

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al

u

D

n

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2

PU

C

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I

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1

T

B

J

H

X

P

B

M

S

J

L

1

ATA

S

SAS CTRLR Adaptec 9410W

7

J

4

SB

U

3

USB2/

4

5

ATA

S

WOL

A2

A3

AT

S

I

SGP

CF1

J

1

JWF

JPS1

l ES B 2

nte

I

Bridge

h

t

u

o

S

Fa

F

h as

l

py p

act F

o

p

Fl

m o C

C

PLED

B

4-7 S

SA

3

SAS0-

3

A

S

J

Fa

n4

A. GLAN Port1 Enable

1 n a F

B. GLAN Port2 Enable

FP C ontrol

2 n a F

SPK

PW LED

JP1

JOH1

n3

8

an

1 E D

I

n

o

2-24

Chapter 2: Installation

CMOS Clear

JBT1 is used to clear CMOS. Instead of pins, this "jumper" consists of contact

pads to prevent the accidental clearing of CMOS. To clear CMOS, use a metal

object such as a small screwdriver to touch both pads at the same time to short

the connection. Always remove the AC power cord from the system before clearing

CMOS. Note: For an ATX power supply, you must completely shut down the system,

remove the AC power cord and then short JBT1 to clear CMOS.

Watch Dog Enable/Disable

Watch Dog is a system monitor that can

reboot the system when a software ap-

plication hangs. Close pins 1-2 to re-

set the system if an application hangs.

Close pins 2-3 to generate a non-mask-

able interrupt signal for the application

that hangs. See the table on the right for

jumper settings. Watch Dog must also

be enabled in the BIOS.

in

P

-

4

5

KB

Mo

USB0

O

C

G

V

/ se

u

M1

Parrallel

JLAN1

A

GLAN1

GLAN2

C

I/O

S

JCOM2

1

/

Port

S

GA

V

TRL

C

N

A

L

R

L

R

T

an6

F

UPE R

lot7

S

J

lot6

S

R

lot5

S

lot4

S

3

t

o

l

S

L1

P

J

L2

P

J

2

t

lo

S

lot1

S

Fan

®

X7DB

SIML P IP MI

1

G

P

PCI-Exp x8

I-E

C

P

PCI-Exp x4

B

D

W

J

13

X

-

I

C

P

J2 J27

X

-

I

C

P

JWO

X

CI-

P

x

p

x

3

8

3 M

13

R

00

1

PWR

DI

M

DIMM 4

DIMM 3

DIM

M

DIMM

D

IMM

D

IM

M

DIMM 1

8

z

H

M

z

H

ZCR

Hz

M

24-Pi

4

B (Bank

A (B

B (

3A

(

2

B (Bank 2)

2

A (Ba

1

B (Bank 1)

A (Ban

3

SEPC

ttery

Ba

ATX PW

n

a

n

B

ank 3)

B

a

B

R

4)

k

4)

n

k

3)

n

k

2

k

1)

Inte

N

IOS

Buzzer

)

00P

50

l

orth Bridge

A

J

K1

0

ATA

S

7

PSF

n

SMBPS

a

F

MB

S

J3P

JAR

T1

B

J

J7

H

X

P

4

ATA

S

J

L

1

A2

T

A

S

1

ATA

S

Xeon Dual Core

1

PU

C

l Cor e

a

u

D

n

eo

X

2

PU

C

SAS CTRLR Adaptec 9410W

4

SB

U

3

USB2/

5

ATA

S

WOL

A3

T

A

S

I

S

n

o

e

t

u

l ES B 2

t

Watch Dog

Jumper Settings (JWD)

Jumper Setting Deﬁ nition

Pins 1-2 Reset

Pins 2-3 NMI

Open Disabled

8-pinPWR

Fan1

FP C ontrol

2 n a F

SPK

PW LED

JP1

LE1

JOH1

Fa

n3

8

an

F

2

h

SGPIO

s

1

la

py

1 E

act F

CF1

J

1

F

W

J

S1

P

J

h Bridge

SGPIO

ID

Flop

mp o C

n

o

C

PLED

B

7

S4

SA

3

S0

SA

SA3

J

Fa

n4

(*default)

A. Clear CMOS

B. Watch Dog Enable

2-25

X7DB3 User's Manual

SAS Controller Enable/Disable

JPS1 enables or disables the AIC

9410W Adaptec SAS Controller on the

motherboard. See the table on the right

for jumper settings. The default setting

is enabled.

VGA Enable/Disable

JPG1 allows you to enable or disable the

VGA port. The default position is on pins

1 and 2 to enable VGA. See the table on

the right for jumper settings.

SAS Controller Enable

Jumper Settings

Jumper Setting Deﬁ nition

Pins 1-2 Enabled

(*default)

Pins 2-3 Disabled

VGA Enable/Disable

Jumper Settings (JPG1)

Jumper Setting Deﬁ nition

Pins 1-2 Enabled

Pins 2-3 Disabled

KB

Mo

USB0

O

C

G

V

/

se

u

M1

Parrallel

JLAN1

A

GLAN1

GLAN2

CT

I/O

S

JCOM2

1

/

Port

CTRLR

A

L

S

GA

V

N

RL

an6

F

UPE R

lot7

S

lot6

S

lot5

S

lot4

S

3

t

o

l

S

JPL1

R

L2

P

J

2

t

lo

S

lot1

S

an

F

®

SIMLP IPMI

1

G

P

J

PCI-Exp x8

I-E

C

P

PCI-Exp x4

WD

J

X

-

I

C

P

X

-

I

C

P

JWO

X

CI-

P

4

5

PWR

DI

DIMM 4

DIMM 3

DIM

DIMM

D

DIMM 1

X7DB

B

x

p

x

3

13

8

J2 J27

3 M

13

R

00

1

P

-

M

IMM

IM

8

MH

H

Hz

M

in

M

z

4

M

3A

2

M

1

3

SEPC

ZCR

Ba

ATX PW

n

24-Pi

B (Bank

4)

A (B

a

n

k

4)

B (

B

a

nk 3)

(

B

a

n

k

3)

B (Bank 2)

A (Ba

n

k

B (Bank 1)

A (Bank 1)

ttery

IOS

B

R

2

)

Inte

North Bridge

S

l

J

50

ATA

K

Buzzer

00P

1

7

PSF

n

SMBPS

a

F

JAR

J3P

8-pinPWR

1

A. SAS Enable

n a

F

B. VGA Enabled

Xeon Dual Core

1

PU

C

l Cor e

a

u

D

n

eo

X

2

PU

C

2

SGPIO

I

S

t

n

o

J J

l ES B 2

e

h Bridge

t

u

CF1 W

1

SGPIO

1

F

A

S1

P

J

1

T

B

J

H

X

P

MB

S

J

L

1

0

1

ATA

S

SAS CTRLR Adaptec 9410W

7

J

4

SB

U

3

USB2/

4

5

ATA

S

WOL

A2

A3

T

A

S

FP C ontrol

Fan2

SPK

PW LED

JP1

LE1

JOH1

Fa

n3

8

an

F

lash

1 E

act F

ID

Floppy

mp o C

n

o

C

LED

P

B

7

S4A S

3

S0

SA

SA3

J

Fa

n4

2-26

Chapter 2: Installation

3rd PWR Supply PWR Fault Detect J3P)

The system can notify you in the event

of a power supply failure. This feature is

available when three power supply units

are installed in the chassis with one act-

ing as a backup. If you only have one

or two power supply units installed, you

should disable this (the default setting)

with J3P to prevent false alarms.

3rd PWR Supply PWR Fault

Jumper Settings

Jumper Setting Deﬁ nition

Closed Enabled

Open Disabled (*Default)

KB

Mo

USB0

O

C

G

V

/

se

u

/

M1

Parrallel

JLAN1

A

GLAN1

GLAN2

L

CT

I/O

S

JCOM2

1

Port

V

CTRLR

A

S

GA

N

RL

an6

F

UPE R

lot7

S

lot6

S

lot5

S

lot4

S

3

t

o

l

S

JPL1

R

L2

P

J

2

t

lo

S

lot1

S

Fan

®

SIMLP IPMI

1

G

P

J

PCI-Exp x8

I-E

C

P

PCI-Exp x4

WD

J

X

-

I

C

P

X

-

I

C

P

JWO

X

CI-

P

5

DI

DIMM 4

X7DB

x

p

x

3

13

8

J2 J27

3 M

13

R

00

1

in

P

-

4 PWR

M

4

DIMM 3

DIM

M

3A

DIMM

2

D

IMM

2

D

IM

M

1

DIMM 1

3

8

z

MH

z

H

ZCR

Hz

M

n

24-Pi

B (Ba

A (B

B (

B

(

B

B (Bank 2)

A (Ba

B (Bank 1)

A (Bank 1)

SEPC

ttery

Ba

ATX PW

nk 4)

a

n

k

4)

ank 3)

a

n

k

3)

n

k

2

IOS

B

R

)

50

l

Inte

orth Bridge

N

J

K

ATA

S

Buzzer

00P

1

0

7

PSF

n

SMBPS

a

F

JAR

J3P

A

Xeon Dual Core

1

PU

C

l Cor e

a

u

D

n

eo

X

2

PU

C

1

T

B

J

H

X

P

MB

S

J

L

1

ATA

S

SAS CTRLR Adaptec 9410W

7

J

e

t

n

I

4

SB

U

USB2/

4

ATA

S

A2

A3

T

A

S

u

o

S

3

5

WOL

CF1

J

1

F

W

J

P

J

l ES B 2

h Bridge

t

8-pinPWR

1 n a F

FP C ontrol

n2 a F

SPK

PW LED

JP1

LE1

JOH1

Fa

n3

8

an

F

2

SGPIO

ash

1

l

1 E

act F

SGPIO

S1

ID

Floppy

mp o C

n

o

C

LED

P

B

7

S4A S

3

S0

SA

SA3

J

Fa

n4

A. 3rd PWR Fail

2-27

X7DB3 User's Manual

Compact Flash Master/Slave Select

A Compact Flash Master (Primary)/Slave

(Secondary) Select Jumper is located

at JCF1. Close this jumper to enable

Compact Flash Card. For the Compact

Flash Card or the Compact Flash Jumper

(JCF1) to work properly, you will need to

connect the Compact Flash Card power

cable to JWF1 ﬁ rst. Refer to the board

layout below for the location.

I2C Bus to PCI-X/PCI-Exp. Slots

Jumpers J27, J28 allow you to connect

the System Management Bus (I PCI-X/PCI-E slots. The default setting

is "Open" to disable the connection.

See the table on the right for jumper

settings.

2

C) to

Compact Flash Card Master/

Slave Select

Jumper Deﬁ nition

Open Slave (Secondary)

Closed Master (Primary)

I2C to PCI-S/PCI/Exp

Jumper Settings

Jumper Setting Deﬁ nition

Closed Enabled

Open Disabled (*Default)

KB

u

Mo

USB0/1

M1

O

C

Parrallel

A

G

V

GLAN1

GLAN2

J

/

se

Port

JLAN1

L

C

I/O

S

O

C

S

GA

V

CTRLR

N

A

RL

T

M

R

2

an6

F

UPE R

lot7

S

J

lot6

S

lot5

S

lot4

S

3

t

lo

S

L1

JP

L2

P

J

2

t

lo

S

lot1

S

5

an

F

®

X7D

SIMLP IPMI

1

G

P

PCI-Exp x8

Exp x8

I-

C

P

PCI-Exp x4

WD

J

13

X

-

I

C

P

J28 J27

13

X

-

I

C

P

JW

1

X

CI-

P

4 PWR

D

DIMM 4

DIMM 3

DIMM

D

DIMM 1

3 M

R

O

M

00

in

P

-

IMM 4

IMM

B3

z

H

B

z

H

ZCR

Hz

24-Pi

B (Bank 4

A (Ban

B

(

B

A

(

B

2

B (Bank 2)

2

A (Ba

B (Bank 1

A (Ban

SEPC

ttery

Ba

ATX PW

n

k

ank 3)

a

n

IOS

B

4)

k

3)

k

2

k

1)

R

)

50

l

Inte

orth Bridge

N

J

K

ATA

S

Buzzer

00P

1

7

PSF

n

SMBPS

a

F

JAR

J3P

8-pinPWR

Xeon Dual Core

1

PU

C

LE1

l Cor e

a

Du

n

eo

X

2

PU

C

2

SGPIO 1

1

ridge

lash

act F

SGPIO

Floppy

mp o C

PLED

B

7

S4A S

3

S0

SA

SA3

J

Fa

1

T

B

J

PXH

B

M

S

J

L

1

0

ATA

S

SAS CTRLR Adaptec 9410W

J7

SB

U

USB2/

4

5

ATA

S

A2

A3

T

A

S

A

CF1

J JWF

JPS1

l ES B 2

nte

I

4

3

WOL

B

h

t

u

o

S

A. Compact Flash Master/

1 n a

Slave Select

F

B. SMBus to PCI slots

FP C ontrol

Fan2

SPK

PW LED

JP1

JOH1

Fa

n3

an8

F

1 E

ID

n

o

C

n4

2-28

Chapter 2: Installation

2-7 Onboard Indicators

GLAN LEDs

There are two GLAN ports on the moth-

erboard. Each Gigabit Ethernet LAN port

has two LEDs. The yellow LED indicates

activity, while the power LED may be

green, orange or off to indicate the speed

of the connection. See the tables at right

for more information.

Onboard Power LED

There is an Onboard Power LED (LE1)

located on the motherboard. When LE1 is

off, the system is off. When the green light

is on, the system is on. When the yellow

light is on, the system is off, but the AC

power cable is still connected. Make sure

to disconnect the power cable before re-

moving or installing components. See the

layout below for the LED location.

Link LED (off,

green, amber)

Activity LED

(yellow)

Rear View

(When Viewing from the back of the systgem)

GLAN Activity Indicator

(Yellow)

LED Color Deﬁ nition

Yellow Blinking: LAN active

Yellow Solid on: LAN connected

GLAN Link Indicator

LED Color Deﬁ nition

Off No Connection or 10 Mbps

Green 100 Mbps

Amber 1 Gbps

Onboard PWR LED Indicator (LE1)

LED Color Deﬁ nition

Off System Off

Green System On

Yellow System off, PWR Cable

Connected

KB/

Mo

USB 0

COM1

G

V

se

u

Parrallel

JLAN1

A

GLAN1

GLAN2

CT

S

COM

J

/1

Port

S

GA

V

TRL

C

N

A

L

R

I/O

2

an

F

A

B

UPE R

t7

o

l

S

t6

o

l

S

R

t5

o

l

S

lot4

S

lot3

S

L1

P

J

R

L2

P

J

lot2

S

1

t

o

l

S

an5

F

6

®

SIMLP IPMI

1

G

P

J

PCI-Exp x8

PCI-Exp x4

D

W

J

X

-

I

C

P

X

-

I

C

P

JW

X

CI-

P

in

P

-

4

R

PW

DIMM 4

D

IMM

DIMM

DIMM 3

DIMM 2

DIMM 1

D

IMM

X7DB3

133 MHz

J28 J27

Hz

M

133

OR

Hz

M

100

-

4

2

B (

4

A (Ba

3

B (Ba

A (Ban

B (Bank 2)

A

B

1

A (Ba

SEPC

y

er

Batt

ZCR

A

B

ank 4)

(B

a

(

B

ank 1)

B

P

X

T

n

k

4

nk 3)

k

n

k

2)

n

k

1)

S

IO

W

Buzzer

)

3

)

00P

l 50

e

t

n

I

ge

d

ri

B

h

rt

No

MB

S

J

K1

0

ATA

S

J3P

JAR

Core

eon Dual

X

1

PU

C

Dual Core

n

o

Xe

2

PU

C

JBT1

H

X

P

J

L

1

ATA

S

SAS CTRLR Adaptec 9410W

J7

Inte

4

B

S

U

S

U

4

ATA

S

2

ATA

S

B2/3

Sou

5

L

WO

3

l

t

J JWF

E

h

8-pinPWR

A. GLAN Port1 LEDs

1 n a F

B. GLAN Port2 LEDs

C. Onboard PWR LED

FP Control

n2 a F

SPK

PW LED

JP1

LE1

C

JOH1

Fa

n

3

8

an

F

2

SGPIO

1

lash

1 E

act F

SGPIO

1

CF

1

S1

JP

SB2

ridge

B

ID

Floppy

mp o C

on

C

D

E

L

P

B

7

S4A S

3

S0

SA

3

SA

J

Fan4

PSF

SMBPS

an7

F

R

2-29

X7DB3 User's Manual

A

Backpanel SAS Activity LED Header

(JSLED1), located next to IDE1, indicates

SAS Activity status. See the table on the

right for pin deﬁ nitions. (*Note: SAS Com-

mon LED will be activated when any of

SAS0 to SAS7 LEDs is activated.)

Onboard SAS Activity LED Indicators

There are eight Onboard SAS Activity

LED indicators on the X7DB3. LED Indi-

cators Act#0 to Act#7 indicate the activity

status of onboard SAS connectors. See

the table on the right for LED settings.

Backpanel SAS_ACT_Output

Pin Deﬁ nitions

Pin# Deﬁ nition Pin# Deﬁ nition

1 SAS0:Act 6 SAS4:Act

2 SAS1:Act 7 SAS5:Act

3 SAS2:Act 8 SAS6:Act

4 SAS3:Act 9 SAS7:Act

5 *SAS

10 NC

Common

Onboard SAS_Activity_LED Indica-

tors (*Note: Act=Active)

Act# Deﬁ nition Act# Deﬁ nition

Act#0 SAS0:Act Act#4 SAS4:Act

Act#1 SAS1:Act Act#5 SAS5:Act

Act#2 SAS2:Act Act#6 SAS6:Act

Act#3 SAS3:Act Act#7 SAS7:Act

KB

Mo

USB 0

C

G

V

u

M1

O

Parrallel

A

GLAN1

GLAN2

JCOM2

/

se

/

Port

JLAN1

L

C

I/O

S

1

S

GA

V

TRL

C

N

A

R

L

R

T

an6

F

UPE R

lot7

S

J

lot6

S

R

lot5

S

lot4

S

3

t

o

l

S

L1

P

J

L2

P

J

2

t

lo

S

lot1

S

5

Fan

®

X7DB

SIMLP IPMI

1

G

P

PCI-Exp x8

I-E

C

P

PCI-Exp x4

D

W

J

13

X

-

I

C

P

J2 J27

13

X

-

I

C

P

JWO

1

X

CI-

P

DI

DIMM 4

x

p

x

3

8

3 M

R

00

in

P

-

4 PWR

M

4

DIMM 3

DIM

M

3A

DIMM

D

IMM

D

IM

M

DIMM 1

3

8

z

H

M

z

H

ZCR

Hz

M

24-Pi

B (Bank

A (B

B (

B

(

B

2

B (Ba

2

A (Ba

1

B (Bank 1)

A (Ban

SEPC

ttery

Ba

ATX PW

n

a

nk 4)

a

nk 3

a

n

nk 2)

n

IOS

B

4)

k

3)

k

2

k

1)

R

)

50

l

Inte

orth Bridge

N

J

K1

ATA

S

Buzzer

00P

Onboard SAS Activity LEDs

Act#5

ct#4

Act#0

7

PSF

n

SMBPS

a

F

JAR

J3P

8-pinPWR

Act#1

1

A. Backpanel Activity

n a

F

Act#6

Act#2

Act#7

Act#3

LED

Xeon Dual Core

1

PU

C

LE1

l Cor e

a

u

D

n

eo

X

2

PU

C

2

SGPIO 1

1

T

B

J

H

X

P

MB

S

J

L

1

0

ATA

S

SAS CTRLR Adaptec 9410W

J7

4

SB

U

3

USB2/

4

5

ATA

S

WOL

A2

A3

T

A

S

I

S

t

n

o

J J

l ES B 2

e

h Bridge

t

u

CF1 W

F

J

lash

act F

SGPIO

Floppy

mp o

1

C

S1

P

PLED

B

7

A

B

S4A S

3

S0

SA

SA3

J

Fa

B. SAS#0-7 Activity LEDs

FP C ontrol

an2 F

SPK

PW LED

JP1

JOH1

Fa

n3

8

an

F

1 E

ID

n

o

C

n4

2-30

Chapter 2: Installation

2-8 Parallel Port, Floppy Drive, Hard Disk Drive and SIMLP IPMI Connections

Note the following when connecting the ﬂ oppy and hard disk drive cables:

• The ﬂ oppy disk drive cable has seven twisted wires.

• A red mark on a wire typically designates the location of pin 1.

• A single ﬂ oppy disk drive ribbon cable has 34 wires and two connectors to provide

for two ﬂ oppy disk drives. The connector with twisted wires always connects to

drive A, and the connector that does not have twisted wires always connects to

drive B.

Parallel (Printer) Port Connector

The parallel (printer) port is located

at J21. See the table on the right for

pin deﬁ nitions.

in

P

-

4

5

KB

u

Mo

USB0/1

M1

O

C

Parrallel

A

G

V

GLAN1

GLAN2

J

/

se

Port

JLAN1

L

C

I/O

S

O

C

S

UPE R

GA

V

CTRLR

N

A

R

L

R

T

2

M

Fan

an6

F

A

®

X7D

lot7

S

SIMLP IPMI

1

G

P

J

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Pin# Deﬁ nition Pin # Deﬁ nition

1 Strobe- 2 Auto Feed-

3 Data Bit 0 4 Error-

5 Data Bit 1 6 Init-

7 Data Bit 2 8 SLCT IN-

9 Data Bit 3 10 GND

11 Data Bit 4 12 GND

13 Data Bit 5 14 GND

15 Data Bit 6 16 GND

17 Data Bit 7 18 GND

19 ACK 20 GND

21 BUSY 22 Write Data

23 PE 24 Write Gate

25 SLCT 26 NC

l Cor e

2

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h

t

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Parallel (Printer) Port Connector

Pin Deﬁ nitions

8-pinPWR

1 n a F

FP C ontrol

n2 a F

SPK

PW LED

JP1

LE1

JOH1

Fa

n3

8

an

F

2

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1 E

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A. Parallel Port

2-31

X7DB3 User's Manual

Floppy Connector

The ﬂ oppy connector is located at

J21. See the table below for pin

deﬁ nitions.

SIMLP IPMI Slot

There is a SIMLP IPMI Slot

on the motherboard. Refer to

the layout below for the IPMI

Slot location. Note: This slot is

reserved for the optional AOC-

SIMLP IPMI card.

Floppy Drive Connector Pin Deﬁ nitions (Floppy)

Pin# Deﬁ nition Pin # Deﬁ nition

1 Ground 2 FDHDIN

3 Ground 4 Reserved

5 Key 6 FDEDIN

7 Ground 8 Index

9 Ground 10 Motor Enable

11 Ground 12 Drive Select B

13 Ground 14 Drive Select B

15 Ground 16 Motor Enable

17 Ground 18 DIR

19 Ground 20 STEP

21 Ground 22 Write Data

23 Ground 24 Write Gate

25 Ground 26 Track 00

27 Ground 28 Write Protect

29 Ground 30 Read Data

31 Ground 32 Side 1 Select

33 Ground 34 Diskette

JLAN1

S

UPE R

®

X7DB

A. Floppy

B. SIMLP IPMI

3

B

A

2-32

Chapter 2: Installation

IDE Connectors

There are two IDE Connectors (JIDE1:

Blue, JIDE2: White) on the moth-

erboard. The blue IDE connector

(JIDE1) is designated the Primary

IDE Drive. The white IDE connector

(JIDE2) is designated the Second-

ary IDE Drive, reserved for Compact

Flash Card use only. (See the note

below.) See the table on the right for

pin deﬁ nitions.

Note: JIDE2 (the white slot) is re-

served for Compact Flash Card only.

Do not use it for other devices. If

JIDE2 is populated with a Compact

Flash Card, JIDE1 (the blue slot) will

be available for one device only. For

the Compact Flash Card to work prop-

erly, you will need to connect a power

cable to JWF1 ﬁ rst.

IDE Drive Connectors

Pin Deﬁ nitions

Pin# Deﬁ nition Pin # Deﬁ nition

1 Reset IDE 2 Ground

3 Host Data 7 4 Host Data 8

5 Host Data 6 6 Host Data 9

7 Host Data 5 8 Host Data 10

9 Host Data 4 10 Host Data 11

11 Host Data 3 12 Host Data 12

13 Host Data 2 14 Host Data 13

15 Host Data 1 16 Host Data 14

17 Host Data 0 18 Host Data 15

19 Ground 20 Key

21 DRQ3 22 Ground

23 I/O Write 24 Ground

25 I/O Read 26 Ground

27 IOCHRDY 28 BALE

29 DACK3 30 Ground

31 IRQ14 32 IOCS16

33 Addr1 34 Ground

35 Addr0 36 Addr2

37 Chip Select 0 38 Chip Select 1

39 Activity 40 Ground

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2-33

X7DB3 User's Manual

Notes

2-34

Chapter 3: Troubleshooting

Chapter 3

Troubleshooting

3-1 Troubleshooting Procedures

Use the following procedures to troubleshoot your system. If you have followed all

of the procedures below and still need assistance, refer to the ‘Technical Support

Procedures’ and/or ‘Returning Merchandise for Service’ section(s) in this chapter.

Note: Always disconnect the power cord before adding, changing or installing any

hardware components.

Before Power On

1. Make sure that there are no short circuits between the motherboard and chas-

sis.

2. Disconnect all ribbon/wire cables from the motherboard, including those for the

keyboard and mouse.

3. Remove all add-on cards.

4. Install one CPU (making sure it is fully seated) and connect the chassis speaker

and the power LED to the motherboard. (Check all jumper settings as well.)

5. Use only the correct type of CMOS onboard battery as recommended by the

Manufacturer. Do not install the onboard battery upside down to avoid pos-

sible explosion.

No Power

1. Make sure that there are no short circuits between the motherboard and the

chassis.

2. Verify that all jumpers are set to their default positions.

3. Check that the 115V/230V switch on the power supply is properly set.

4. Turn the power switch on and off to test the system.

No Video

1. If the power is on but you have no video, remove all the add-on cards and

cables.

2. Use the speaker to determine if any beep codes exist. Refer to the Appendix

for details on beep codes.

3-1

X7DB3 User's Manual

Losing the System’s Setup Conﬁ guration

1. Ensure that you are using a high quality power supply. A poor quality power

supply may cause the system to lose the CMOS setup information. Refer to

Section 1-6 for details on recommended power supplies.

2. The battery on your motherboard may be old. Check to verify that it still supplies

~3VDC. If it does not, replace it with a new one.

3. If the above steps do not ﬁ x the Setup Conﬁ guration problem, contact your

vendor for repairs.

NOTE

If you are a system integrator, VAR or OEM, a POST diagnostics

card is recommended. For I/O port 80h codes, refer to App. B.

Memory Errors

1. Make sure the DIMM modules are properly and fully installed.

2. Determine if different speeds of DIMMs have been installed and verify that the

BIOS setup is conﬁ gured for the fastest speed of RAM used. It is recom-

mended to use the same RAM speed for all DIMMs in the system.

3. Make sure you are using the correct type of DDR2 Fully Buffered (FBD) ECC

533/667 SDRAM (*recommended by the manufacturer.)

4. Check for bad DIMM modules or slots by swapping a single module between

four slots and noting the results.

5. Make sure all memory modules are fully seated in their slots. As an interleaved

memory scheme is used, you must install two modules at a time, beginning

with Bank 1, then Bank 2, and so on (see Section 2-3).

6. Check the position of the 115V/230V switch on the power supply.

3-2 Technical Support Procedures

Before contacting Technical Support, please take the following steps. Also, note

that as a motherboard manufacturer, Super Micro does not sell directly to end-us-

ers, so it is best to ﬁ rst check with your distributor or reseller for troubleshooting

services. They should know of any possible problem(s) with the speciﬁ c system

conﬁ guration that was sold to you.

1. Please go through the ‘Troubleshooting Procedures’ and 'Frequently Asked Ques-

tion' (FAQ) sections in this chapter or see the FAQs on our web site (

www.supermicro.com/support/faqs/) before contacting Technical Support.

http://

3-2

Chapter 3: Troubleshooting

2. BIOS upgrades can be downloaded from our web site at (http://www.supermicro.

com/support/bios/

Note: Not all BIOS can be ﬂ ashed; it depends on the modiﬁ cations to the boot block code.

3. If you still cannot resolve the problem, include the following information when

contacting Super Micro for technical support:

• Motherboard model and PCB revision number

• BIOS release date/version (this can be seen on the initial display when your

system ﬁ rst boots up)

•System conﬁ guration

An example of a Technical Support form is on our web site at

supermicro.com/support/contact.cfm).

4. Distributors: For immediate assistance, please have your account number ready

when placing a call to our technical support department. We can be reached

by e-mail at support@supermicro.com or by fax at: (408) 503-8000, option

2.

)

(http://www.

3-3 Frequently Asked Questions

Question: What are the various types of memory that my motherboard can support?

Answer: The X7DB3 has eight 240-pin DIMM slots that support DDR2 FDB ECC

533/667 SDRAM modules. It is strongly recommended that you do not mix memory

modules of different speeds and sizes. (See Chapter 2 for detailed Information.)

Question: How do I update my BIOS? Answer: It is recommended that you do not upgrade your BIOS if you are experi-

encing no problems with your system. Updated BIOS ﬁ les are located on our web

site at http://www.supermicro.com/support/bios/. Please check our BIOS warning

message and the information on how to update your BIOS on our web site. Also,

check the current BIOS revision and make sure that it is newer than your BIOS

before downloading. Select your motherboard model and download the BIOS ﬁ le

to your computer. You can choose from the zip ﬁ le and the .exe ﬁ le. If you choose

the zip BIOS ﬁ le, please unzip the BIOS ﬁ le onto a bootable device or a USB pen.

Run the batch ﬁ le using the format ﬂ ash.bat ﬁ lename.rom from your bootable device

or USB pen to ﬂ ash the BIOS. Then, your system will automatically reboot. If you

choose the .exe ﬁ le, please run the .exe ﬁ le under Windows to create the BIOS ﬂ ash

ﬂ oppy disk. Insert the ﬂ oppy disk into the system you wish to ﬂ ash the BIOS. Then,

bootup the system to the ﬂ oppy disk. The BIOS utility will automatically ﬂ ash the

BIOS without any prompts. Please note that this process may take a few minutes

to complete. Do not be concerned if the screen is paused for a few minutes.

3-3

X7DB3 User's Manual

(Warning: Do not shut down or reset the system while updating BIOS to

prevent possible system boot failure!)

Question: What's on the CD that came with my motherboard? Answer: The supplied compact disc has quite a few drivers and programs that will

greatly enhance your system. We recommend that you review the CD and install the

applications you need. Applications on the CD include chipset drivers for Windows

and security and audio drivers.

3-4 Returning Merchandise for Service

A receipt or copy of your invoice marked with the date of purchase is required be-

fore any warranty service will be rendered. You can obtain service by calling your

vendor for a Returned Merchandise Authorization (RMA) number. When returning

to the manufacturer, the RMA number should be prominently displayed on the

outside of the shipping carton, and mailed prepaid or hand-carried. Shipping and

handling charges will be applied for all orders that must be mailed when service

is complete.

This warranty only covers normal consumer use and does not cover damages in-

curred in shipping or from failure due to the alternation, misuse, abuse or improper

maintenance of products.

During the warranty period, contact your distributor ﬁ rst for any product problems.

3-4

Chapter 4: BIOS

Chapter 4

BIOS

4-1 Introduction

This chapter describes the Phoenix BIOS™ Setup utility for the X7DB3. The

Phoenix ROM BIOS is stored in a ﬂ ash chip and can be easily upgraded using a

ﬂ oppy disk-based program.

Note: Due to periodic changes to the BIOS, some settings may have been added

or deleted and might not yet be recorded in this manual. Please refer to the Manual

Download area of the Super Micro web site <http://www.supermicro.com> for any

changes to the BIOS that may not be reﬂ ected in this manual.

System BIOS

The BIOS is the Basic Input Output System used in all IBM® PC, XT™, AT®, and

PS/2® compatible computers. The Phoenix BIOS stores the system parameters,

types of disk drives, video displays, etc. in the CMOS. The CMOS memory requires

very little electrical power. When the computer is turned off, a backup battery pro-

vides power to the CMOS Logic, enabling it to retain system parameters. When the

computer is powered on, the computer is conﬁ gured with the values stored in the

CMOS Logic by the system BIOS, which gains control at boot up.

How To Change the Conﬁ guration Data

The CMOS information that determines the system parameters may be changed by

entering the BIOS Setup utility. This Setup utility can be accessed by pressing the

<Delete> key at the appropriate time during system boot. (See below.)

Starting the Setup Utility

Normally, the only visible POST (Power On Self Test) routine is the memory test. As

the memory is being tested, press the <Delete> key to enter the main menu of the

BIOS Setup utility. From the main menu, you can access the other setup screens,

such as the Security and Power menus. Beginning with Section 4-3, detailed de-

scriptions are given for each parameter setting in the Setup utility.

Warning: Do not shut down or reset the system while updating BIOS

to prevent possible boot failure.

4-1

X7DB3 User's Manual

4-2 Running Setup

*Default settings are in bold text unless otherwise noted.

The BIOS setup options described in this section are selected by choosing the ap-

propriate text from the main BIOS Setup screen. All displayed text is described in

this section, although the screen display is often all you need to understand how

to set the options (See the next page).

When you ﬁ rst power on the computer, the Phoenix BIOS™ is immediately acti-

vated.

While the BIOS is in control, the Setup program can be activated in one of two

ways:

1. By pressing <Delete> immediately after turning the system on, or

2. When the message shown below appears brieﬂ y at the bottom of the screen

during the POST (Power On Self-Test), press the <Delete> key to activate the

main Setup menu:

Press the <Delete> key to enter Setup

4-3 Main BIOS Setup

All main Setup options are described in this section. The main BIOS Setup screen

is displayed below.

Use the Up/Down arrow keys to move among the different settings in each menu.

Use the Left/Right arrow keys to change the options for each setting.

Press the <Esc> key to exit the CMOS Setup Menu. The next section describes

in detail how to navigate through the menus.

Items that use submenus are indicated with the Xicon. With the item highlighted,

press the <Enter> key to access the submenu.

4-2

Main BIOS Setup Menu

Chapter 4: BIOS

Main Setup Features

System Time

To set the system date and time, key in the correct information in the appropriate

ﬁ elds. Then press the <Enter> key to save the data.

System Date

Using the arrow keys, highlight the month, day and year ﬁ elds, and enter the correct

data. Press the <Enter> key to save the data.

BIOS Date

This ﬁ eld displays the date when this version of BIOS was built.

Legacy Diskette A

This setting allows the user to set the type of ﬂ oppy disk drive installed as diskette A.

The options are Disabled, 360Kb 5.25 in, 1.2MB 5.25 in, 720Kb 3.5 in, 1.44/1.25MB,

3.5 in and 2.88MB 3.5 in.

4-3

X7DB3 User's Manual

XIDE Channel 0 Master/Slave, IDE Channel 1 Master/Slave, SATA Port2 and SATA Port3

These settings allow the user to set the parameters of IDE Channel 0 Master/

Slave, IDE Channel 1 Master/Slave, IDE Channel 2 Master, IDE Channel 3 Master

slots. Hit <Enter> to activate the following sub-menu screen for detailed options

of these items. Set the correct conﬁ gurations accordingly. The items included in

the sub-menu are:

Type

This option allows the user to select the type of IDE hard drive. The option

Auto will allow the BIOS to automatically conﬁ gure the parameters of the

HDD installed at the connection. Enter a number between 1 to 39 to select a

predetermined HDD type. Select User to allow the user to enter the parameters

of the HDD installed. Select CDROM if a CDROM drive is installed. Select ATAPI

if a removable disk drive is installed.

4-4

Chapter 4: BIOS

CHS Format

The following items will be displayed by the BIOS:

TYPE: This item displays the type of IDE or SATA Device. Cylinders: This item indicates the status of Cylinders. Headers: This item indicates the number of headers. Sectors: This item displays the number of sectors. Maximum Capacity: This item displays the maximum storage capacity of the

system.

LBA Format

The following items will be displayed by the BIOS:

Total Sectors: This item displays the number of total sectors available in the

LBA Format.

Maximum Capacity: This item displays the maximum capacity in the LBA

Format.

Multi-Sector Transfers

This item allows the user to specify the number of sectors per block to be

used in multi-sector transfer. The options are Disabled, 4 Sectors, 8 Sectors,

and 16 Sectors.

LBA Mode Control

This item determines whether the Phoenix BIOS will access the IDE Channel 0

Master Device via the LBA mode. The options are Enabled and Disabled.

32 Bit I/O

This option allows the user to enable or disable the function of 32-bit data transfer.

The options are Enabled and Disabled.

Transfer Mode

This option allows the user to set the transfer mode. The options are Standard,

Fast PIO1, Fast PIO2, Fast PIO3, Fast PIO4, FPIO3/DMA1 and FPIO4/DMA2.

Ultra DMA Mode

This option allows the user to select Ultra DMA Mode. The options are Disabled,

Mode 0, Mode 1, Mode 2, Mode 3, Mode 4, and Mode 5.

4-5

X7DB3 User's Manual

Parallel ATA

This setting allows the user to enable or disable the function of the Parallel ATA.

The options are Disabled, Channel 0, Channel 1, and Both.

Serial ATA

This setting allows the user to enable or disable the function of the Serial ATA. The

options are Disabled and Enabled.

Native Mode Operation

Select the native mode for ATA. The options are: Parallel ATA, Serial ATA, Both,

and Auto.

SATA Controller Mode

Select Compatible to allow the SATA and PATA drives to be automatically-detected

and be placed in the Legacy Mode by the BIOS. Select Enhanced to allow the

SATA and PATA drives to be to be automatically-detected and be placed in the

Native IDE Mode. (*Note: The Enhanced mode is supported by the Windows

2000 OS or a later version.)

When the SATA Controller Mode is set to Enhanced, the following items will

display:

Serial ATA (SATA) RAID Enable

Select Enable to enable Serial ATA RAID Functions. (*For the Windows OS

environment, use the RAID driver if this feature is set to Enabled. When this item

is set to Enabled, the item: "ICH RAID Code Base" will be available for you to select

Intel ﬁ rmware to be activated. If this item is set to Disabled, the item-SATA AHCI Enable will be available.) The options are Enabled and Disabled.

ICH RAID Code Base

Select Intel to enable Intel's SATA RAID ﬁ rmware. The default setting is Intel.

SATA AHCI

Select Enable to enable the function of Serial ATA Advanced Host Interface. (*Take

caution when using this function. This feature is for advanced programmers only.

The options are Enabled and Disabled.)

4-6

Chapter 4: BIOS

System Memory

This display informs you how much system memory is detected in the system.

Extended Memory

This display informs you how much extended memory is detected in the system.

4-4 Advanced Setup

Choose Advanced from the Phoenix BIOS Setup Utility main menu with the arrow keys.

You should see the following display. The items with a triangle beside them have sub

menus that can be accessed by highlighting the item and pressing <Enter>.

4-7

X7DB3 User's Manual

XBoot Features

Access the submenu to make changes to the following settings.

Quick Boot Mode

If enabled, this feature will speed up the POST (Power On Self Test) routine by

skipping certain tests after the computer is turned on. The settings are Enabled

and Disabled. If Disabled, the POST routine will run at normal speed.

Quiet Boot

This setting allows you to Enable or Disable the graphic logo screen during

boot-up.

ACPI Mode

Use the setting to determine if you want to use ACPI (Advanced Conﬁ guration

and Power Interface) power management on your system. The options are

Yes and No.

Power Button Behavior

If set to Instant-Off, the system will power off immediately as soon as the user

hits the power button. If set to 4-sec., the system will power off when the user presses the power button for 4 seconds or longer. The options are instant-off and 4-sec override.

Resume On Modem Ring

Select On to “wake your system up” when an incoming call is received by your

modem. The options are On and Off.

Power Loss Control

This setting allows you to choose how the system will react when power returns

after an unexpected loss of power. The options are Stay Off, Power On, and

Last State.

Watch Dog

If enabled, this option will automatically reset the system if the system is not

active for more than 5 minutes. The options are Enabled and Disabled.

Summary Screen

This setting allows you to Enable or Disable the summary screen which displays

the system conﬁ guration during bootup.

4-8

Chapter 4: BIOS

XMemory Cache Cache System BIOS Area

This setting allows you to designate a reserve area in the system memory to be used

as a System BIOS buffer to allow the BIOS to write (cache) data into this reserved

memory area. Select Write Protect to enable this function, and this area will be

reserved for BIOS ROM access only. Select Uncached to disable this function and

make this area available for other devices.

Cache Video BIOS Area

This setting allows you to designate a reserve area in the system memory to be

used as a Video BIOS buffer to allow the BIOS to write (cache) data into this

reserved memory area. Select Write Protect to enable the function and this area

will be reserved for Video BIOS ROM access only. Select Uncached to disable this

function and make this area available for other devices.

Cache Base 0-512K

512K to be cached (written) into a buffer, a storage area in Static DROM (SDROM)

or to be written into L1, L2 cache inside the CPU to speed up CPU operations.

Select Uncached to disable this function. Select Write Through to allow data to

be cached into the buffer and written into the system memory at the same time.

Select Write Protect to prevent data from being written into the base memory

area of Block 0-512K. Select Write Back to allow the CPU to write data back

directly from the buffer without writing data to the System Memory for fast CPU

data processing and operation. The options are Uncached, Write Through, Write

Protect, and Write Back.

Cache Base 512K-640K

If enabled, this feature will allow the data stored in the memory area: 512K-640K

to be cached (written) into a buffer, a storage area in the Static DROM (SDROM)

or written into L1, L2, L3 cache inside the CPU to speed up CPU operations.

Select Uncached to disable this function. Select Write Through to allow data to

be cached into the buffer and written into the system memory at the same time.

Select Write Protect to prevent data from being written into the base memory

area of Block 512-640K. Select Write Back to allow the CPU to write data back

directly from the buffer without writing data to the System Memory for fast CPU

data processing and operation. The options are Uncached, Write Through, Write

Protect, and Write Back.

Cache Extended Memory

If enabled, this feature will allow the data stored in the extended memory area to

be cached (written) into a buffer, a storage area in the Static DROM (SDROM)

or written into L1, L2, L3 cache inside the CPU to speed up CPU operations.

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X7DB3 User's Manual

Select Uncached to disable this function. Select Write Through to allow data

to be cached into the buffer and written into the system memory at the same

time. Select Write Protect to prevent data from being written into the extended

memory area above 1 MB. Select Write Back to allow the CPU to write data back

directly from the buffer without writing data to the System Memory for fast CPU

data processing and operation. The options are Uncached, Write Through, Write

Protect, and Write Back.

Discrete MTRR Allocation

If enabled, MTRRs (-Memory Type Range Registers) are conﬁ gured as distinct, separate units and cannot be overlapped. If enabled, the user can achieve better graphic effects when using a Linux graphic driver that requires the write-combining

conﬁ guration with 4GB or more memory. The options are Enabled and Disabled.

XPCI Conﬁ guration

Access the submenu to make changes to the following settings for PCI devices.

Onboard GLAN1/Onboard GLAN2 (Gigabit- LAN) OPROM Conﬁ gure

Enabling this option provides the capability to boot from GLAN. The options are

Disabled and Enabled.

Onboard SCSI OPROM Conﬁ gure

Enabling this option provides the capitally to boot from SCSI HDD. The options

are Disabled and Enabled.

PCI Parity Error Forwarding

The feature allows SERR and PERR errors detected in PCI slots to be sent

(forwarded) to the BIOS DMI Event Log for the user to review. The options are

Enabled and Disabled.

Reset Conﬁ guration Data

If set to Yes, this setting clears the Extended System Conﬁ guration Data- (ESCD)

area. The options are Yes and No.

Frequency for PCI-X#1, PCI-X#2, PCI-X#3

This option allows the user to change the bus frequency for the devices installed

in the slot indicated. The options are Auto, PCI 33 MHz, PCI 66 MHz, PCI-X 66

MHz, PCI-X 100 MHz, and PCI-X 133 MHz.

Frequency for PCI-X#1 On Riser, Frequency for PCI-X#2-#3 On Riser

(Available when an Active Riser Card is present.)

This option allows the user to change the bus frequency of the devices installed

in the slot indicated. The options are Auto, PCI 33 MHz, PCI 66 MHz, PCI-X 66

MHz, PCI-X 100 MHz, and PCI-X 133 MHz.

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XSlot1 PCI-X 100 MHz ZCR, Slot2 PCI-X 133MHz, Slot3 PCI-X 133MHz, Slot4 PCI-Exp x4, Slot5 PCI-Exp x8, and Slot6 PCI-Exp x8

Access the submenu for each of the settings above to make changes to the

following:

Option ROM Scan

When enabled, this setting will initialize the device expansion ROM. The options

are Enabled and Disabled.

Enable Master

This setting allows you to enable the selected device as the PCI bus master.

The options are Enabled and Disabled.

Latency Timer

This setting allows you to set the clock rate for Bus Master. A high-priority, high-

throughout device may beneﬁ t from a greater clock rate. The options are Default,

0020h, 0040h, 0060h, 0080h, 00A0h, 00C0h, and 00E0h. For Unix, Novell and

other Operating Systems, please select the option: other. If a drive fails after

the installation of a new software, you might want to change this setting and

try again. A different OS requires a different Bus Master clock rate.

Large Disk Access Mode

This setting determines how large hard drives are to be accessed. The options are

DOS or Other (for Unix, Novelle NetWare and other operating systems).

XAdvanced Chipset Control

Access the submenu to make changes to the following settings.

Warning: Take caution when changing the Advanced settings. An incorrect

setting, a very high DRAM frequency or an incorrect DRAM timing may cause

the system to become unstable. When this occurs, revert to the default set-

ting.

SERR Signal Condition

This setting speciﬁ es the ECC Error conditions that an SERR# is to be asserted.

The options are None, Single Bit, Multiple Bit, and Both.

4GB PCI Hole Granularity

This feature allows you to select the granularity of PCI hole for PCI slots. If MTRRs

are not enough, this option may be used to reduce MTRR occupation. The options

are: 256 MB, 512 MB, 1GB and 2GB.

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Memory Branch Mode

This option determines how the two memory branches operate. System address

space can either be interleaved between the two branches or Sequential from one

branch to another. Mirror mode allows data correction by maintaining two copies

of data in two branches. Single Channel 0 allows a single DIMM population during

system manufacturing. The options are Interleave, Sequential, Mirroring, and

Single Channel 0.

Branch 0 Rank Sparing

Select enable to enable the sparing feature for Branch 0 Rank. The options are

Enabled and Disabled.

Branch 1 Rank Sparing

Select enable to enable the sparing feature for Branch 0 Rank. The options are

Enabled and Disabled.

Enhanced x8 Detection

Select Enabled to enable Enhanced x8 DRAM UC Error Detection. The options are Disabled and Enabled.

Crystal Beach Features

This feature cooperates with Intel I/O AT (Acceleration Technology) to accelerate the performance of TOE devices. (*Note: A TOE device is a specialized, dedicated processor that is installed on an add-on card or a network card to handle some or all packet processing of this add-on card. For the X7DB3, the TOE device is built

inside the ESB 2 South Bridge chip.) The options are Enabled and Disabled.

Route Port 80h Cycles to

This feature allows the user to decide which bus to send debug information to. The

options are Disabled, PCI and LPC.

Clock Spectrum Feature

If Enabled, the BIOS will monitor the level of Electromagnetic Interference caused

by the components and will attempt to decrease the interference whenever needed.

The options are Enabled and Disabled.

Enabling Multi-Media Timer

Select Yes to activate a set of timers that are alternative to the traditional 8254

timers for the OS use. The options are Yes and No.

USB Function

Select Enabled to enable the function of USB devices speciﬁ ed. The settings are

Enabled and Disabled.

Legacy USB Support

This setting allows you to enable support for Legacy USB devices. The settings

are Enabled and Disabled.

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Chapter 4: BIOS

XAdvanced Processor Options

Access the submenu to make changes to the following settings.

CPU Speed

This is a display that indicates the speed of the installed processor.

Frequency Ratio (*Available when supported by the CPU.)

The feature allows the user to set the internal frequency multiplier for the CPU.

The options are: Default, x12, x13, x14, x15, x16, x17 and x18.

Hyper-threading (*Available when supported by the CPU.)

Set to Enabled to use the Hyper-Threading Technology, which will result in increased

CPU performance. The options are Disabled and Enabled.

Core-Multi-Processing (*Available when supported by the CPU.)

Set to Enabled to use a processor's Second Core and beyond. (Please refer to

Intel's web site for more information.) The options are Disabled and Enabled.

Machine Checking (*Available when supported by the CPU.)

Set to Enabled to activate the function of Machine Checking and allow the CPU to

detect and report hardware (machine) errors via a set of model-speciﬁ c registers

(MSRs). The options are Disabled and Enabled.

Thermal Management 2 (*Available when supported by the CPU.)

Set to Enabled to use Thermal Management 2 (TM2) which will lower CPU voltage

and frequency when the CPU temperature reaches a predeﬁ ned overheat threshold.

Set to Disabled to use Thermal Manager 1 (TM1), allowing CPU clocking to be

regulated via CPU Internal Clock modulation when the CPU temperature reaches

the overheat threshold.

C1 Enhanced Mode (*Available when supported by the CPU.)

Set to Enabled to enable Enhanced Halt State to lower CPU voltage/frequency to

prevent overheat. The options are Enabled and Disabled. (Note: please refer

to Intel’s web site for detailed information.)

No Execute Mode Memory Protection (*Available when supported by the

CPU and the OS.)

Set to Enabled to enable Execute Disable Bit and allow the processor to classify

areas in memory where an application code can execute and where it cannot, and

thus preventing a worm or a virus from inserting and creating a ﬂ ood of codes to

overwhelm the processor or damage the system during an attack.

(Note: this feature is available when your OS and your CPU support the function of Execute Disable Bit.) The options are Disabled and Enabled. (Note: For more

information regarding hardware/software support for this function, please refer to

Intel's and Microsoft's web sites.)

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X7DB3 User's Manual

Adjacent Cache Line Prefetch (*Available when supported by the CPU.)

The CPU fetches the cache line for 64 bytes if this option is set to Disabled. The

CPU fetches both cache lines for 128 bytes as comprised if Enabled. The options

are Disabled and Enabled.

Hardware Prefetch (*Available when supported by the CPU.)

Set to this option to enabled to enable the hardware components that are used in

conjunction with software programs to prefetch data in order to shorten execution

cycles and maximize data processing efﬁ ciency. The options are Disabled and

Enabled.

PECI Absent Alarm (*Available when supported by the CPU.)

If set to Enabled, the PECI Absent Alarm will be activated if the function of PECI

(Platform Environment Control Interface) is not available for the onboard process(s)

or for the motherboard. The options are Disabled and Enabled.

Intel <R> Virtualization Technology (*Available when supported by the CPU.)

Select Enabled to use the feature of Virtualization Technology to allow one platform

to run multiple operating systems and applications in independent partitions, creating

multiple "virtual" systems in one physical computer. The options are Enabled and

Disabled. (*Note: If there is any change to this setting, you will need to power off

and restart the system for the change to take effect.) Please refer to Intel’s web

site for detailed information.

Intel EIST Support (*Available when supported by the CPU.)

Select Enabled to use the Enhanced Intel SpeedStep Technology and allow the

system to automatically adjust processor voltage and core frequency in an effort

to reduce power consumption and heat dissipation. The options are Enabled and Disabled. Please refer to Intel’s web site for detailed information.

XI/O Device Conﬁ guration

Access the submenu to make changes to the following settings.

KBC Clock Input

This setting allows you to select clock frequency for KBC. The options are 6MHz,

8MHz, 12MHz, and 16MHz.

Serial Port A

This setting allows you to assign control of serial port A. The options are Enabled

(user deﬁ ned), Disabled, and Auto (BIOS- or OS- controlled).

Base I/O Address

This setting allows you to select the base I/O address for serial port A. The options

are 3F8, 2F8, 3E8, and 2E8.

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Chapter 4: BIOS

Interrupt

This setting allows you to select the IRQ (interrupt request) for serial port A. The

options are IRQ3 and IRQ4.

Serial Port B

This setting allows you to assign control of serial port B. The options are Enabled

(user deﬁ ned), Disabled, Auto (BIOS controlled) and OS Controlled.

Mode

This setting allows you to set the type of device that will be connected to serial

port B. The options are Normal and IR (for an infrared device).

Base I/O Address

This setting allows you to select the base I/O address for serial port B. The options

are 3F8, 2F8, 3E8 and 2E8.

Interrupt

This setting allows you to select the IRQ (interrupt request) for serial port B. The

options are IRQ3 and IRQ4.

Parallel Port

This setting allows you to assign control of the parallel port. The options are

Enabled (user deﬁ ned), Disabled and Auto (BIOS-or OS- controlled).

Base I/O Address

Select the base I/O address for the parallel port. The options are 378, 278 and

3BC.

Interrupt

This setting allows you to select the IRQ (interrupt request) for the parallel port.

The options are IRQ5 and IRQ7.

Mode

This feature allows you to specify the parallel port mode. The options are Output

only, Bi-Directional, EPP and ECP.

DMA Channel

This item allows you to specify the DMA channel for the parallel port. The options

are DMA1 and DMA3.

Floppy Disk Controller

This setting allows you to assign control of the ﬂ oppy disk controller. The options

are Enabled (user deﬁ ned), Disabled, and Auto (BIOS and OS controlled).

Base I/O Address

This setting allows you to select the base I/O address for the Floppy port. The

options are Primary and Secondary.

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X7DB3 User's Manual

XDMI Event Logging

Access the submenu to make changes to the following settings.

Event Log Validity

This is a display to inform you of the event log validity. It is not a setting.

Event Log Capacity

This is a display to inform you of the event log capacity. It is not a setting.

View DMI Event Log

Highlight this item and press <Enter> to view the contents of the event log.

Event Logging

This setting allows you to Enable or Disable event logging.

ECC Event Logging

This setting allows you to Enable or Disable ECC event logging.

Mark DMI Events as Read

Highlight this item and press <Enter> to mark the DMI events as read.

Clear All DMI Event Logs

Select Yes and press <Enter> to clear all DMI event logs. The options are Yes

and No.

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Chapter 4: BIOS

XConsole Redirection

Access the submenu to make changes to the following settings.

COM Port Address

This item allows you to specify which COM port to direct the remote console to:

Onboard COM A or Onboard COM B. This setting can also be Disabled.

BAUD Rate

This item allows you to set the BAUD rate for the console redirection. The options

are 300, 1200, 2400, 9600, 19.2K, 38.4K, 57.6K, and 115.2K.

Console Type

This item allows you to choose the console redirection type. The options are VT100,

VT100,8bit, PC-ANSI, 7bit, PC ANSI, VT100+,

and VT-UTF8.

Flow Control

This item allows you to set the ﬂ ow control for the console redirection. The options

are: None, XON/XOFF, and CTS/RTS.

Console Connection

This item allows you to decide how the console redirection is to be connected:

either Direct or Via Modem.

Continue CR after POST

This item allows you to decide whether you want to continue with the console

redirection after POST routines. The options are On and Off.

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X7DB3 User's Manual

XHardware Monitor Logic

*Note: The Phoenix BIOS will automatically detect the type of CPU(s) and hardware monitoring chip used on the motherboard and will display the Hardware Monitoring Screen accordingly. Your Hardware Monitoring Screen may look like the one shown on this page, on P. 4-19, or on P. 4-20, depending on the type of CPU(s) and HW Monitoring chip you are using.

CPU Temperature Threshold

This option displays the CPU temperature threshold that will activate the alarm system when the CPU temperature reaches this pre-set threshold. The options are

o

70

C, 75oC, 80

Highlight this and hit <Enter> to see the status of each item below:

CPU1 Temperature/CPU1 Second Core/CPU2 Temperature/CPU2 Second Core/System Temperature

Fan1-Fan8 Speeds: If the feature of Auto Fan Control is enabled, the BIOS will

automatically display the status of the fans indicated in this item.

o

C and 85oC. (See the note below.)

Fan Speed Control Modes

This feature allows the user to decide how the system controls the speeds of the

onboard fans. The CPU temperature and the fan speed are correlative. When the

CPU on-die temperature increases, the fan speed will also increase, and vice versa.

If the option is set to 3-pin fan, the fan speed is controlled by voltage. If the option

is set to 4-pin, the fan speed will be controlled by Pulse Width Modulation (PWM).

Select 3-pin if your chassis came with 3-pin fan headers. Select 4-pin if your chas-

sis came with 4-pin fan headers. Select Workstation if your system is used as a

Workstation. Select Server if your system is used as a Server. Select Disable to

disable the fan speed control function and allow the onboard fans to constantly run

at full speed (12V). Select 4-pin Quiet (or Super Quiet) to lower the fan speed and

noise. The Options are: 1. Disable, 2. 3-pin (Server), 3. 3-pin (Workstation), 4.

4-pin (Server), and 5. 4-pin (Workstation).

Voltage Monitoring

The following items will be monitored and displayed:

P12V_VR0/P12V_VR1/FSB VTT/PXH Vcore/ES2B Vcore/CPU1Vcore/CPU2Vcore/ P3V3

Note: In the Windows OS environment, the Supero Doctor III settings take prece-

dence over the BIOS settings. When ﬁ rst installed, Supero Doctor III adopts the

temperature threshold settings previously set in the BIOS. Any subsequent changes

to these thresholds must be made within Supero Doctor, since the SD III settings

override the BIOS settings. For the Windows OS to adopt the BIOS temperature

threshold settings, please change the SDIII settings to be the same as those set

in the BIOS.

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Chapter 4: BIOS

XHardware Monitor Logic

CPU Temperature Threshold (*See the Note on Page 4-18.)