Supermicro Super X6DH8-XG2, X6DHE-XG2 User Manual

X6DH8-XG2 X6DHE-XG2

USER’S MANUAL

Revision 1.0c

The information in this User’s Manual has been carefully reviewed and is believed to be accurate. The vendor assumes no responsibility for any inaccuracies that may be contained in this document, makes no commitment to update or to keep current the information in this manual, or to notify any person or organization of the updates.

Please Note: For the most up-to-date version of this manual, please see our web site at www.supermicro.com.

SUPERMICRO COMPUTER reserves the right to make changes to the product described in this manual at any time and without notice. This product, including software, if any, and documentation may not, in whole or in part, be copied, photocopied, reproduced, translated or reduced to any medium or machine without prior written consent.

IN NO EVENT WILL SUPERMICRO COMPUTER BE LIABLE FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING FROM THE USE OR INABILITY TO USE THIS PRODUCT OR DOCUMENTATION, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IN PARTICULAR, THE VENDOR SHALL NOT HAVE LIABILITY FOR ANY HARDWARE, SOFTWARE, OR DATA STORED OR USED WITH THE PRODUCT, INCLUDING THE COSTS OF REPAIRING, REPLACING, INTEGRATING, INSTALLING OR RECOVERING SUCH HARDWARE, SOFTWARE, OR DATA.

Any disputes arising between manufacturer and customer shall be governed by the laws of Santa Clara County in the State of California, USA. The State of California, County of Santa Clara shall be the exclusive venue for the resolution of any such disputes. Supermicro's total liability for all claims will not exceed the price paid for the hardware product.

Manual Revision: Rev. 1.0c Release Date: March 10, 2006

Unless you request and receive written permission from SUPER MICRO COMPUTER, you may not copy any part of this document.

Information in this document is subject to change without notice. Other products and companies referred to herein are trademarks or registered trademarks of their respective companies or mark holders.

Printed in the United States of America

iii

Preface

Preface About This Manual

This manual is written for system integrators, PC technicians and knowledgeable PC users. It provides information for the installation and use of the X6DH8-XG2/X6DHE-XG2 motherboard. The X6DH8XG2/X6DHE-XG2 supports single or dual Intel® NoconaTM processors at a 800 MHz front side bus. Based upon Intel's NetBurst microarchitecture, the Nocona processor supports the IA-32 software and includes features found in the XeonTM processor such as Hyper Pipelined Technology, which includes a multi-stage pipeline, allowing the processor to operate at much higher core frequencies. Packaged in a 604-pin Flip Chip Micro Pin Grid Array(FC-mPGA4) platform in a Zero Insertion Force(ZIF) socket (mPGA

604), the Nocona Processor (800 MHz) which supports Hyper-Threading Technology and Intel EM64T, is ideal for high performance workstation and server environments with up to two processors on one system bus. Please refer to the motherboard specifications pages on our web site (http:// www.supermicro.com/Product_page/product-m.htm) for updates on supported processors. This product is intended to be professionally installed.

Manual Organization

Chapter 1 begins with a checklist of what should be included in your

mainboard box, describes the features, specifications and performance of the motherboard and provides detailed information about the chipset.

Chapter 2 begins with instructions on handling static-sensitive devices. Read this chapter when you want to install the processor and DIMM memory modules and when mounting the mainboard in the chassis. Also refer to this chapter to connect the floppy and hard disk drives, SCSI drives, the IDE interfaces, the parallel and serial ports, the keyboard and mouse, the power supply and various control panel buttons and indicators.

If you encounter any problems, see Chapter 3, which describes troubleshooting procedures for the video, the memory and the setup configuration stored in CMOS. For quick reference, a general FAQ [Frequently Asked Questions] section is provided.

Chapter 4 includes an introduction to BIOS and provides detailed information on running the CMOS Setup utility.

Appendix A provides BIOS POST Messages. Appendix B provides BIOS POST codes. Appendix C provides software and the OS installation instructions.

iv

Preface

About This Manual ...................................................................................................... iii

Manual Organization ................................................................................................... ii i

Chapter 1: Introduction

1-1 Overview ......................................................................................................... 1-1

Checklist .................................................................................................... 1-1

Contacting Supermicro ............................................................................ 1-2

X6DH8-XG2/X6DHE-XG2 Image ............................................... 1-3

X6DH8-XG2/X6DHE-XG2 Layout ............................................. 1-4

X6DH8-XG2/X6DHE-XG2 Quick Reference............................ 1-5

Motherboard Features ............................................................................. 1-6

Intel E7520 Chipset: System Block Diagram ........................................ 1-8

1-2 Chipset Overview........................................................................................... 1-9

1-3 Special Features........................................................................................... 1-10

BIOS Recovery ....................................................................................... 1-10

Recovery from AC Power Loss ......................................................... 1-10

1-4 PC Health Monitoring.................................................................................... 1-10

1- 5 ACPI Features ............................................................................................... 1-11

1-6 Power Supply ............................................................................................... 1-13

1- 7 Super I/O ......................................................................................................... 1-14

Chapter 2: Installation

2-1 Static-Sensitive Devices ............................................................................... 2-1

Precautions............................................................................................... 2-1

Unpacking.................................................................................................. 2-1

2-2 Processor and Heatsink Installation ............................................................ 2-2

2-3 Installing DIMMs............................................................................................... 2-5

2- 4 I/O Ports/Control Panel Connectors ............................................................. 2-6

2-5 Connecting Cables .......................................................................................... 2-8

ATX Power Connector............................................................................ 2-8

Processor Power Connector................................................................. 2-8

NMI Button .................................................................................................. 2-9

Power LED ................................................................................................. 2-9

HDD LED .................................................................................................. 2-10

NIC1/NIC2 LED ........................................................................................ 2-10

Overheat/Fan Fail LED .......................................................................... 2-11

Power Fail LED ....................................................................................... 2-11

Table of Contents

X6DH8-XG2/X6DHE-XG2 User's Manual

Table of Contents

v

Reset Button ........................................................................................... 2-12

Power Button ......................................................................................... 2-12

Chassis Intrusion ................................................................................... 2-13

Universal Serial Bus (USB0/1) ............................................................ 2-13

Front Panel Universal Serial Bus Headers ........................................ 2-14

Serial Ports ............................................................................................. 2-14

GLAN (Ethernet Port) ............................................................................. 2-15

ATX PS/2 Keyboard and Mouse Ports ................................................2-15

Fan Headers ........................................................................................... 2-16

Power LED/Speaker Header ................................................................ 2-16

Wake-On-Ring ......................................................................................... 2-17

Wake-On-LAN ......................................................................................... 2-17

SMB Power (I2C) ..................................................................................... 2-18

SMB ........................................................................................................... 2-18

Power Fault ............................................................................................. 2-19

Power Fail Alarm Clear Switch ............................................................ 2-19

Overheat LED .......................................................................................... 2-20

3rd PWR Supply PWR Fault Detect ..................................................... 2-20

2- 6 Jumper Settings ............................................................................................ 2-21

Explanation of Jumpers ........................................................................ 2-21

GLAN Enable/Disable............................................................................. 2-2 1

CMOS Clear............................................................................................. 2-22

Watch Dog Enable/Disable .................................................................... 2-22

VGA Enable/Disable ............................................................................... 2-23

SCSI Enable/Disable................................................................................ 2-24

SCSI Termination Enable/Disable.......................................................... 2-24

2-7 Onboard Indicators ...................................................................................... 2-25

SCSI Channel Activity LEDs .................................................................. 2-25

GLAN LEDs.............................................................................................. 2-25

2- 8 Floppy/Hard Disk Drive and SCSI Connections ....................................... 2-26

Floppy Connector ................................................................................... 2-26

IDE Connectors ...................................................................................... 2-2 7

Ultra320 SCSI Connectors .................................................................... 2-28

Chapter 3: Troubleshooting

3-1 Troubleshooting Procedures ........................................................................ 3-1

Before Power On .................................................................................... 3-1

No Power .................................................................................................. 3-1

No Video ................................................................................................... 3-1

vi

Memory Errors .......................................................................................... 3-2

Losing the System’s Setup Configuration ........................................... 3-2

3-2 Technical Support Procedures .................................................................... 3-2

3-3 Frequently Asked Questions........................................................................ 3-3

3-4 Returning Merchandise for Service............................................................ 3-4

Chapter 4: BIOS

4- 1 Introduction....................................................................................................... 4-1

4- 2 Running Setup.................................................................................................. 4-2

4- 3 Main BIOS Setup.............................................................................................. 4-2

4-4 Advanced Setup.............................................................................................. 4-7

4-5 Security Setup ............................................................................................... 4-18

4- 6 Boot Setup...................................................................................................... 4-20

4-7 Exit ................................................................................................................... 4-21

Appendices:

Appendix A: BIOS POST Messages ..................................................................... A-1

Appendix B: BIOS POST Codes .............................................................................B-1

Appendix C: Installing Software Drivers and the Operating System ..............C-1

X6DH8-XG2/X6DHE-XG2 User's Manual

Chapter 1: Introduction

1-1

Introduction

Chapter 1

Introduction

1-1 Overview

Checklist

Congratulations on purchasing your computer motherboard from an acknowledged leader in the industry. Supermicro boards are designed with the utmost attention to detail to provide you with the highest standards in quality and performance. Check that the following items have all been included with your motherboard. If anything listed here is damaged or missing, contact your retailer. All are included in the Retail Box.

One (1) Supermicro Mainboard

One (1) ribbon cable for IDE devices

One (1) floppy ribbon cable

One (1) Ultra 320 SCSI cable (*X6DH8-XG2 only)

One (1) COM2 cable

One (1) SATA cables

One (1) I/O backpanel shield

One (1) USB 2 Port cable

One (1) Supermicro CD or diskettes containing drivers and utilities

One (1) User's/BIOS Manual

One (1) Ultra 320 SCSI User's Manual (*X6DH8-XG2 only)

1-2

Introduction

X6DH8-XG2/X6DHE-XG2 User's Manual

Contacting Supermicro

Headquarters

Address: SuperMicro Computer, Inc.

980 Rock Ave.

San Jose, CA 95131 U.S.A. Tel: +1 (408) 503-8000 Fax: +1 (408) 503-8008 Email: marketing@supermicro.com (General Information)

support@supermicro.com (Technical Support) Web Site: www.supermicro.com

Europe

Address: SuperMicro Computer B.V.

Het Sterrenbeeld 28, 5215 ML

's-Hertogenbosch, The Netherlands Tel: +31 (0) 73-6400390 Fax: +31 (0) 73-6416525 Email: sales@supermicro.nl (General Information)

support@supermicro.nl (Technical Support)

rma@supermicro.nl (Customer Support)

Asia-Pacific

Address: SuperMicro, Taiwan

4F, No. 232-1 Liancheng Road

Chung-Ho 235, Taipei Hsien, Taiwan, R.O.C. Tel: +886-(2) 8226-3990 Fax: +886-(2) 8226-3991 Web Site: www.supermicro.com.tw Technical Support: Email: support@supermicro.com.tw Tel: 886-2-8228-1366, ext.132 or 139

Chapter 1: Introduction

1-3

Introduction

Figure 1-1. X6DH8-XG2/X6DHE-XG2 Image

(*Note: The drawings and pictures shown in this manual were based on the

latest PCB Revision available at the time of publishiing of this manual. The motherboard you’ve received may or may not look exactly the same as the graphics shown in the manual.)

1-4

Introduction

X6DH8-XG2/X6DHE-XG2 User's Manual

Figure 1-2. X6DH8-XG2/X6DHE-XG2 Motherboard Layout

(not drawn to scale)

1. Jumpers not indicated are for test purposes only.

2. See Chapter 2 for detailed information on jumpers, I/O ports and JF1 front panel connections.

3. " " indicates the location of Pin 1.

4. SCSI is for the X6DH8-XG2 only

5. The drawings and pictures shown in this manual were based on the latest PCB Revision available at the time of publishiing of this manual. The

motherboard you’ve received may or may not look exactly the same as the graphics shown in the manual.

GLAN1

®

S

UPER X6DH8-XG2

GLAN2

DIMM 2B (Bank 2)

DIMM 2A (Bank 2)

DIMM 3B (Bank 3)

DIMM 3A (Bank 3)

DIMM 4B (Bank 4)

DIMM 4A (Bank 4)

DIMM 1A (Bank 1)

DIMM 1B (Bank 1)

Fan1

8-pin PWR

PWR SMBus

CPU Fan1

JF1

FP C

ontrol

JD1

SPK

PW LED

JP15

Fan2

OH

3rd PS

PWR

Fault

Detect

CPU Fan2

Fan3

CH Intru

JL1

WD Enable

IPMI

IDE1

IDE2

Floppy

BIOS

J18

JPA1

Ultra 320

SCSI CH A

Ultra 320

SCSI CH B

F

a

n

4

7902

CTRL

SATA0

SATA1

USB2/3

SMBUS

Buzzer

PCI-X 1 100 MHz ZCR

PCI-X 2 100 MHz

PCI-X #3 133 MHz

WOR

Battery

JPL1

GLAN CTLR

RAGE-X

82546

GLAN Enable

PCI-X #5 133MHz

X8 PCI-Epx #6

Super

I/O

(North Bridge)

JPG1

VGA

C

O

M

1

U

SB0/1

KB/ Mouse

Fan5

Fan6

ATX PWR

4-Pin PWR

JP16

24-Pin

Force PWR ON

VGA Enable

Fan7

J24

JP12

Reboot

Option

JP14

JP13

Fan8

SCSI

CPU 1

CPU 2

Alarm

Reset

SCSI Enable

PXH

PCI-X #4 133MHz

COM2

WOL

USB4

PW

R

Fault

LE1

PW LED

JPA2 JPA3

DA1

DA2

ICH5R

PXH

Lindenhurst

Clear CMOS

CHB SCSI LED

CHA SCSI LED

(South

Bridge)

E7520

82801ER

SCSI CH A Term

SCSI CH B Term

Notes

Chapter 1: Introduction

1-5

Introduction

Jumper Description Default Setting

J18 Watch Dog Enable Pins 1-2 (Reset) JP12 Power Fault (See Chapter 2) JP13 3rd PWR Supply PWR Fault Detect On (Enabled) JP14 Alarm Reset Enable Off (Disabled) JPA1 SCSI Controller Enable On (Enabled)(*X6DH8) JBT1 CMOS Clear See Chapter 2 JPG1 VGA Enable Pins 1-2 (Enabled) JPL1 GLAN Enable/Disable Pins 1-2 (Enabled)

Connector Description

ATX PWR (JPW1) Primary ATX PWR Connector(*Also:JPW2, JPW3) CPU PWR (JPW3) +12 V8-pin CPU PWR Connector (*required) Aux. PWR (JPW2) +12V 4-pin (Auxiliary) system PS (*Required) COM1/COM2 COM1(JCOM1)/COM2(JCOM2) Serial Ports DIMM#1A-DIMM#4B Memory (RAM) Slots FAN 1- 8 CPU/Chassis/Overheat Fan Headers (Fan7: CPU1

Fan, Fan8:CPU2 Fan)

FP USB 2/3/4 Front Panel USB Headers(JUSB2: FPUSB 2/3,

JUSB3: FPUSB 4) GLAN 1/2 G-bit Ethernet Ports IDE1/IDE2 (JIDE1/JIDE2) IDE1/2 Hard Disk Drive Connectors J22 System Management Bus Connector J24 Power System Management Connector JD1 PWR LED(pins1-3)/SpeakerHeader (pins 4-7) JF1 Front Control Panel Connector JL1 Chassis Intrusion Header JPA2, JPA3 SCSI CHA(JPA2),CHB(JPA3)Term. Enabled(X6DH8) JPFDD1 Floppy Disk Drive Connector JPIMI IPMI Connector JOH1 Overheat LED JVGA1 VGA Connector JWOL Wake-on-LAN Header JWOR1 Wake-on-Ring Header USB 0/1(JUSB1) (Back Panel) Universal Serial Bus Ports

Indicator Description

Quick Reference ( X6DH8-XG2/X6DHE-XG2)

(*Please refer to Chapter 2 for pin definitions and detailed information.)

LE1 Power LED DA1/DA2 (*X6DH8) SCSI CH A LED (DA1)/SCSI CH B LED(DA2)

1-6

Introduction

X6DH8-XG2/X6DHE-XG2 User's Manual

Motherboard Features

CPU

• Single or dual Intel® 604-pin NoconaTM (w/EM64T) processors at 800 MHz front side (system) bus speed. (*Notes: CPU FSB speed is set by

Manufacturer. Please do not change the FSB setting. Please refer to the support section of our web site for a complete listing of supported processors (http://www.supermicro.com/ products/.)

Memory

• Eight 240-pin DIMM sockets supporting up to 16 GB Registered ECC DDR2-400 (PC3200) SDRAM

Notes: 1. Memory size is set via BIOS. 2. Interleaved memory; requires memory modules to be installed in pairs. See Section 2-3 for details.

Chipset

• Intel E7520 Lindenhurst chipset

Expansion Slots

• X6DH8-XG2/X6DHE-XG2 One PCI-E slot (x8@4GB/sec)

Five 64-bit PCI-X slots (*Three PCI-X-133 slots, One PCI-X-100 slot, One

PCI-X-100 w/ZCR suport)

BIOS

• 8 Mb Phoenix® Flash ROM

• DMI 2.1, PCI 2.2, ACPI 2.0, Plug and Play (PnP), SMBIOS 2.3

PC Health Monitoring

• Onboard voltage monitors for CPU cores, chipset voltage, 3.3V, +5V, +12V and 3.3V standby

• Fan status monitor with firmware/software on/off control

• CPU/chassis temperature monitors

• Environmental temperature monitor and control

• CPU fan auto-off in sleep mode (S1 is not supported.)

• CPU slow-down on temperature overheat

• CPU thermal trip support for processor protection, +5V standby alert LED

• Power-up mode control for recovery from AC power loss

Chapter 1: Introduction

1-7

Introduction

• System overheat LED and control

• Chassis intrusion detection

• System resource alert

ACPI Features (optional)

• Microsoft OnNow

• Slow blinking LED for suspend state indicator

• Main switch override mechanism

Onboard I/O

• Support Adaptec 7902 dual channel Ultra 320 SCSI(*X6DH8-XG2 only)

• One IPMI 2.0 socket

• Intel 82546 dual Channel Gigabit Ethernet controller (PCI-X-133)

• 2 EIDE Ultra DMA/100 bus master interfaces

• 1 floppy port interface (up to 2.88 MB)

• PS/2 mouse and PS/2 keyboard ports

• Up to 5 USB 2.0 (Universal Serial Bus) (3 Front Panel USB ports, 2 Back Panel USB Headers)

• Super I/O

• 2 COM ports (1 header, 1 port)

• 2 SATA ports support 2 drives (RAID 0, 1)

Other

• Internal/external modem ring-on (WOR)

• Wake-on-LAN (WOL)

• Console redirection

• SMBbus for SMC Power Supply

• Fan Speed Control via BIOS

CD/Diskette Utilities

• BIOS flash upgrade utility and device drivers

Dimensions

• ATX Ext. 12" x 13.05" (304.8 x 331.5 mm)

1-8

Introduction

X6DH8-XG2/X6DHE-XG2 User's Manual

MCH

NOCONA PROCESSOR#2VRM

CLOCK

ADDR

CTRL

DATA

NOCONA PROCESSOR#1

ADDR

CTRL

DATA

ADDR

CTRL

ICH5R

HUB

DDRII-400

PCI BUS(32 -BIT)

DIMMs

IDE

PRI/SEC

UDMA/100

VGA

DIMMs

SATA

LPC BU SUSB

BMC CON. FWHLPC I/O

Mouse

Floppy

H/WCOM1

COM2 MONITOR

4 DDR II - 400

DDRII-400

A

X8

PCI EXP. B X8

B

PCI EXP. C

PCI EXP. AAX8

PXH #1

B

PCI-EXP SLOT

PXH #2

PCIEXP1

PCI-X BUS(133 MHZ)

PCI-X BUS(100 MHZ)

AIC7902W

SCSI

PCI2

SLOT

1 PCI-X

SLOT PCI1

SLOT

1 PCI-X

PCI3

Gbit LAN

ANVIK

82546EB

IDSEL:PXH2_ PBAD17

IDSEL:PXH2_ PAAD17

IDSEL:PXH1_ PBAD18

IDSEL:PXH1_ PBAD17

IDSEL:PXH1_ PAAD19

SLOT

1 PCI-X

PCI4

U24

U62

U4E1

U6

CPU1

CPU2

U16 X3P1

U10

SLOT

1 PCI-X

PCI5

USB Ports 0-4

Figure 1-9. Block Diagram of the E7520 Lindenhurst Chipset

Note: This is a general block diagram. Please see the previous Motherboard

Features pages for details on the features of each motherboard.

Chapter 1: Introduction

1-9

Introduction

1-2 Chipset Overview

Built upon the functionality and the capability of the E7520 Lindenhurst chipset, The X6DH8-XG2/X6DHE-XG2 motherboard provides the performance and feature set required for dual processor-based servers, with configuration options optimized for communications, presentation, storage, computation or database applications. The Intel E7520 Lindenhurst chipset consists of the following components: the Lindenhurst Memory Controller Hub (MCH), the 82801ER I/O Controller Hub 5-R (ICH5-R), and the PCI-X Hub.

The E7520 Lindenhurst MCH supports single or dual Nocona processors with Front Side Bus speeds of up to 800 MHz(*Note). Its memory controller provides direct connection to two channels of registered DDR2 400 with a marched system bus address and data bandwidths of up to 6.4GB/s. The Lindenhurst also supports the new PCI Express high speed serial I/O interface for superior I/O bandwidth. The MCH provides three configurable x8 PCI Express interfaces which may alternatively be configured as two independent x4 PCI Express interfaces. These interfaces support connection of the MCH to a variety of other bridges that are compliant with the PCI Express Interface Specification, Rev. 1.0a. The MCH interfaces with the 82801ER I/O Controller Hub 5-R (ICH5R) via a dedicated Hub Interface supporting a peak bandwidth of 266 MB/s using a x4 base clock of 66 MHz. The PXH provides connection between a PCI Express interface and two independent PCI bus interfaces that can be configured for standard PCI 2.3 protocol, as well as the enhanced high-frequency PCI-X protocol. The PXH can be configured to support for 64-bit PCI devices running at 33 MHz, 66 MHz, 100 MHz, and 133 MHz.

The ICH5R I/O Controller Hub provides legacy support similar to that of previous ICH-family devices, but with extensions in RAID 0,1 support, Serial ATA Technology, and an integrated ASF Controller. In addition, the ICH5R also provides various integrated functions, including a two-channel Ultra ATA/100 bus master IDE controller, USB 2.0 host controllers, an integrated 10/100 LAN controller, an LPC firmware hub (FWH) and Super IO interface, a System Management Interface, a power management interface, integrated IOxAPIC and 8259 interrupt controllers.

(*Notes: The CPU FSB speed is set at 800 MHz by the Manufacturer.

Please do not change the CPU FSB setting.)

1-10

Introduction

X6DH8-XG2/X6DHE-XG2 User's Manual

1-3 Special Features

Recovery from AC Power Loss

BIOS provides a setting for you to determine how the system will respond when AC power is lost and then restored to the system. You can choose for the system to remain powered off (in which case you must hit the power switch to turn it back on) or for it to automatically return to a poweron state. See the Power Lost Control setting in the Advanced BIOS Setup section (Peripheral Device Configuration) to change this setting. The default setting is Always On.

1-4 PC Health Monitoring

This section describes the PC health monitoring features of the X6DH8-XG2/ X6DHE-XG2. All have an onboard System Hardware Monitor chip that supports PC health monitoring.

Onboard Voltage Monitors for the CPU Cores, Chipset Voltage, +3.3V, +5V, +12V and +3.3V Standby

An onboard voltage monitor will scan these voltages continuously. Once a voltage becomes unstable, a warning is given or an error message is sent to the screen. Users can adjust the voltage thresholds to define the sensitivity of the voltage monitor.

Fan Status Monitor with Firmware/Software On/Off Control

The PC health monitor can check the RPM status of the cooling fans. The onboard CPU and chassis fans are controlled by the power management functions. The thermal fan is controlled by the overheat detection logic.

Environmental Temperature Control

The thermal control sensor monitors the CPU temperature in real time and will turn on the thermal control fan whenever the CPU temperature exceeds a user-defined threshold. The overheat circuitry runs independently from the CPU. It can continue to monitor for overheat conditions even when the CPU is in sleep mode. Once it detects that the CPU temperature is too high, it will automatically turn on the thermal control fan to prevent any overheat

Chapter 1: Introduction

1-11

Introduction

damage to the CPU. The onboard chassis thermal circuitry can monitor the overall system temperature and alert users when the chassis temperature is too high.

CPU Fan Auto-Off in Sleep Mode

The CPU fan activates when the power is turned on. It continues to operate when the system enters Standby mode. When in sleep mode, the CPU will not run at full power, thereby generating less heat.

CPU Overheat LED and Control

This feature is available when the user enables the CPU overheat warning function in the BIOS. This allows the user to define an overheat temperature. When this temperature is exceeded, both the overheat fan and the warning LED are triggered.

System Resource Alert

This feature is available when used with Supero Doctor III in the Windows OS environment or used with Supero Doctor II in Linux. LDCM is used to notify the user of certain system events. For example, if the system is running low on virtual memory and there is insufficient hard drive space for saving the data, you can be alerted of the potential problem.

1-5 ACPI Features

ACPI stands for Advanced Configuration and Power Interface. The ACPI specification defines a flexible and abstract hardware interface that provides a standard way to integrate power management features throughout a PC system, including its hardware, operating system and application software. This enables the system to automatically turn on and off peripherals such as CD-ROMs, network cards, hard disk drives and printers. This also includes consumer devices connected to the PC such as VCRs, TVs, telephones and stereos.

In addition to enabling operating system-directed power management, ACPI provides a generic system event mechanism for Plug and Play and an operating system-independent interface for configuration control. ACPI leverages the Plug and Play BIOS data structures while providing a processor

1-12

Introduction

X6DH8-XG2/X6DHE-XG2 User's Manual

architecture-independent implementation that is compatible with both Windows 2000 and Windows NT 5.0.

Microsoft OnNow

The OnNow design initiative is a comprehensive, system-wide approach to system and device power control. OnNow is a term for a PC that is always on but appears to be off and responds immediately to user or other requests.

Slow Blinking LED for Suspend-State Indicator

When the CPU goes into a suspend state, the chassis power LED will start blinking to indicate that the CPU is in suspend mode. When the user presses any key, the CPU will wake-up and the LED will automatically stop blinking and remain on.

Main Switch Override Mechanism

When an ATX power supply is used, the power button can function as a system suspend button to make the system enter a SoftOff state. The monitor will be suspended and the hard drive will spin down. Depressing the power button again will cause the whole system to wake-up. During the SoftOff state, the ATX power supply provides power to keep the required circuitry in the system alive. In case the system malfunctions and you want to turn off the power, just depress and hold the power button for 4 seconds. This option can be set in the Power section of the BIOS Setup routine.

External Modem Ring-On

Wake-up events can be triggered by a device such as the external modem ringing when the system is in the SoftOff state. Note that external modem ring-on can only be used with an ATX 2.01 (or above) compliant power supply.

Chapter 1: Introduction

1-13

Introduction

Wake-On-LAN (WOL)

Wake-On-LAN is defined as the ability of a management application to remotely power up a computer that is powered off. Remote PC setup, updates and asset tracking can occur after hours and on weekends so that daily LAN traffic is kept to a minimum and users are not interrupted. The motherboard has a 3-pin header (WOL) to connect to the 3-pin header on a Network Interface Card (NIC) that has WOL capability. Wake-On-LAN must be enabled in BIOS. Note that Wake-On-LAN can only be used with an ATX

2.01 (or above) compliant power supply.

1-6 Power Supply

As with all computer products, a stable power source is necessary for proper and reliable operation. It is even more important for processors that have high CPU clock rates.

The X6DH8-XG2/X6DHE-XG2 accommodates ATX power supplies. Although most power supplies generally meet the specifications required by the CPU, some are inadequate. You should use one that will supply at least 400W of power and includes the additional +12V, 4-pin power connector - an even higher wattage power supply is recommended for high-load configurations. Also your power supply must supply 1.5A for the Ethernet ports.

NOTE: A 12V 8-pin power connector (JPW3) is required for CPU power support, and additional 12 V 4-pin power connector (JPW2) is also required to supplement system power consumption. Failure to provide this extra power will result in instability of the CPU after only a few minutes of operation. See Section 2-5 for details on connecting the power supply.

It is strongly recommended that you use a high quality power supply that meets ATX power supply Specification 2.02 or above. It must also be SSI compliant (info at http://www.ssiforum.org/). Additionally, in areas where noisy power transmission is present, you may choose to install a line filter to shield the computer from noise. It is recommended that you also install a power surge protector to help avoid problems caused by power surges.

1-14

Introduction

X6DH8-XG2/X6DHE-XG2 User's Manual

1-7 Super I/O

The disk drive adapter functions of the Super I/O chip include a floppy disk drive controller that is compatible with industry standard 82077/765, a data separator, write pre-compensation circuitry, decode logic, data rate selection, a clock generator, drive interface control logic and interrupt and DMA logic. The wide range of functions integrated onto the Super I/O greatly reduces the number of components required for interfacing with floppy disk drives. The Super I/O supports 360 K, 720 K, 1.2 M, 1.44 M or 2.88 M disk drives and data transfer rates of 250 Kb/s, 500 Kb/s or 1 Mb/s.It also provides two high-speed, 16550 compatible serial communication ports (UARTs), one of which supports serial infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable baud rate generator, complete modem control capability and a processor interrupt system. Both UARTs provide legacy speed with baud rate of up to 115.2 Kbps as well as an advanced speed with baud rates of 250 K, 500 K, or 1 Mb/s, which support higher speed modems.

The Super I/O provides functions that comply with ACPI (Advanced Configuration and Power Interface), which includes support of legacy and ACPI power management through an SMI or SCI function pin. It also features auto power management to reduce power consumption.

The IRQs, DMAs and I/O space resources of the Super I/O can flexibly adjust to meet ISA PnP requirements, which support ACPI and APM (Advanced Power Management).

Chapter 2: Installation

2-1

Chapter 2

Installation

2-1 Static-Sensitive Devices

Electric-Static-Discharge (ESD) can damage electronic components. To prevent damage to your system board, it is important to handle it very carefully. The following measures are generally sufficient to protect your equipment from ESD.

Precautions

• Use a grounded wrist strap designed to prevent static discharge.

• Touch a grounded metal object before removing the board from the antistatic bag.

• Handle the board by its edges only; do not touch its components, peripheral chips, memory modules or gold contacts.

• When handling chips or modules, avoid touching their pins.

• Put the motherboard and peripherals back into their antistatic bags when not in use.

• For grounding purposes, make sure your computer chassis provides excellent conductivity between the power supply, the case, the mounting fasteners and the motherboard.

• Use only the correct type of onboard CMOS battery. Do not install the onboard upside down battery to avoid possible explosion.

Unpacking

The motherboard is shipped in antistatic packaging to avoid static damage. When unpacking the board, make sure the person handling it is static protected.

2-2

X6DH8-XG2/X6DHE-XG2 User's Manual

IMPORTANT: Always connect the power cord last and always remove it before adding, removing or changing any hardware components. Make sure that you install the processor into the CPU socket before you install the CPU (CEK) heat sink. To adequately support the weight of CPU heat sinks, please install the X6DH8-XG2/X6DHE-XG2 in a chassis that is compliant with the SSI EEB 3.5 Specification.

2-2 Processor and Heatsink Installation

When handling the processor package, avoid placing direct pressure on the label area of the fan. Also, do not place the motherboard on a conductive surface, which can damage the BIOS battery and prevent the system from booting up.

!

CPU Installation

1. Lift the lever on the CPU socket:

lift the lever completely as shown on the picture on the right; otherwise, you will damage the CPU socket when power is applied. (Install CPU1 first.)

Socket lever Pin1

2. Insert the CPU in the socket, making sure that pin 1 of the CPU aligns with pin 1 of the socket (both corners are marked with a triangle). When using only one CPU, install it into CPU socket #1 (socket #2 is automatically disabled if only one CPU is used).

3. Press the lever down until you hear the *click* so you can be sure that the CPU is securely installed in the CPU socket.

Pin 1

Socket lever in the locking Position

Chapter 2: Installation

2-3

Screw#3

Heatsink Installation

1. Do not apply any thermal compound

to the heatsink or the CPU die-the required amount has already been applied.

2. Place the heatsink on top of the CPU

so that the four mounting holes are aligned with those on the retention mechanism.

3. Screw in two diagonal screws (ie the

#1 and the #2 screws) until just snug (do not fully tighten the screws to avoid possible damage to the CPU.)

4. Finish the installation by fully tightening

all four screws.

Screw#1

Screw#2

Screw#1

Intel CEK Heatsink

Screw#4

Screw#2

(Caution! We do not recommend that the CPU or the heatsink be removed. However, if you do need to un-install the heatsink, please follow the instructions below to remove the heatsink to prevent damage done to the CPU or the CPU socket. )

1. Unscrew and remove the heatsink

screws from the motherboard in the sequence as show in the picture on the right.

2. Hold the heatsink as show in the picture

on the right and gently wriggle the heatsink to loosen it from the CPU. (Do not use excessive force when wriggling the heatsink!!)

3. Once the CPU is loosened from the

heatsink, remove the heatsink from the CPU socket.

4. Clean the surface of the CPU and the

heatsink to get rid of the old thermal grease. Reapply the proper amount of thermal grease on the surface before you reinstall the CPU and the heatsink.

Heatsink Removal

2-4

X6DH8-XG2/X6DHE-XG2 User's Manual

Figure 2-1. PGA 604 Socket: Empty and with Processor Installed

Mounting the Motherboard in the Chassis

All motherboards have standard mounting holes to fit different types of chassis. Make sure the location of all the mounting holes for both the motherboard and the chassis match. Although a chassis may have both plastic and metal mounting fasteners, metal ones are highly recommended because they ground the motherboard to the chassis. Make sure the metal standoffs click in or are screwed in tightly. Then use a screwdriver to secure the motherboard onto the motherboard tray.

Lever

Processor

(installed)

Triangle

Empty socket

Warning! Make

sure you lift the lever completely when installing the CPU. If the lever is only partly raised, damage to the socket or CPU may result.

!

Chapter 2: Installation

2-5

Figure 2-2. Installing and Removing DIMMs

To Install:

Insert module vertically and press down until it snaps into place. Pay attention to the alignment notch at the bottom.

2-3 Installing DIMMs

Note: Check the Supermicro web site for recommended memory modules:

http://www.supermicro.com/TECHSUPPORT/FAQs/Memory_vendors.htm

CAUTION

Exercise extreme care when installing or removing DIMM

modules to prevent any possible damage. Also note that the

memory is interleaved to improve performance (see step 1).

DIMM Installation (See Figure 2-2)

1. Insert the desired number of DIMMs into the memory slots, starting with

Bank 0. The memory scheme is interleaved so you must install two modules at a time, beginning with Bank 1, then Bank 2, and so on.

2. Insert each DIMM module vertically into its slot. Pay attention to the

notch along the bottom of the module to prevent inserting the DIMM module incorrectly.

3. Gently press down on the DIMM module until it snaps into place in the

slot. Repeat for all modules (see step 1 above).

Memory Support

The X6DH8-XG2/X6DHE-XG2 supports up to 16 GB of Registered DDR2-400 (PC3200) memory. All motherboards were designed to support 2 GB modules in each slot, but has only been verified for up to 1 GB modules.

Note: Notch

should align

with the

receptive point

on the slot

Notch

Release

Tab

Release

Tab

DDRII

2-6

X6DH8-XG2/X6DHE-XG2 User's Manual

To Remove:

Use your thumbs to gently push near the edge of both ends of the module. This should release it from the slot.

2-4 I/OPorts/Control Panel Connectors

The I/O ports are color coded in conformance with the PC 99 specification. See Figure 2-3 below for the colors and locations of the various I/O ports.

Figure 2-3. I/O Port Locations and Definitions

Video

II

Chapter 2: Installation

2-7

Front Control Panel

JF1 contains header pins for various buttons and indicators that are normally located on a control panel at the front of the chassis. These connectors are designed specifically for use with Supermicro server chassis. See Figure 2-4 for the descriptions of the various control panel buttons and LED indicators. Refer to the following section for descriptions and pin definitions.

Figure 2-4. JF1 Header Pins

Power Button

OH/Fan Fail LED

1

NIC1 LED

Reset Button

2

Power Fail LED

HDD LED

Power LED

Reset

Pwr

Vcc

Ground

1920

Vcc

X

Ground

NMI

X

NIC2 LED

Vcc

2-8

X6DH8-XG2/X6DHE-XG2 User's Manual

ATX Power Supply 24-pin Connector

Pin Definitions (JPW1)

Pin Number Definition 13 +3.3V 14 -12V 15 COM 16 PS_ON# 17 COM 18 COM 19 COM 20 Res(NC) 21 +5V 22 +5V 23 +5V 24 COM

Pin Number Definition

1 +3.3V 2 +3.3V 3 COM

4 +5V

5 COM

6 +5V

7 COM

8 PWR_OK 9 5VSB 10 +12V 11 +12V 12 +3.3V

2-5 Connecting Cables

ATX Power Connector

The main power supply connector on the X6DH8-XG2/X6DHE-XG2 meets the SSI (Superset ATX) 24pin specification. You must also connect the 4-pin (JPW2) power connector to your power supply to provide adequate power supply for system power consumption. See the table on the right for pin definitions.

Pins

1 thru 4 5 thru 8

Definition

Ground

+12v

+12v 8-Pin Power Supp

ly

Connector (J1D1)

Processor Power Connector

In addition to the Primary ATX and the Auxiliary power connectors (above), the 12v 8-pin Processor connector at JPW3 must also be connected to your power supply for CPU power consumption.

Pins #

1 & 2 3 & 4

Definition

Ground

+12 V

+12V 4-pin Connector

(JPW2)

GLAN1

®

S

U

P

E

R

X

6

D

H

8

-X

G

2

GLAN2

D

IM

M

2

B

( B

a

n

k

2

)

D

IM

M

2

A

( B

a

n

k

2

)

D

IM

M

3

B

( B

a

n

k

3

)

D

IM

M

3

A

( B

a

n

k

3

)

D

IM

M

4

B

( B

a

n

k

4

)

D

IM

M

4

A

( B

a

n

k

4

)

D

IM

M

1

A

( B

a

n

k

1

)

D

IM

M

1

B

(B

a

n

k

1

)

Fan1

8-pin PWR

PWR SMBus

CPU Fan1

JF1

F

P

C

o

n

tr

o

l

JD

1

S

P

K

PW LED

JP15

Fan2

OH

3rd PS

PWR

Fault

Detect

CPU F an2

Fan3

CH In tru

JL1

WD Enab le

IPMI

IDE1

ID

E

2

F

lo

p

y

BIOS

J18

JPA1

Ultr a 32 0

S

C

S

I C

H

A

U

lt

r

a

3

2

0

S

C

S

I

C

H

B

F

a

n

4

790 2

CTR L

SATA0

SATA1

USB2/ 3

SMBUS

P

C

I-X

1

0

M

H

z

Z

C

R

P

C

I-

X

2

1

0

M

H

z

P

C

I-X

#

3

1

3

M

H

z

WOR

Batte ry

JPL1

GLA N CTL R

RAGE-X

825 46

GLA N Enable

P

C

I-X

#

5

1

3

M

H

z

X

8

P

C

I-

E

p

x

#

6

Super

I/O

(Nor th Bridge )

JPG1

VGA

C

O

M

1

U

S

B

0/1

KB/ Mouse

Fan5

Fan6

ATX PWR

4-Pin PWR

JP16

24-Pin

Force P WR ON

VGA Enable

Fan7

J24

J

P

1

2

Rebo ot

Option

JP14

J

P

13

Fan8

SCSI

CPU 1

CPU 2

A

la

rm

R

e

s

et

SCSI Enable

PXH

P

C

I-X

#

4

1

3

M

H

z

COM2

WOL

USB 4

P

W

R

F

a

u

lt

LE1

PW LED

JPA2 JPA3

DA1

D

A

2

ICH 5R

PXH

L

in

d

e

n

h

u

r

s

t

Clea r CMOS

C

H

B

S

C

S

I L

E

D

C

H

A

S

C

S

I L

E

D

(South Bridge )

E752 0

82801ER

S

C

S

I C

H

A

T

e

rm

S

C

S

I C

H

B

T

e

rm

24-pinPWR

8-Pin PWR

(*Required)

(*

Required)

4-Pin PWR

Chapter 2: Installation

2-9

Pow er Button

OH/Fan Fail LED

1

NIC1 LED

Reset Button

2

Power Fail LED

HDD LED

Power LED

Reset

Pwr

Vcc

Ground

1920

Vcc

X

Ground

NMI

X

NIC2 L ED

Vcc

Power LED

The Power LED connection is located on pins 15 and 16 of JF1. Refer to the table on the right for pin definitions.

NMI Button

The non-maskable interrupt button header is located on pins 19 and 20 of JF1. Refer to the table on the right for pin definitions.

Number

19 20

Definition

Control

Ground

NMI Button Pin

Definitions (JF1)

Number

15 16

Definition

Vcc

Control

PWR_LED Pin Definitions

(JF1)

GLAN1

®

S

U

P

E

R

X

6D

H

8-X

G

2

GLAN2

D

IM

M

2

B

(B

a

n

k

2

)

D

IM

M

2

A

(B

a

n

k

2

)

D

IM

M

3

B

(B

a

n

k

3

)

D

IM

M

3

A

(B

a

n

k

3

)

D

IM

M

4

B

(B

a

n

k

4

)

D

IM

M

4

A

(B

a

n

k

4)

D

IM

M

1

A

(B

a

n

k

1)

D

IM

M

1

B

(B

a

n

k 1

)

Fan1

8-pin PWR

PWR SMBus

CPU Fan1

JF1

F

P

C

o

n

tr

o

l

JD1

S

P

K

PW LED

J

P

1

5

Fan2

OH

3rd PS

PWR

Fault

Detect

CPU Fan2

Fan3

CH Intru

JL1

WD Enable

IPMI

IDE1

ID

E

2

F

lo

p

y

BIOS

J18

JPA1

Ultra 320

SCSI CH A

U

ltr

a

3

2

0

S

C

S

I

C

H

B

F

an4

7902

CTRL

SATA0

SATA1

USB2/3

SMBUS

Buzzer

P

C

I-X

1

0

M

H

z

Z

C

R

P

C

I-X

2

1

0

M

H

z

P

C

I-X

#

3

1

3

M

H

z

WOR

Battery

JPL1

GLAN CTLR

RAGE-X

82546

GLAN Enable

P

C

I-X

#

5

1

3

M

H

z

X

8

P

C

I-E

p

x

#

6

Super

I/O

(North Bridge)

JPG1

VGA

COM1

USB0/1

KB/ Mouse

Fan5

Fan6

ATX PWR

4-Pin PWR

JP16

24-Pin

Force PWR ON

VGA Enable

Fan7

J24

J

P

1

2

Reboot

Option

JP14

JP

13

Fan8

SCSI

CPU 1

CPU 2

A

larm

R

eset

SCSI Enable

PXH

P

C

I-X

#

4

1

3

M

H

z

COM2

WOL

USB4

P

W

R

F

a

u

lt

LE1

PW LED

JPA2 JPA3

DA1

D

A

2

ICH5R

PXH

L

in

d

e

n

h

u

r

s

t

Clear CMOS

C

H

B

S

C

S

I L

E

D

C

H

A

S

C

S

I L

E

D

(South

Bridge)

E7520

82801ER

S

C

S

I C

H

A

T

e

r

m

S

C

S

I C

H

B

T

e

r

m

NMI

PWR LED

2-10

X6DH8-XG2/X6DHE-XG2 User's Manual

Pow er Button

OH/Fan Fail LED

1

NIC1 LED

Reset Button

2

Power Fail LED

HDD LED

Power LED

Reset

Pwr

Vcc

Ground

1920

Vcc

X

Ground

NMI

X

NIC2 L ED

Vcc

NIC1/NIC2 LED Indicators

The NIC (Network Interface Controller) LED connections for the GLAN Port1 is located on pins 11 and 12 of JF1, and for the GLAN Port2 is located on pins 9 and 10 of JF1. Attach the NIC LED cables to display network activity. Refer to the tables on the right for pin definitions.

NIC1 LED Pin

Definitions

(JF1)

Number

11 12

Definition

Vcc

GND

HDD LED

The HDD LED connection is located on pins 13 and 14 of JF1. Attach the hard drive LED cable here to display disk activity (for any hard drives on the system, including SCSI, Serial ATA and IDE). See the table on the right for pin definitions.

HDD LED Pin

Definitions

(JF1)

Number

13 14

Definition

Vcc

HD Active

NIC2 LED Pin

Definitions

(JF1)

Number

9

10

Definition

Vcc

GND

GLAN1

®

S

UPER X6DH8-XG2

GLAN2

D

IM

M

2

B

(B

an

k

2

)

D

IM

M

2

A

(B

an

k

2

)

D

IM

M

3

B

(B

a

n

k

3

)

D

IM

M

3

A

(B

an

k

3)

D

IM

M

4

B

(B

a

n

k

4

)

D

IM

M

4

A

(B

a

n

k 4

)

D

IM

M

1A

(B

a

n

k

1)

D

IM

M

1B

(B

a

n

k

1

)

Fan1

8-pin PWR

PWR SMBus

CPU Fan1

JF1

FP Control

J

D

1

SPK

PW LED

J

P

1

5

Fan2

OH

3rd PS

PWR

Fault

Detect

CPU Fan2

Fan3

CH Intru

JL1

WD Enable

IPMI

IDE1

IDE2

Floppy

BIOS

J

1

8

JPA1

Ultra 320

S

C

S

I C

H

A

Ultra 320

S

C

S

I C

H

B

F

a

n

4

7902

CTRL

SATA0

SATA1

USB2/3

SMBUS

Buzzer

PCI-X 1 100 MHz ZCR

PCI-X 2 100 MHz

PCI-X #3 133 MHz

WOR

Battery

JPL1

GLAN CTLR

RAGE-X

82546

GLAN Enable

PCI-X #5 133MHz

X8 PCI-Epx #6

S

u

p

e

r

I/O

(North Bridge)

JPG1

VGA

C

O

M

1

U

S

B

0

/1

KB/ Mouse

Fan5

Fan6

ATX PWR

4-Pin PWR

JP16

24-Pin

Force PWR ON

VGA Enable

Fan7

J24

JP12

R

e

b

o

t

O

p

t

io

n

JP14

JP13

Fan8

SCSI

CPU 1

CPU 2

A

la

rm

R

e

s

e

t

SCSI Enable

PXH

PCI-X #4 133MHz

COM2

WOL

USB4

PWR Fault

LE1

PW LED

JPA2 JPA3

DA1

D

A

2

ICH5R

PXH

Lindenhurst

Clear CMOS

C

H

B

S

C

S

I L

E

D

C

H

A

S

C

S

I L

E

D

(South Bridge)

E

7

5

2

0

8

2

8

0

1

E

R

S

C

S

I C

H

A

T

e

rm

S

C

S

I C

H

B

T

e

rm

HDD

NIC1/NIC2 LED

Chapter 2: Installation

2-11

Pow er Button

OH/Fan Fail LED

1

NIC1 LED

Reset Button

2

Power Fail LED

HDD LED

Power LED

Reset

Pwr

Vcc

Ground

1920

Vcc

X

Ground

NMI

X

NIC2 L ED

Vcc

Overheat/FanFail LED

Connect an LED to the OH/Fan Fail connection on pins 7 and 8 of JF1 to provide advanced warning of chassis overheating or system fan failure. Refer to the table on the right for pin definitions.

Power Fail LED

The Power Fail LED connection is located on pins 5 and 6 of JF1. Refer to the table on the right for pin definitions.

OH/Fan Fail LED

Pin Definitions

(JF1)

Number

7 8

Definition

Vcc

GND

Power Fail LED Pin

Definitions

(JF1)

Number

5 6

Definition

Vcc

GND

GLAN1

®

S

UPER X6DH8-XG2

GLAN2

D

IM

M

2

B

(B

a

n

k

2

)

D

IM

M

2

A

(B

a

n

k

2

)

D

IM

M

3

B

(B

a

n

k

3

)

D

IM

M

3

A

(B

a

n

k

3

)

D

IM

M

4

B

(B

a

n

k

4

)

D

IM

M

4

A

(B

a

n

k

4

)

D

IM

M

1

A

(B

a

n

k

1

)

D

IM

M

1

B

(B

a

n

k

1

)

Fan1

8-pin PWR

PWR SMBus

CPU Fan1

JF1

FP Control

J

D

1

SPK

PW LED

J

P

1

5

Fan2

OH

3rd PS

PWR

Fault

Detect

CPU Fan2

Fan3

CH Intru

JL1

W

D

Enable

IPM

I

IDE1

IDE2

Floppy

BIO

S

J

1

8

JPA1

Ultra 320

S

C

S

I C

H

A

Ultra 320

S

C

S

I C

H

B

F

a

n

4

7902

C

TRL

SATA0

SATA1

US

B2/3

SM

BUS

Buzzer

PCI-X 1 100 MHz ZCR

PCI-X 2 100 MHz

PCI-X #3 133 MHz

WOR

Battery

JPL1

GLAN CTLR

RAGE-X

82546

GLAN Enable

PCI-X #5 133MHz

X8 PCI-Epx #6

Super

I/O

(North Bridge)

JPG

1

VG

A

C

O

M

1

U

S

B

0

/1

KB/ M

ouse

Fan5

Fan6

ATX PW

R

4-Pin PW

R

JP16

24-Pin

Force PWR ON

VG

A

Enable

Fan7

J24

JP12

R

e

b

o

t

O

p

tio

n

JP14

JP13

Fan8

SCSI

CPU 1

CPU 2

A

larm

R

eset

SCSI Enable

PXH

PCI-X #4 133MHz

CO

M

2

W

O

L

USB4

PWR Fault

LE1

PW LED

JPA2 JPA3

DA1

D

A

2

ICH5R

PXH

Lindenhurst

Clear CMOS

C

H

B

S

C

S

I L

E

D

C

H

A

S

C

S

I L

E

D

(South Bridge)

E7520

82801E

R

S

C

S

I C

H

A

T

e

rm

S

C

S

I C

H

B

T

e

rm

OH/Fan Fail LED

PWR Fail LED

OH/Fan Fail LED

(JF1)

State

Off

Stay On

Blink

Message

Normal

Overheat

Fan Fail

2-12

X6DH8-XG2/X6DHE-XG2 User's Manual

Pow er Button

OH/Fan Fail LED

1

NIC1 LED

Reset Button

2

Power Fail LED

HDD LED

Power LED

Reset

Pwr

Vcc

Ground

1920

Vcc

X

Ground

NMI

X

NIC2 L ED

Vcc

GLAN1

®

S

UPER X6DH8-XG2

GLAN2

DIMM 2B (Bank 2)

DIMM 2A (Bank 2)

DIMM 3B (Bank 3)

DIMM 3A (Bank 3)

DIMM 4B (Bank 4)

DIMM 4A (Bank 4)

DIMM 1A (Bank 1)

DIMM 1B (Bank 1)

Fan1

8-pin PWR

PWR SMBus

C

P

U

F

a

n

1

JF1

FP Control

J

D

1

SPK

PW LED

J

P

1

5

Fan2

OH

3rd PS

PWR

Fault

Detect

C

P

U

F

a

n

2

Fan3

C

H

In

tr

u

J

L

1

W

D

E

n

a

b

le

IP

M

I

IDE1

IDE2

Floppy

B

IO

S

J

1

8

J

P

A

1

Ultra 320

SCSI CH

A

U

ltra 320

S

C

S

I C

H

B

Fan4

7

9

0

2

C

T

R

L

S

A

T

A

0

S

A

T

A

1

U

S

B

2

/3

S

M

B

U

S

B

u

z

e

r

P

CI-X 1 100 M

H

z ZC

R

P

C

I-X 2 100 M

H

z

P

C

I-X

#3 133 M

H

z

WOR

B

a

tte

r

y

J

P

L

1

G

L

A

N

C

T

L

R

A

G

E

-X

8

2

5

4

6

G

L

A

N

E

n

a

b

le

P

C

I-X #5 133M

H

z

X

8 P

C

I-E

px #6

S

u

p

e

r

I/O

(N

o

rth

B

rid

g

e

)

J

P

G

1

V

G

A

C

O

M

1

U

S

B

0

/1

K

B

/

M

o

u

s

e

F

a

n

5

F

a

n

6

A

T

X

P

W

R

4

-P

in

P

W

R

JP16

2

4

-P

in

Force PWR ON

V

G

A

E

n

a

b

le

F

a

n

7

J24

JP12

R

e

b

o

t

O

p

tio

n

JP14

JP13

Fan8

SCSI

C

P

U

1

C

P

U

2

A

la

rm

R

e

s

e

t

SCSI Enable

P

X

H

PC

I-X

#4 133M

H

z

C

O

M

2

W

O

L

U

S

B

4

P

W

R

F

a

u

lt

LE1

PW LED

J

P

A

2

J

P

A

3

DA1

D

A

2

IC

H

5

R

P

X

H

Lindenhurst

Clear CMOS

C

H

B

S

C

S

I L

E

D

C

H

A

S

C

S

I L

E

D

(S

o

u

th

B

r

id

g

e

)

E

7

5

2

0

8

2

8

0

1

E

R

S

C

S

I C

H

A

T

e

rm

S

C

S

I C

H

B

T

e

rm

Power Button

The Power Button connection is located on pins 1 and 2 of JF1. Momentarily contacting both pins will power on/off the system. This button can also be configured to function as a suspend button (with a setting in BIOS - see Chapter 4). To turn off the power when set to suspend mode, depress the button for at least 4 seconds. Refer to the table on the right for pin definitions.

Number

1 2

Definition

PW_ ON

Ground

Power Button

Connector

Pin De finitions

(JF1)

Reset Button

The Reset Button connection is located on pins 3 and 4 of JF1. Attach it to the hardware reset switch on the computer case. Refer to the table on the right for pin definitions.

Number

3 4

Definition

Reset

Ground

Reset Pin

Definitions

(JF1)

PWR Button

Reset Button

Chapter 2: Installation

2-13

Universal Serial Bus (USB0/1)

Two USB 2.0 ports (JPUSB1) are located beside the PS/2 keyboard/ mouse ports. USB0 is the bottom connector and USB1 is the top connector. See the table on the right for pin definitions.

Universal Serial Bus Pin Definitions

Pin Number Definition 1+5V 2P0 3P0+ 4 Ground 5 N/A

Pin Number Definitio

n

1+5V 2P0 3P0+ 4 Ground 5Key

USB0

USB1

Chassis Intrusion

A Chassis Intrusion header is located at JL1. Attach the appropriate cable to inform you of a chassis intrusion.

GLAN1

®

S

UPER X6DH8-XG2

GLAN2

D

IM

M

2

B

(B

a

n

k

2

)

D

IM

M

2

A

(B

a

n

k

2)

D

IM

M

3

B

(B

a

n

k

3

)

D

IM

M

3

A

(B

an

k

3

)

D

IM

M

4

B

(B

a

n

k

4

)

D

IM

M

4

A

(B

an

k

4

)

D

IM

M

1A

(B

a

n

k

1

)

D

IM

M

1

B

(B

a

n

k

1

)

Fan1

8-pin PWR

PWR SMBus

CPU Fan1

JF1

FP Control

J

D

1

SPK

PW LED

J

P

1

5

Fan2

OH

3rd PS

PWR

Fault

Detect

CPU Fan2

Fan3

CH Intru

JL1

WD Enable

IPMI

IDE1

IDE2

Floppy

BIOS

J

1

8

JPA1

Ultra 320

SCSI CH A

Ultra 320

S

C

S

I C

H

B

Fan4

7902

CTRL

SATA0

SATA1

USB2/3

SMBUS

Buzzer

PCI-X 1 100 MHz ZCR

PCI-X 2 100 MHz

PCI-X #3 133 MHz

WOR

Battery

JPL1

GLAN CTLR

RAGE-X

82546

GLAN Enable

PCI-X #5 133MHz

X8 PCI-Epx #6

S

u

p

e

r

I/O

(North Bridge)

JPG1

VGA

C

O

M

1

U

S

B

0

/1

KB/

Mouse

Fan5

Fan6

ATX PWR

4-Pin PW

R

JP16

24-Pin

Force PWR ON

VGA Enable

Fan7

J24

JP12

R

e

b

o

t

O

p

t

io

n

JP14

JP13

Fan8

SCSI

CPU 1

CPU 2

A

la

rm

R

e

s

e

t

SCSI Enable

PXH

PCI-X #4 133MHz

COM2

WOL

USB4

PWR Fault

LE1

PW LED

JPA2 JPA3

DA1

D

A

2

ICH5R

PXH

Lindenhurst

Clear CMOS

C

H

B

S

C

S

I L

E

D

C

H

A

S

C

S

I L

E

D

(South Bridge)

E

7

5

20

8

2

8

01

E

R

S

C

S

I C

H

A

T

e

rm

S

C

S

I C

H

B

T

e

rm

USB 0/1

Chassis Intrusion

2-14

X6DH8-XG2/X6DHE-XG2 User's Manual

Front Panel Universal Serial Bus Headers

Extra USB header: FP USB2/FP USB3 (JUSB2), and FP USB4 (JUSB3) can be used for front side USB access. You will need a USB cable to use either connection. Refer to the tables on the right for pin definitions.

Front Panel Universal Serial Bus Pin

Definitions

Pin Number Definition 1+5V 2P0 3P0+ 4 Ground 5 N/A

Pin Number Definitio

n

1+5V 2P0 3P0+ 4 Ground 5Key

FPUSB2/FPUSB3

FPUSB4

Serial Ports

The COM1 (JCOM1) and COM2 (JCOM2) serial ports are located under the parallel port (see Figure 2-3). See the table on the right for pin definitions.

Serial Port Pi n Definitions

(COM1, COM2)

Pin Number Definition 1 DCD 2 RXD 3 TXD 4 DTR 5 GND

Pin Number Definition 6 DSR 7 RTS 8 CTS 9 RI 10 NC

GLAN1

®

S

UPER X6DH8-XG2

GLAN2

DIMM 2B (Bank 2)

DIMM 2A (Bank 2)

DIMM 3B (Bank 3)

DIMM 3A (Bank 3)

DIMM 4B (Bank 4)

DIMM 4A (Bank 4)

DIMM 1A (Bank 1)

DIMM 1B (Bank 1)

Fan1

8-pin PWR

PWR SMBus

CPU Fan1

JF1

F

P

C

o

n

tro

l

J

D

1

SPK

PW LED

J

P

1

5

Fan2

OH

3rd PS

PWR

Fault

Detect

CPU Fan2

Fan3

CH Intru

JL1

WD Enable

IPMI

IDE1

IDE2

Floppy

BIOS

J18

JPA1

Ultra 320

SCSI CH A

U

ltra

3

20

S

C

S

I C

H

B

F

a

n

4

7902

CTRL

SATA0

SATA1

USB2/3

SMBUS

Buzzer

P

C

I-X

1

0

M

H

z Z

C

R

P

C

I-X

2

1

0

M

H

z

P

C

I-X

#

3

1

3

M

H

z

W

O

R

Battery

JPL1

GLAN CTLR

RAGE-X

82546

GLAN Enable

P

C

I-X

#5

1

3

M

H

z

X

8

P

C

I-E

p

x

#

6

Super

I/O

(North Bridge)

JPG1

VGA

COM1

USB0/1

KB/

Mouse

Fan5

Fan6

ATX PWR

4-Pin PWR

JP16

24-Pin

Force PWR ON

VGA Enable

Fan7

J24

JP12

R

e

b

o

t

O

p

tio

n

JP14

JP13

F

a

n

8

SCSI

CPU 1

CPU 2

Alarm

Reset

SCSI Enable

PXH

P

C

I-X

#4

1

3

M

H

z

COM2

WOL

USB4

PWR Fault

L

E

1

P

W

L

E

D

JPA2 JPA3

DA1

D

A

2

ICH5R

PXH

L

in

d

e

n

h

u

rs

t

Clear CMOS

C

H

B

S

C

S

I L

E

D

C

H

A

S

C

S

I L

E

D

(South

Bridge)

E7520

82801ER

S

C

S

I C

H

A

T

e

r

m

S

C

S

I C

H

B

T

e

r

m

COM1

COM2 FP USB4 FP USB 2/3

(*Pin 10 is available on COM2 only.)

Chapter 2: Installation

2-15

ATX PS/2 Keyboard and PS/2 Mouse Ports

The ATX PS/2 keyboard and PS/2 mouse are located on J9. See the table at right for pin definitions. (See Figure 2-3 for the locations of each.)

PS/2 Keyboard

and Mouse Port

Pin Definitions

(JKM1)

Number

1 2 3 4 5 6

Definition

Data

NC

Ground

VCC

Clock

NC

GLAN (Giga-bit Ethernet Ports)

A G-bit Ethernet port (designated JLAN1/JLAN2) is located beside the COM2 port on the IO backplane. This port accepts RJ45 type cables.

GLAN1

®

S

UPER X6DH8-XG2

GLAN2

DIM

M

2B (Bank 2)

DIM

M

2A (Bank 2)

DIM

M

3B (Bank 3)

DIM

M

3A (Bank 3)

DIM

M

4B (Bank 4)

DIM

M

4A (Bank 4)

DIM

M

1A (Bank 1)

DIM

M

1B (Bank 1)

Fan1

8-pin PWR

PWR SMBus

C

P

U

F

a

n

1

JF1

F

P

C

o

n

tr

o

l

JD1

S

P

K

PW LED

J

P

1

5

Fan2

OH

3rd PS

PWR

Fault

Detect

C

P

U

F

a

n

2

Fan3

C

H

In

tru

J

L

1

W

D

E

n

a

b

le

IP

M

I

IDE1

ID

E

2

F

lo

p

y

B

IO

S

J18

J

P

A

1

Ultra 320

SCSI CH A

U

ltra

3

2

0

S

C

S

I C

H

B

Fan4

7

9

0

2

C

T

R

L

S

A

T

A

0

S

A

T

A

1

U

S

B

2

/3

S

M

B

U

S

B

u

zz

e

r

P

C

I-X

1

0

M

H

z

Z

C

R

P

C

I-X

2

1

0

M

H

z

P

C

I-X

#

3

1

3

M

H

z

W

O

R

B

atte

ry

J

P

L

1

G

L

A

N

C

T

L

R

A

G

E

-X

8

2

5

4

6

G

L

A

N

E

n

a

b

le

P

C

I-X

#

5

1

3

M

H

z

X

8

P

C

I-E

p

x

#

6

Super

I/O

(N

o

rth

B

rid

g

e

)

J

P

G

1

V

G

A

C

O

M

1

U

S

B

0

/1

K

B

/

M

o

u

s

e

F

a

n

5

F

an

6

A

T

X

P

W

R

4

-P

in

P

W

R

JP16

2

4

-P

in

Force PWR ON

V

G

A

E

n

ab

le

F

a

n

7

J24

J

P

1

2

R

ebo

o

t

O

p

tio

n

JP14

JP13

F

a

n

8

SCSI

C

P

U

1

C

P

U

2

A

la

rm

R

e

s

et

SCSI Enable

P

X

H

P

C

I-X

#

4

1

3

M

H

z

C

O

M

2

W

O

L

U

S

B

4

P

W

R

F

a

u

lt

L

E

1

PW

LED

J

P

A

2

J

P

A

3

DA1

D

A

2

IC

H

5R

P

X

H

L

in

d

e

n

h

u

rs

t

Clear CMOS

C

H

B

S

C

S

I L

E

D

C

H

A

S

C

S

I L

E

D

(S

o

u

th

B

rid

g

e

)

E7520

82801ER

S

C

S

I C

H

A

T

erm

S

C

S

I C

H

B

T

erm

Keyboard/ Mouse

GLAN1

GLAN2

2-16

X6DH8-XG2/X6DHE-XG2 User's Manual

GLAN1

®

S

UPER X6DH8-XG2

GLAN2

D

IM

M

2

B

(B

a

n

k

2

)

D

IM

M

2

A

(B

a

n

k

2

)

D

IM

M

3

B

(B

a

n

k

3

)

D

IM

M

3

A

(B

a

n

k

3

)

D

IM

M

4

B

(B

a

n

k

4

)

D

IM

M

4

A

(B

a

n

k

4

)

D

IM

M

1

A

(B

a

n

k

1

)

D

IM

M

1

B

(B

a

n

k

1

)

Fan1

8-pin PWR

PWR SMBus

CPU Fan1

JF1

FP Control

J

D

1

S

P

K

PW LED

JP15

Fan2

OH

3rd PS

PWR

Fault

Detect

CPU Fan2

Fan3

CH Intru

JL1

WD Enable

IPMI

IDE1

IDE2

F

lo

p

y

BIOS

J18

JPA1

Ultra 320

SCSI CH A

U

ltra

3

2

0

S

C

S

I C

H

B

Fan4

7902

CTRL

SATA0

SATA1

USB2/3

SMBUS

Buzzer

P

C

I-X

1 1

00

M

H

z Z

C

R

P

C

I-X

2

10

0 M

H

z

P

C

I-X

#

3 13

3

M

H

z

W

OR

Battery

JPL1

GLAN CTLR

RAGE-X

82546

GLAN

Enable

P

C

I-X

#5 133

M

H

z

X

8

P

C

I-E

p

x #

6

S

u

p

e

r

I/O

(North

Bridge)

JPG1

VGA

COM1

USB0/1

KB/ Mouse

Fan5

Fan6

ATX PWR

4-Pin PWR

JP16

24-Pin

Force PWR ON

VGA Enable

Fan7

J24

J

P

1

2

Reboot

Option

JP14

J

P

1

3

Fan8

SCSI

CPU 1

CPU 2

A

la

rm

R

e

s

e

t

SCSI Enable

PXH

P

C

I-X

#4 133M

H

z

COM2

WOL

USB4

PWR Fault

L

E

1

P

W

L

E

D

JPA2 JPA3

DA1

DA2

ICH5R

PXH

L

in

d

en

h

u

rst

Clear CMOS

CHB SCSI LED

CHA SCSI LED

(South Bridge)

E

7

5

2

0

8

2

8

0

1

E

R

SCSI CH A Term

SCSI CH B Term

Power LED/Speaker

On the JDI header, pins 1-3 are for a power LED and pins 4-7 are for the speaker. See the table on the right for speaker pin definitions. Note: The speaker connector pins are for use with an external speaker. If you wish to use the onboard speaker, you should close pins 6-7 with a jumper.

Speaker Connector Pin

Definitions (J D 1)

Number

4 5 6 7

Function

+

Key

Defi n iti o n

Red wire, Speaker data

No connection

Key

Speaker data

Fan Header Pin Definitions

Number

1 2 3

Defin i tion

Ground (black)

+12V (red)

Tachometer

Caution: Fan headers are DC pow e r.

Fan Headers

The X6DH8-XG2/X6DHE-XG2 has eight fan headers. (*Note: These fan headers can support both 3pin fans and 4-pin fans. Pins #1#3 of 4-pin fan headers are backward compatible with the traditional 3-pin fans.) The fan speeds are controlled by Thermal Management via BIOS under the Hardware Monitoring section in the Advanced Setting. See the table on the right for pin definitions.

4-pin Fan Hea der Pin Definitions

(CPU and Chassis Fans )

Pin#

1 2 3

Definition

Ground (black)

+12V (red)

Tachometer

Caution: These fan headers use DC power.

4 PWR_Control

Fan5 Fan6

Fan7

Fan2

Speaker/ PWR LED

Fan1

Fan3

Fan8

Fan4

Chapter 2: Installation

2-17

Wake-On-Ring

The Wake-On-Ring header is designated JWOR1. This function allows your computer to receive and "wake-up" by an incoming call to the modem when in suspend state. See the table on the right for pin definitions. You must have a Wake-On-Ring card and cable to use this feature.

Wake-on-Ring

Pin Definitions

(JWOR1)

Number

1 2

Definition

Ground

Wake-up

Wake-On-LAN

The Wake-On-LAN header is located at JWOL on the motherboard. See the table on the right for pin definitions. You must enable the LAN Wake-Up setting in BIOS to use this function. (You must also have a LAN card with a Wake-On-LAN connector and cable to use this feature.)

Number

1 2 3

Definition

+5V Standby

Ground

Wake-up

Wake-On-LAN Pin

Definitions (JWOL)

GLAN1

®

S

UPER X6DH8-XG2

GLAN2

DIMM 2B (Bank 2)

DIMM 2A (Bank 2)

DIMM 3B (Bank 3)

DIMM 3A (Bank 3)

DIMM 4B (Bank 4)

DIMM 4A (Bank 4)

DIMM 1A (Bank 1)

DIMM 1B (Bank 1)

Fan1

8-pin PWR

PWR SMBus

C

P

U

F

a

n

1

JF1

F

P

C

o

n

tr

o

l

JD

1

S

P

K

PW LED

JP15

Fan2

OH

3rd PS

PWR

Fault

Detect

C

P

U

F

a

n

2

Fan3

C

H

In

t

r

u

J

L

1

W

D

E

n

a

b

le

IP

M

I

IDE1

ID

E

2

F

lo

p

y

B

IO

S

J18

J

P

A

1

Ultra 320

SCSI CH A

Ultra 320

SCSI CH B

Fan4

7

9

0

2

C

T

R

L

S

A

T

A

0

S

A

T

A

1

U

S

B

2

/3

S

M

B

U

S

B

u

z

e

r

PCI-X 1 100 MHz ZCR

PCI-X 2 100 MHz

PCI-X #3 133 MHz

WOR

B

a

tt

e

r

y

J

P

L

1

G

L

A

N

C

T

L

R

A

G

E

-X

8

2

5

4

6

G

L

A

N

E

n

a

b

le

PCI-X #5 133MHz

X8 PCI-Epx #6

S

u

p

e

r

I/O

(N

o

r

t

h

B

r

id

g

e

)

J

P

G

1

V

G

A

C

O

M

1

U

S

B

0

/1

K

B

/

M

o

u

s

e

F

a

n

5

F

a

n

6

A

T

X

P

W

R

4

-

P

in

P

W

R

JP16

2

4

-

P

in

Force PWR ON

V

G

A

E

n

a

b

le

F

a

n

7

J24

JP12

R

e

b

o

t

O

p

tio

n

JP14

J

P

1

3

F

a

n

8

SCSI

C

P

U

1

C

P

U

2

A

la

r

m

R

e

s

e

t

SCSI Enable

P

X

H

PCI-X #4 133MHz

C

O

M

2

W

O

L

U

S

B

4

P

W

R

F

a

u

lt

LE1

P

W

L

E

D

J

P

A

2

J

P

A

3

DA1

D

A

2

IC

H

5

R

P

X

H

Lindenhurst

Clear CMOS

C

H

B

S

C

S

I L

E

D

C

H

A

S

C

S

I L

E

D

(S

o

u

th

B

r

id

g

e

)

E

7

5

2

0

8

2

8

0

1

E

R

S

C

S

I C

H

A

T

e

r

m

S

C

S

I C

H

B

T

e

r

m

WOR

WOL

2-18

X6DH8-XG2/X6DHE-XG2 User's Manual

SMB

A System Management Bus header is located at J22. Connect the appropriate cable here to utilize SMB on your system.

Fan Header Pin Definitions

Number

1 2 3 4

Definition

Date

Ground

Clock

NA

Caution: These fan headers are DC power.

SMB Power (I

2

C)

Connector

I2 C Connector (J24), located between Fan7 (CPU1 Fan), and the PWR Fault header, monitors the status of PWR Supply, Fan and system temperature.

SMB PWR

Pin Definitions (J24)

Pin #

1 2 3 4 5

Definition

Clock

Data

N/A

GND

+3.3V

GLAN1

®

S

UPER X6DH8-XG2

GLAN2

DIMM 2B (Bank 2)

DIMM 2A (Bank 2)

DIMM 3B (Bank 3)

DIMM 3A (Bank 3)

DIMM 4B (Bank 4)

DIMM 4A (Bank 4)

DIMM 1A (Bank 1)

DIMM 1B (Bank 1)

Fan1

8-pin PWR

PWR SMBus

C

P

U

Fan1

JF1

F

P

C

o

n

tr

o

l

J

D

1

S

P

K

PW LED

J

P

1

5

Fan2

OH

3rd PS

PWR

Fault

Detect

C

P

U

F

an2

Fan3

C

H

Intru

JL1

W

D

E

n

able

IP

M

I

IDE1

IDE2

F

lo

p

y

B

IO

S

J

1

8

JP

A

1

Ultra 320

S

C

S

I C

H

A

Ultra 320

SCSI CH B

F

a

n

4

7902

C

TR

L

S

A

T

A

0

S

A

T

A

1

U

S

B

2/3

S

M

B

U

S

B

uzzer

PCI-X 1 100 MHz ZCR

PCI-X 2 100 MHz

PCI-X #3 133 MHz

WOR

B

attery

JP

L

1

G

LA

N

C

TLR

R

A

G

E

-X

82546

G

LA

N

E

nab

le

PCI-X #5 133MHz

X8 PCI-Epx #6

Super

I/O

(N

o

rth

B

ridge)

JP

G

1

V

G

A

C

O

M

1

U

SB

0/1

K

B

/

M

ouse

F

an5

F

an6

A

TX

PW

R

4-P

in

P

W

R

JP16

24-P

in

Force PWR ON

V

G

A

E

n

ab

le

Fan7

J24

JP12

R

e

b

o

t

O

p

tio

n

JP14

J

P

1

3

F

a

n

8

SCSI

C

P

U

1

C

P

U

2

A

la

r

m

R

e

s

e

t

SCSI Enable

P

X

H

PCI-X #4 133MHz

C

O

M

2

W

O

L

U

S

B

4

PWR Fault

LE1

P

W

L

E

D

JP

A

2

JP

A

3

DA1

D

A

2

IC

H

5R

P

X

H

Lindenhurst

Clear CMOS

C

H

B

S

C

S

I L

E

D

C

H

A

S

C

S

I L

E

D

(South B

ridg

e)

E7520

82801ER

S

C

S

I C

H

A

T

e

rm

S

C

S

I C

H

B

T

e

rm

SMB PWR

SMB

Chapter 2: Installation

2-19

Power Fault

Connect a cable from your power supply to the Power Fault header (JP12) to provide warning of power supply failure. This warning signal is passed through the PWR_LED pin to indicate of a power failure on the chassis. See the table on the right for pin definitions.

Power Fault

Pin Definitions (JP12)

Number

1 2 3 4

Definition PWR 1 Fail Signal PWR 2 Fail Signal PWR 3 Fail Signal

Signal: Alarm Reset

Note: This feature is only available when using redundant Supermicro power supplies.

Power Fail Alarm Clear Switch (Alarm Reset)

The system will notify you in the event of a power supply failure. This feature assumes that Supermicro redundant power supply units are installed in the chassis. If you only have a single power supply installed, you should leave the pins open (the default setting) to prevent false alarms. See the table on the right for jumper settings.

Jumper

Position

Open

Short

Definition

Normal(*default

)

Clear Alarm

Alarm Clear Switch

(JP14)

GLAN1

®

S

UPER X6DH8-XG2

GLAN2

D

IM

M

2

B

(B

a

n

k

2

)

D

IM

M

2

A

(B

a

n

k

2

)

D

IM

M

3

B

(B

a

n

k

3

)

D

IM

M

3

A

(B

a

n

k

3

)

D

IM

M

4

B

(B

a

n

k

4

)

D

IM

M

4

A

(B

a

n

k

4

)

D

IM

M

1

A

(B

a

n

k

1

)

D

IM

M

1

B

(B

a

n

k

1

)

Fan1

8-pin PWR

PWR SMBus

C

P

U

F

a

n

1

JF1

F

P

C

o

n

tr

o

l

JD1

SPK

PW LED

J

P

1

5

Fan2

OH

3rd PS

PWR

Fault

Detect

C

P

U

F

a

n

2

Fan3

C

H

In

tru

J

L

1

W

D

E

n

a

b

le

IP

M

I

IDE1

ID

E

2

Floppy

B

IO

S

J

1

8

J

P

A

1

Ultra 320

SCSI CH A

Ultra 320

SCSI CH B

Fan4

7

9

0

2

C

T

R

L

S

A

T

A

0

S

A

T

A

1

U

S

B

2

/3

S

M

B

U

S

B

u

z

e

r

PCI-X 1 100 MHz ZCR

PCI-X 2 100 MHz

PCI-X #3 133 MHz

WOR

B

a

tte

ry

J

P

L

1

G

L

A

N

C

T

L

R

A

G

E

-X

8

2

5

4

6

G

L

A

N

E

n

a

b

le

PCI-X #5 133MHz

X8 PCI-Epx #6

S

u

p

er

I/O

(N

o

rth

B

rid

g

e

)

J

P

G

1

V

G

A

C

O

M

1

U

S

B

0

/1

K

B

/

M

o

u

s

e

F

a

n

5

F

a

n

6

A

T

X

P

W

R

4

-P

in

P

W

R

JP16

2

4

-P

in

Force PWR ON

V

G

A

E

n

a

b

le

F

a

n

7

J24

J

P

1

2

Reboot

Option

JP14

J

P

1

3

F

a

n

8

SCSI

C

P

U

1

C

P

U

2

A

la

rm

R

e

se

t

SCSI Enable

P

X

H

PCI-X #4 133MHz

C

O

M

2

W

O

L

U

S

B

4

P

W

R

F

a

u

lt

LE1

P

W

L

E

D

J

P

A

2

J

P

A

3

DA1

DA2

IC

H

5

R

P

X

H

Lindenhurst

Clear CMOS

CHB SCSI LED

CHA SCSI LED

(S

o

u

th

B

rid

g

e

)

E

75

2

0

82

80

1

E

R

SCSI CH A Term SCSI CH B Term

PWR Fault

Alarm Reset

2-20

X6DH8-XG2/X6DHE-XG2 User's Manual

3rd PWR Supply PWR Fault Detect (JP13)

The system can notify you in the event of a power supply failure. This feature assumes that three power supply units are installed in the chassis, with one acting as a backup. If you only have one or two power supply units installed, you should disable this (the default setting) with JP13 to prevent false

alarms.

Jumper

Position

Open

Closed

Definition

Disabled

Enabled

3rd PWR Supply PWR

Fault Detect

Jumper Settings (JP13)

Overheat LED (JOH1)

The JOH1 header is used to connect an LED to provide warning of chassis overheating. It is located near the microphone connector.

Number

1 2

Definition

5vDC

OH Active

Overheat LED

Pin Definitions (JOH1)

GLAN1

®

S

UPER X6DH8-XG2

GLAN2

DIMM 2B (Bank 2)

DIMM 2A (Bank 2)

DIMM 3B (Bank 3)

DIMM 3A (Bank 3)

DIMM 4B (Bank 4)

DIMM 4A (Bank 4)

DIMM 1A (Bank 1)

DIMM 1B (Bank 1)

Fan1

8-pin PWR

PWR SMBus

C

P

U

F

a

n

1

JF1

F

P

C

o

n

t

r

o

l

J

D

1

S

P

K

PW LED

JP15

Fan2

OH

3rd PS

PWR

Fault

Detect

C

P

U

F

a

n

2

Fan3

C

H

In

tru

J

L

1

W

D

E

n

a

b

le

IP

M

I

IDE1

IDE2

F

lo

p

y

B

IO

S

J18

J

P

A

1

Ultra 320

SCSI CH A

Ultra 320

SCSI CH B

F

an

4

7

9

0

2

C

T

R

L

S

A

T

A

0

S

A

T

A

1

U

S

B

2

/3

S

M

B

U

S

B

u

z

e

r

PCI-X 1 100 MHz ZCR

PCI-X 2 100 MHz

PCI-X #3 133 MHz

WOR

B

a

tte

ry

J

P

L

1

G

L

A

N

C

T

L

R

A

G

E

-X

8

2

5

4

6

G

L

A

N

E

n

a

b

le

PCI-X #5 133MHz

X8 PCI-Epx #6

S

u

p

e

r

I/O

(N

o

r

th

B

rid

g

e

)

J

P

G

1

V

G

A

C

O

M

1

U

S

B

0

/1

K

B

/

M

o

u

s

e

F

a

n

5

F

a

n

6

A

T

X

P

W

R

4

-P

in

P

W

R

JP16

2

4

-P

in

Force PWR ON

V

G

A

E

n

a

b

le

F

a

n

7

J24

JP12

R

e

b

o

t

O

p

tio

n

JP14

J

P

1

3

F

a

n

8

SCSI

C

P

U

1

C

P

U

2

A

la

r

m

R

e

s

e

t

SCSI Enable

P

X

H

PCI-X #4 133MHz

C

O

M

2

W

O

L

U

S

B

4

P

W

R

Fa

ult

LE1

P

W

L

E

D

J

P

A

2

J

P

A

3

DA1

D

A

2

IC

H

5

R

P

X

H

Lindenhurst

Clear CMOS

C

H

B

S

C

S

I L

E

D

C

H

A

S

C

S

I L

E

D

(S

o

u

th

B

rid

g

e

)

E

7

5

20

82

8

0

1E

R

S

C

S

I C

H

A

T

e

r

m

S

C

S

I C

H

B

T

e

r

m

OH LED

3rd PS PWR Fault

Chapter 2: Installation

2-21

2-6 Jumper Settings

Explanation of Jumpers

To modify the operation of the motherboard, jumpers can be used to choose between optional settings. Jumpers create shorts between two pins to change the function of the connector. Pin 1 is identified with a square solder pad on the printed circuit board. See the motherboard layout pages for jumper locations. Note: On two pin jumpers, "Closed" means the jumper is on and "Open" means the jumper is off the pins.

Connector

Pins

Jumper

Cap

Setting

Pin 1-2 short

3 2 1

GLAN Enable/Disable

JPL1 enables or disables the GLAN port(s) on the motherboard. See the table on the right for jumper settings. The default setting is enabled.

Jumper Position Pins 1-2 Pins 2-3

Definition

Enabled

Disabled

GLAN

Enable/Disable

Jumper Settings

(JPL1)

GLAN1

®

S

U

P

E

R

X

6D

H

8-X

G

2

GLAN2

D

IM

M

2B

(B

a

n

k

2)

D

IM

M

2A

(B

an

k 2)

D

IM

M

3B

(B

an

k 3)

D

IM

M

3A

(B

an

k 3)

D

IM

M

4B

(B

an

k 4)

D

IM

M

4A

(B

an

k 4)

D

IM

M

1A

(B

an

k 1

)

D

IM

M

1B

(B

an

k 1)

Fan1

8-pin PWR

PWR SMBus

CPU Fan1

JF1

F

P

C

o

n

tro

l

JD1

S

P

K

PW LED

J

P

1

5

Fan2

OH

3rd PS

PWR

Fault

Detect

CPU Fan2

Fan3

CH Intru

JL1

WD Enable

IPMI

IDE1

ID

E

2

F

lo

p

y

BIOS

J18

JPA1

Ultra 320

SCSI CH A

U

ltra

3

2

0

S

C

S

I

C

H

B

Fan4

7902

CTRL

SATA0

SATA1

USB2/3

SMBUS

Buzzer

P

C

I-X

1

0

M

H

z

Z

C

R

P

C

I-X

2

1

0

M

H

z

P

C

I-X

#

3

1

3

M

H

z

WOR

Battery

JPL1

GLAN CTLR

RAGE-X

82546

GLAN Enable

P

C

I-X

#

5

1

3

M

H

z

X

8

P

C

I-E

p

x

#

6

Super

I/O

(North Bridge)

JPG1

VGA

COM1

USB0/1

KB/ Mouse

Fan5

Fan6

ATX PWR

4-Pin PWR

JP16

24-Pin

Force PWR ON

VGA Enable

Fan7

J24

J

P

1

2

Reboot

O

ption

JP14

JP13

Fan8

SCSI

CPU 1

CPU 2

Alarm

Reset

SCSI Enable

PXH

P

C

I-X

#

4

1

3

M

H

z

COM2

WOL

USB4

P

W

R

F

a

u

lt

LE1

PW LED

JPA2 JPA3

DA1

D

A

2

ICH5R

PXH

L

in

d

e

n

h

u

rs

t

Clear CMOS

C

H

B

S

C

S

I L

E

D

C

H

A

S

C

S

I L

E

D

(South

Bridge)

E7520

82801ER

S

C

S

I C

H

A

T

e

r

m

S

C

S

I C

H

B

T

e

r

m

GLAN Enable

2-22

X6DH8-XG2/X6DHE-XG2 User's Manual

Watch Dog

J18 controls Watch Dog, a system monitor that takes action when a software application freezes the system. Pins 1-2 will have WD reset the system if a program freezes. Pins 2-3 will generate a non-maskable interrupt for the program that has frozen (requires software implementation). Watch Dog must also be enabled in BIOS.

Jumper Position Pins 1-2 Pins 2-3

Open

Definition

WD to Reset

WD to NMI

Disabled

Watch Dog

Jumper Settings (J18)

CMOS Clear

JBT1 is used to clear CMOS. Instead of pins, this "jumper" consists of contact pads to prevent the accidental clearing of CMOS. To clear CMOS, use a metal object such as a small screwdriver to touch both pads at the same time to short the connection. Always remove the AC power cord from the system before clearing CMOS. Note: For an ATX power supply, you must completely shut down the system, remove the AC power cord and then short JBT1 to clear CMOS.

Do not use the PW_ON connector to clear CMOS.

GLAN1

®

S

U

P

E

R

X

6D

H

8-X

G

2

GLAN2

DIMM 2B (Bank 2)

DIMM 2A (Bank 2)

DIMM 3B (Bank 3)

DIMM 3A (Bank 3)

DIMM 4B (Bank 4)

DIMM 4A (Bank 4)

DIMM 1A (Bank 1)

DIMM 1B (Bank 1)

Fan1

8-pin PWR

PWR SMBus

CPU Fan1

JF1

F

P

C

o

n

tro

l

J

D

1

SPK

PW LED

JP15

Fan2

OH

3rd PS

PWR

Fault

Detect

CPU Fan2

Fan3

CH Intru

JL1

WD Enable

IPMI

IDE1

IDE2

F

l

o

p

y

BIOS

J

1

8

JPA1

Ultra 320

S

C

S

I C

H

A

U

l

t

r

a

3

2

0

S

C

S

I

C

H

B

F

a

n

4

7902

CTRL

SATA0

SATA1

USB2/3

SMBUS

Buzzer

P

C

I

-

X

1

0

M

H

z

Z

C

R

P

C

I

-

X

2

1

0

M

H

z

P

C

I

-

X

#

3

1

3

M

H

z

W

O

R

Battery

JPL1

GLAN CTLR

RAGE-X

82546

GLAN Enable

P

C

I

-

X

#

5

1

3

M

H

z

X

8

P

C

I

-

E

p

x

#

6

S

u

p

e

r

I/O

(North Bridge)

JPG1

VGA

COM1

USB0/1

KB/ Mouse

Fan5

Fan6

ATX PWR

4-Pin PWR

JP16

24-Pin

Force PWR ON

VGA Enable

Fan7

J24

J

P

1

2

R

e

b

o

t

O

p

t

i

o

n

JP14

J

P

1

3

Fan8

SCSI

CPU 1

CPU 2

A

l

a

r

m

R

e

s

e

t

SCSI Enable

PXH

P

C

I

-

X

#

4

1

3

M

H

z

COM2

WOL

USB4

PWR Fault

L

E

1

PW LED

JPA2 JPA3

DA1

DA

2

ICH5R

PXH

L

i

n

d

e

n

h

u

r

s

t

Clear CMOS

CHB SCSI LED

CHA SCSI LED

(South Bridge)

E

7

5

2

0

8

2

8

0

1

E

R

SCSI CH A Term

SCSI CH B Term

WD

Clear CMOS

Chapter 2: Installation

2-23

VGA Enable/Disable

JPG1 enables or disables the VGA Connector on the motherboard. See the table on the right for jumper settings. The default setting is enabled.

Jumper Position Pins 1-2 Pins 2-3

Definition

Enabled

Disabled

VGA

Enable/Disable

Jumper Settings

(JPG1)

GLAN1

®

S

UPER X6DH8-XG2

GLAN2

D

IM

M

2

B

(B

a

n

k

2

)

D

IM

M

2

A

(B

a

n

k

2

)

D

IM

M

3

B

(B

a

n

k

3

)

D

IM

M

3

A

(B

a

n

k

3

)

D

IM

M

4

B

(B

a

n

k

4

)

D

IM

M

4

A

(B

a

n

k

4

)

D

IM

M

1

A

(B

a

n

k

1

)

D

IM

M

1

B

(B

a

n

k

1

)

Fan1

8-pin PWR

PWR SMBus

CPU Fan1

JF1

F

P

C

o

n

t

r

o

l

JD1

S

P

K

PW LED

JP15

Fan2

OH

3rd PS

PWR

Fault

Detect

CPU Fan2

Fan3

CH Intru

JL1

WD Enable

IPMI

IDE1

I

D

E

2

Floppy

BIOS

J

1

8

JPA1

Ultra 320

S

C

SI C

H

A

Ultra 320

S

C

S

I C

H

B

F

a

n

4

7902

CTRL

SATA0

SATA1

USB2/3

SMBUS

Buzzer

PCI-X 1 100 MHz ZCR

PCI-X 2 100 MHz

PCI-X #3 133 MHz

WOR

Battery

JPL1

GLAN CTLR

RAGE-X

82546

GLAN Enable

PCI-X #5 133MHz

X8 PCI-Epx #6

S

u

p

e

r

I/O

(North Bridge)

JPG1

VGA

COM1

USB0/1

KB/ Mouse

Fan5

Fan6

ATX PWR

4-Pin PWR

JP16

24-Pin

Force PWR ON

VGA Enable

Fan7

J24

JP12

R

e

b

o

t

O

p

tio

n

JP14

J

P

1

3

F

a

n

8

SCSI

CPU 1

CPU 2

A

la

rm

R

e

s

e

t

SCSI Enable

PXH

PCI-X #4 133MHz

COM2

WOL

USB4

P

W

R

F

a

u

l

t

LE

1

P

W

L

E

D

JPA2 JPA3

DA1

DA2

ICH5R

PXH

Lindenhurst

Clear CMOS

CHB SCSI LED

CHA SCSI LED

(South Bridge)

E

7

5

2

0

8

2

8

0

1

E

R

SCSI CH A Term SCSI CH B Term

VGA Enable

2-24

X6DH8-XG2/X6DHE-XG2 User's Manual

SCSI Enable/Disable (*ForX6DH8-XG2 only)

Jumper JPA1 allows you to enable or disable the SCSI headers. Jumper JPA1 is for headers #1 and #2. The default setting is pins 1-2 to enable all four headers. See the table on the right for jumper settings.

Jumper

Position Pins 1-2 Pins 2-3

Definition

Enabled

Disabled

SCSI Enable/Disable

Jumper Settings

(JPA1)

SCSI Termination Enable/ Disable (*ForX6DH8-XG2

only)

Jumpers JPA2 and JPA3 allow you to enable or disable termination for the SCSI connectors. Jumper JPA2 controls SCSI channel A and JPA3 is for SCSI channel B. The default setting is open to enable (terminate) both SCSI channels. (*Note: For the SCSI Drives to function properly, please do not change the default setting.) See the table on the right for jumper settings.

Jumper

Position

*Open

Closed

Definition

Enabled

Disabled

SCSI Channel Terminatio

n

Enable (JPA2, JPA3)

(*Default)

GLAN1

®

S

UPER X6DH8-XG2

GLAN2

D

IM

M

2B

(B

a

n

k 2

)

D

IM

M

2

A

(B

a

n

k

2)

D

IM

M

3B

(B

a

n

k

3

)

D

IM

M

3

A

(B

a

n

k

3)

D

IM

M

4B

(B

a

n

k 4

)

D

IM

M

4

A

(B

a

n

k

4

)

D

IM

M

1

A

(B

a

n

k

1

)

D

IM

M

1

B

(B

a

n

k 1

)

Fan1

8-pin PWR

PWR SMBus

C

P

U

F

a

n

1

JF1

FP Control

JD1

S

P

K

PW LED

J

P

1

5

Fan2

OH

3rd PS

PWR

Fault

Detect

C

P

U

F

a

n

2

Fan3

C

H

In

tr

u

J

L

1

W

D

E

n

a

b

le

IP

M

I

IDE1

ID

E

2

Floppy

B

IO

S

J

1

8

J

P

A

1

Ultra 320

S

C

S

I C

H

A

U

lt

r

a

3

2

0

SCSI CH B

Fan4

7

9

0

2

C

T

R

L

S

A

T

A

0

S

A

T

A

1

U

S

B

2

/3

S

M

B

U

S

B

u

z

e

r

P

C

I-

X

1

0

M

H

z

Z

C

R

P

C

I-

X

2

1

0

M

H

z

P

C

I-

X

#

3

1

3

M

H

z

W

O

R

B

a

tte

ry

J

P

L

1

G

L

A

N

C

T

L

R

A

G

E

-X

8

2

5

4

6

G

L

A

N

E

n

a

b

le

P

C

I-

X

#

5

1

3

M

H

z

X

8

P

C

I-

E

p

x

#

6

Super

I/O

(N

o

rth

B

rid

g

e

)

J

P

G

1

V

G

A

C

O

M

1

U

S

B

0

/1

K

B

/

M

o

u

s

e

F

a

n

5

F

a

n

6

A

T

X

P

W

R

4

-P

in

P

W

R

JP16

2

4

-P

in

Force PWR ON

V

G

A

E

n

a

b

le

F

a

n

7

J24

J

P

1

2

Reboot

Option

JP14

J

P

1

3

Fan8

SCSI

C

P

U

1

C

P

U

2

A

l

a

r

m

R

e

s

e

t

SCSI Enable

P

X

H

P

C

I-

X

#

4

1

3

M

H

z

C

O

M

2

W

O

L

U

S

B

4

P

W

R

F

a

u

lt

L

E

1

P

W

L

E

D

J

P

A

2

J

P

A

3

DA1

D

A

2

IC

H

5

R

P

X

H

L

in

d

e

n

h

u

r

s

t

Clear CMOS

C

H

B

S

C

S

I

L

E

D

C

H

A

S

C

S

I

L

E

D

(S

o

u

th

B

rid

g

e

)

E7520

82801ER

S

C

S

I

C

H

A

T

e

r

m

S

C

S

I

C

H

B

T

e

r

m

SCSI Enable

SCSI Ch A/B Term. Enable

Chapter 2: Installation

2-25

2-7 Onboard Indicators

SCSI Channel Activity LEDs (*ForX6DH8-XG2 only)

Two LEDs (DA1, DA2) to indicate SCSI activity are located near the SCSI controller (AIC-7902) chip. DA1 indicates the activity status of SCSI Channel A, and DA2 DA1 indicates the activity status of SCSI Channel B. See the table at right for the functions associated with each LED.

LED DA1 DA2

Defin itio n

Channel A Activ

e

Channel B Activ

e

SCSI Channel Activity

LEDs (DA1, DA2)

GLAN LEDs

The Gigabit Ethernet LAN ports (located beside the Video port) has two LEDs. The yellow LED indicates activity while the other LED may be green, orange or off to indicate the speed of the connection. See the table at right for the functions associated with the second LED.

LED

Color

Off Green Amber

Definition

No Connection

10/100 MHz

1 GHz

1 Gb LAN (Link LED)

GLAN1

®

S

UPER X6DH8-XG2

GLAN2

DIMM 2B (Bank 2)

DIMM 2A (Bank 2)

DIMM 3B (Bank 3)

DIMM 3A (Bank 3)

DIMM 4B (Bank 4)

DIMM 4A (Bank 4)

DIMM 1A (Bank 1)

DIMM 1B (Bank 1)

Fan1

8-pin PWR

PWR SMBus

CPU Fan1

JF1

F

P

C

o

n

tro

l

J

D

1

S

P

K

PW LED

J

P

1

5

Fan2

OH

3rd PS

PWR

Fault

Detect

CPU Fan2

Fan3

C

H Intru

JL1

W

D Enable

IPM

I

IDE1

IDE2

F

lo

p

y

B

IO

S

J

1

8

JPA1

Ultra 320

S

C

S

I C

H

A

Ultra 320

SCSI CH B

F

a

n

4

7902

CTR

L

SATA

0

SATA

1

US

B2/3

SM

BUS

Buzzer

PCI-X 1 100 MHz ZCR

PCI-X 2 100 MHz

PCI-X #3 133 MHz

WOR

Battery

JPL1

G

LA

N

C

TLR

RAG

E-X

82546

G

LAN

Enable

PCI-X #5 133MHz

X8 PCI-Epx #6

Super

I/O

(North B

ridge)

JPG

1

VG

A

COM

1

USB0/1

KB/ M

ouse

Fan5

Fan6

ATX PW

R

4-Pin PW

R

JP16

24-Pin

Force PWR ON

VG

A

Enable

Fan7

J24

JP12

R

e

b

o

t

O

p

tio

n

JP14

J

P

1

3

F

a

n

8

SCSI

C

PU 1

CPU 2

A

la

rm

R

e

s

e

t

SCSI Enable

PXH

PCI-X #4 133MHz

C

O

M

2

W

O

L

USB4

PWR Fault

LE1

P

W

L

E

D

JPA2 JPA

3

DA1

D

A

2

ICH5R

PXH

Lindenhurst

Clear CMOS

C

H

B

S

C

S

I L

E

D

C

H

A

S

C

S

I L

E

D

(South B

ridge)

E7520

82801ER

S

C

S

I C

H

A

T

e

rm

S

C

S

I C

H

B

T

erm

SCSI Ch. A Activity LED

GLAN LEDs

Link LED

Activity LED

LED

Color

Amber

Definition

Blinking

10/100MHz/

1GHz

1 Gb LAN (Activity LED)

SCSI Ch. B Activity LED

2-26

X6DH8-XG2/X6DHE-XG2 User's Manual

2-8 Floppy/Hard Disk Drive and SCSI Connections

Note the following when connecting the floppy and hard disk drive cables:

• The floppy disk drive cable has seven twisted wires.

• A red mark on a wire typically designates the location of pin 1.

• A single floppy disk drive ribbon cable has 34 wires and two connectors to provide for two floppy disk drives. The connector with twisted wires always connects to drive A, and the connector that does not have twisted wires always connects to drive B.

Floppy Connector

The floppy connector is located on JFDD1. See the table below for pin definitions.

Pin Number Function 1 GND 3 GND 5 Key 7 GND 9 GND 11 GND 13 GND 15 GND 17 GND 19 GND 21 GND 23 GND 25 GND 27 GND 29 GND 31 GND 33 GND

Pin Number Function 2 FDHDIN 4 Reserved 6 FDEDIN 8 Index 10 Motor Enable 12 Drive Select B 14 Drive Select A 16 Motor Enable 18 DIR 20 STEP 22 Write Data 24 Write Gate 26 Track 00 28 Write Protect 30 Read Data 32 Side 1 Select 34 Diskette

Floppy Connector Pin Definitions

GLAN1

®

S

U

P

E

R

X

6D

H

8-X

G

2

GLAN2

D

IM

M

2

B

(B

a

n

k

2

)

D

IM

M

2

A

(B

a

n

k

2

)

D

IM

M

3

B

(B

a

n

k

3

)

D

IM

M

3

A

(B

a

n

k

3

)

D

IM

M

4

B

(B

a

n

k

4

)

D

IM

M

4

A

(B

a

n

k

4

)

D

IM

M

1

A

(B

a

n

k

1

)

D

IM

M

1

B

(B

a

n

k

1

)

Fan1

8-pin PWR

PWR SMBus

CPU Fan1

JF1

F

P

C

o

n

tr

o

l

JD

1

S

P

K

PW LED

JP15

Fan2

OH

3rd PS

PWR

Fault

Detect

CPU Fan2

Fan3

CH Intru

JL1

W

D Enable

IPM

I

IDE1

ID

E

2

F

lo

p

y

BIO

S

J

1

8

JPA1

Ultra 320

S

C

S

I C

H

A

U

l

t

r

a

3

2

0

S

C

S

I

C

H

B

F

a

n

4

7902

C

TR

L

SATA0

SATA1

U

SB

2/3

SM

BU

S

Buzzer

P

C

I

-

X

1

0

M

H

z

Z

C

R

P

C

I

-

X

2

1

0

M

H

z

P

C

I

-

X

#

3

1

3

M

H

z

WOR

Battery

JPL1

G

LAN

CTLR

RA

GE-X

82546

G

LAN

Enable

P

C

I-

X

#

5

1

3

M

H

z

X

8

P

C

I

-

E

p

x

#

6

Super

I/O

(North Bridge)

JPG

1

VG

A

C

O

M

1

U

S

B

0/1

KB/ M

ouse

Fan5

Fan6

ATX PW

R

4-Pin PW

R

JP16

24-Pin

Force PWR ON

VG

A

Enable

Fan7

J24

J

P

1

2

Reboot

Option

JP14

JP

13

F

a

n

8

SCSI

C

PU 1

CPU 2

A

la

rm

R

eset

SCSI Enable

PXH

P

C

I

-

X

#

4

1

3

M

H

z

CO

M

2

W

O

L

U

SB

4

PW

R

Fault

LE1

PW

LED

JPA2 JPA

3

DA1

DA2

ICH5R

PXH

L

i

n

d

e

n

h

u

r

s

t

Clear CMOS

CHB SCSI LED

CHA SCSI LED

(South Bridge)

E7520

82801ER

SCSI CH A Term

SCSI CH B Term

Floppy

Chapter 2: Installation

2-27

IDE Connectors

There are no jumpers to configure the onboard IDE#1 and #2 connectors (at J3 and J4, respectively). See the table on the right for pin definitions.

Pin Number Function 1 Reset IDE 3 H o s t Data 7 5 H o s t Data 6 7 H o s t Data 5 9 H o s t Data 4 11 Host D a ta 3 13 Host D a ta 2 15 Host D a ta 1 17 Host D a ta 0 19 GND 21 DRQ 3 23 I/O W rite 25 I/O Read 27 IOCHRDY 29 DA C K3 31 IRQ1 4 33 Addr 1 35 Addr 0 37 Chip Selec t 0 39 Activity

Pin Number Function 2 GN D 4 Hos t D a ta 8 6 Hos t D a ta 9 8 Host Data 10 10 Hos t Data 11 12 Hos t Data 12 14 Hos t Data 13 16 Hos t Data 14 18 Hos t Data 15 20 Ke y 22 GN D 24 GN D 26 GN D 28 BA L E 30 GN D 32 IOCS 1 6 34 GN D 36 Addr 2 38 Ch ip Selec t 1 40 GN D

IDE Connector Pin Definitions

GLAN1

®

S

U

P

E

R

X

6D

H

8-X

G

2

GLAN2

D

IM

M

2

B

(B

a

n

k

2

)

D

IM

M

2

A

(B

a

n

k

2

)

D

IM

M

3

B

(B

a

n

k

3

)

D

IM

M

3

A

(B

a

n

k

3

)

D

IM

M

4

B

(B

a

n

k

4

)

D

IM

M

4

A

(B

a

n

k

4

)

D

IM

M

1

A

(B

a

n

k

1

)

D

IM

M

1

B

(B

a

n

k

1

)

Fan1

8-pin PWR

PWR SMBus

CPU Fan1

JF1

F

P

C

o

n

tr

o

l

JD1

S

P

K

PW LED

JP15

Fan2

OH

3rd PS

PWR

Fault

Detect

CPU Fan2

Fan3

CH Intru

JL1

W

D Enable

IPM

I

IDE1

ID

E

2

F

lo

p

y

BIO

S

J

1

8

JPA1

Ultra 320

S

C

S

I C

H

A

U

l

t

r

a

3

2

0

S

C

S

I

C

H

B

F

a

n

4

7902

C

TR

L

SATA0

SATA1

U

SB

2/3

SM

BU

S

Buzzer

P

C

I

-

X

1

0

M

H

z

Z

C

R

P

C

I

-

X

2

1

0

M

H

z

P

C

I

-

X

#

3

1

3

M

H

z

WOR

Battery

JPL1

G

LAN

CTLR

RA

GE-X

82546

G

LAN

Enable

P

C

I

-

X

#

5

1

3

M

H

z

X

8

P

C

I

-

E

p

x

#

6

Super

I/O

(North B

ridge)

JPG

1

VGA

C

O

M

1

U

S

B

0/1

KB/ M

ouse

Fan5

Fan6

ATX PW

R

4-Pin PW

R

JP16

24-Pin

Force PWR ON

VGA Enable

Fan7

J24

J

P

1

2

Reboot

Option

JP14

JP

13

F

a

n

8

SCSI

CPU 1

CPU 2

A

la

rm

R

es

et

SCSI Enable

PXH

P

C

I

-

X

#

4

1

3

M

H

z

CO

M

2

W

O

L

U

SB

4

P

W

R

Fault

LE1

PW

LED

JPA2 JPA

3

DA1

DA2

ICH5R

PXH

L

i

n

d

e

n

h

u

r

s

t

Clear CMOS

CHB SCSI LED

CHA SCSI LED

(South Bridge)

E7520

82801ER

SCSI CH A Term

SCSI CH B Term

IDE1

IDE2

2-28

X6DH8-XG2/X6DHE-XG2 User's Manual

Ultra320 SCSI Connectors (*X6DH8-XG2 Only)

Refer to the table below for the pin definitions of the Ultra320 SCSI connectors located at JA1 and JA2.

Signal Names

+DB(12) +DB(13) +DB(14) +DB(15) +DB(P1)

+DB(0) +DB(1) +DB(2) +DB(3) +DB(4) +DB(5) +DB(6) +DB(7) +DB(P)

GROUND

DIFFSENS TERMPWR TERMPWR

RESERVED

GROUND

+ATN

GROUND

+BSY +ACK +RST

+MSG

+SEL +C/D

+REQ

+I/O +DB(8) +DB(9)

+DB(10) +DB(11)

Connector

Contact

Number

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Signal Names

-DB(1 2)

-DB(1 3)

-DB(1 4)

-DB(1 5)

-DB(P 1)

-DB(0 )

-DB(1 )

-DB(2 )

-DB(3 )

-DB(4 )

-DB(5 )

-DB(6 )

-DB(7 )

-DB(P ) GROUND GROUND

TERMPWR TERMPWR RESERVED

GROUND

-ATN

GROUND

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68-pin Ultra320 SCSI Connectors (JA1 and JA2)

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3-1

Chapter 3: Troubleshooting

Chapter 3

Troubleshooting

3-1 Troubleshooting Procedures

Use the following procedures to troubleshoot your system. If you have followed all of the procedures below and still need assistance, refer to the ‘Technical Support Procedures’ and/or ‘Returning Merchandise for Service’ section(s) in this chapter.

Note: Always disconnect the power cord before adding, changing or installing any hardware components.

Before Power On

1. Make sure no short circuits exist between the motherboard and chassis.

2. Disconnect all ribbon/wire cables from the motherboard, including those for the keyboard and mouse.

3. Remove all add-on cards.

4. Install one CPU (making sure it is fully seated) and connect the chassis speaker and the power LED to the motherboard. (Check all jumper settings as well.)

5. Use only the correct type of CMOS onboard battery as recommended by the Manufacturer. Do not install the onboard battery upside down to avoid possible explosion.

No Power

1. Make sure no short circuits exist between the motherboard and the chassis.

2. Verify that all jumpers are set to their default positions.

3. Check that the 115V/230V switch on the power supply is properly set.

4. Turn the power switch on and off to test the system.

5. The battery on your motherboard may be old. Check to verify that it still supplies ~3VDC. If it does not, replace it with a new one.

No Video

1. If the power is on but you have no video, remove all the add-on cards and cables.

2. Use the speaker to determine if any beep codes exist. Refer to the Appendix for details on beep codes.

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X6DH8-XG2/X6DHE-XG2 User's Manual

Losing the System’s Setup Configuration

1. Ensure that you are using a high quality power supply. A poor quality power supply may cause the system to lose the CMOS setup information. Refer to Section 1-6 for details on recommended power supplies.

2. The battery on your motherboard may be old. Check to verify that it still supplies ~3VDC. If it does not, replace it with a new one.

3. If the above steps do not fix the Setup Configuration problem, contact your vendor for repairs.

3-2 Technical Support Procedures

Before contacting Technical Support, please take the following steps. Also, note that as a motherboard manufacturer, Super Micro does not sell directly to end-users, so it is best to first check with your distributor or reseller for troubleshooting services. They should know of any possible problem(s) with the specific system configuration that was sold to you.

NOTE

If you are a system integrator, VAR or OEM, a POST diagnos-

tics card is recommended. For I/O port 80h codes, refer to

App. B.

Memory Errors

1. Make sure the DIMM modules are properly and fully installed.

2. Determine if different speeds of DIMMs have been installed and verify that the BIOS setup is configured for the fastest speed of RAM used. It is recommended to use the same RAM speed for all DIMMs in the system.

3. Make sure you are using the correct type of ECC DDR2-400 (PC3200) SDRAM (*recommended by the manufacturer.)

4. Check for bad DIMM modules or slots by swapping a single module between two slots and noting the results.

5. Make sure all memory modules are fully seated in their slots. As an interleaved memory scheme is used, you must install two modules at a time, beginning with Bank 0, then Bank 1, and so on (see Section 2-3).

6. Check the position of the 115V/230V switch on the power supply.

3-3

Chapter 3: Troubleshooting

1. Please go through the ‘Troubleshooting Procedures’ and 'Frequently Asked Question' (FAQ) sections in this chapter or see the FAQs on our web site (http://www.supermicro.com/support/faqs/) before contacting Technical Support.

2. BIOS upgrades can be downloaded from our web site at

(http://www.supermicro.com/support/bios/).

Note: Not all BIOS can be flashed depending on the modifications to the boot block code.

3. If you still cannot resolve the problem, include the following information

when contacting Super Micro for technical support:

• Motherboard model and PCB revision number

• BIOS release date/version (this can be seen on the initial display when your system first boots up)

•System configuration An example of a Technical Support form is on our web site at

(http://www.supermicro.com/support/contact.cfm).

4. Distributors: For immediate assistance, please have your account number ready when placing a call to our technical support department. We can be reached by e-mail at support@supermicro.com, by phone at:

(408) 503-8000, option 2, or by fax at (408)503-8019.

3-3 Frequently Asked Questions

Question: What are the various types of memory that my motherboard can support?

Answer: The X6DH8-XG2/X6DHE-XG2 has eight 240-pin DIMM slots that

support registered ECC DDR2-400 (PC3200) SDRAM modules. It is strongly recommended that you do not mix memory modules of different speeds and sizes.

Question: How do I update my BIOS?

Answer: It is recommended that you do not upgrade your BIOS if you are

experiencing no problems with your system. Updated BIOS files are located on our web site at http://www.supermicro.com. Please check our BIOS warning message and the info on how to update your BIOS on our web site. Also, check the current BIOS revision and make sure it is newer than your BIOS before downloading. Select your motherboard model and download the BIOS file to your computer. Unzip the BIOS update file and you will find the readme.txt (flash instructions), the phlash.exe (BIOS flash utility), the platform.bin (platform file) and the BIOS image (xxxxxx.rom) files. Copy these files onto a bootable floppy and reboot your system. It is not neces-

3-4

X6DH8-XG2/X6DHE-XG2 User's Manual

sary to set BIOS boot block protection jumpers on the motherboard. At the DOS prompt, enter the command "phlash." This will start the flash utility and give you an opportunity to save your current BIOS image. Flash the boot block and enter the name of the update BIOS image file.

Question: What's on the CD that came with my motherboard?

Answer: The supplied compact disc has quite a few drivers and programs

that will greatly enhance your system. We recommend that you review the CD and install the applications you need. Applications on the CD include chipset drivers for Windows and security and audio drivers.

3-4 Returning Merchandise for Service

A receipt or copy of your invoice marked with the date of purchase is required before any warranty service will be rendered. You can obtain service by calling your vendor for a Returned Merchandise Authorization (RMA) number. When returning to the manufacturer, the RMA number should be prominently displayed on the outside of the shipping carton, and mailed prepaid or hand-carried. Shipping and handling charges will be applied for all orders that must be mailed when service is complete.

This warranty only covers normal consumer use and does not cover damages incurred in shipping or from failure due to the alternation, misuse, abuse or improper maintenance of products.

During the warranty period, contact your distributor first for any product problems.

Chapter 4: BIOS

4-1

Chapter 4

BIOS

4-1 Introduction

This chapter describes the Phoenix BIOS™ Setup utility for the X6DH8-XG2/ X6DHE-XG2. The Phoenix ROM BIOS is stored in a flash chip and can be easily upgraded using a floppy disk-based program.

Note: Due to periodic changes to the BIOS, some settings may have been added or deleted and might not yet be recorded in this manual. Please refer to the Manual Download area of the Supermicro web site <http://www.supermicro.com> for any changes to the BIOS that may not be reflected in this manual.

System BIOS

The BIOS is the Basic Input Output System used in all IBM® PC, XT™, AT®, and PS/2® compatible computers. The Phoenix BIOS stores the system parameters, such as types of disk drives, video displays, etc. in the CMOS. The CMOS memory requires very little electrical power. When the computer is turned off, a backups battery provides power to the CMOS Logic, enabling it to retain system parameters. Each time the computer is powered-on the computer is configured with the values stored in the CMOS Logic by the system BIOS, which gains control at boot-up.

How To Change the Configuration Data

The CMOS information that determines the system parameters may be changed by entering the BIOS Setup utility. This Setup utility can be accessed by pressing the <Delete> key at the appropriate time during system boot. (See below.)

Starting the Setup Utility

Normally, the only visible POST (Power On Self Test) routine is the memory test. As the memory is being tested, press the <Delete> key to enter the main menu of the BIOS Setup utility. From the main menu, you can access the other setup screens, such as the Security and Power menus. Beginning with Section 4-3, detailed descriptions are given for each parameter setting in the Setup utility.

Warning: Do not shut down or reset the system while updating BIOS to prevent possible boot failure.

4-2

X6DH8-XG2/X6DHE-XG2 User's Manual

4-2 Running Setup

*Default settings are in bold text unless otherwise noted.

The BIOS setup options described in this section are selected by choosing the appropriate text from the main BIOS Setup screen. All displayed text is described in this section, although the screen display is often all you need to understand how to set the options (see next page).

When you first power on the computer, the Phoenix BIOS™ is immediately activated.

While the BIOS is in control, the Setup program can be activated in one of two ways:

1. By pressing <Delete> immediately after turning the system on, or

2. When the message shown below appears briefly at the bottom of the screen during the POST (Power On Self-Test), press the <Delete> key to activate the main Setup menu:

Press the <Delete> key to enter Setup

4-3 Main BIOS Setup

All main Setup options are described in this section. The main BIOS Setup screen is displayed below.

Use the Up/Down arrow keys to move among the different settings in each menu. Use the Left/Right arrow keys to change the options for each setting.

Press the <Esc> key to exit the CMOS Setup Menu. The next section describes in detail how to navigate through the menus.

Items that use submenus are indicated with the Xicon. With the item highlighted, press the <Enter> key to access the submenu.

Chapter 4: BIOS

4-3

Main BIOS Setup Menu

Main Setup Features

System Time

To set the system date and time, key in the correct information in the appropriate fields. Then press the <Enter> key to save the data.

System Date

Using the arrow keys, highlight the month, day, and year fields and enter the correct data. Press the <Enter> key to save the data.

BIOS Date

This feature allows the BIOS to automatically display the date when this version of BOIS was built.

4-4

X6DH8-XG2/X6DHE-XG2 User's Manual

Legacy Diskette A

This setting allows the user to set the type of floppy disk drive installed as diskette A. The options are Disabled, 360Kb 5.25 in, 1.2MB 5.25 in, 720Kb

3.5 in, 1.44/1.25MB, 3.5 in and 2.88MB 3.5 in.

Parallel ATA

This setting allows the user to enable or disable the function of Parallel ATA. The options are Disabled, Channel 0, Channel 1 and Both.

Serial ATA

This setting allows the user to enable or disable the function of Serial ATA. The options are Disabled and Enabled.

Serial ATA RAID Feature

Select Enable to enable Serial ATA RAID Functions. (*For the Windows OS environment, use the RAID driver if this feature is set to "Enabled". If "disabled", use the "Non-RAID" driver.)

Native Mode Operation

This setting allows the user to select the Native Mode for the operation of ATA. The options are Parallel ATA, Serial ATA, Both and Auto.

Chapter 4: BIOS

4-5

XX

XIDE Channel 0 Master/Slave, IDE Channel 1 Master/Slave, IDE

Channel 2 Master, IDE Channel 3 Master

These settings allow the user to set the parameters of IDE Channel 0 Master/Slave, IDE Channel 1 Master/Slave, IDE Channel 2 Master, IDE

Channel 3 Master slots. Hit <Enter> to activate the following sub-menu screen for detailed options of these items. Set the correct configurations accordingly. The items included in the sub-menu are:

Type

Selects the type of IDE hard drive. The options are Auto, (which allows the BIOS to automatically determine the hard drive's capacity, number of heads, etc.), a number from 1-39 to select a predetermined type of hard drive, CDROM and ATAPI Removable. The option "User" will allow the user to enter the parameters of the HDD installed at this connection. The option "Auto" will allow the BIOS to automatically configure the parameters of the HDD installed at the connection. Choose the option 139 to select a predetermined HDD type. Select CDROM if a CDROM drive is installed. Select ATAPI if a removable disk drive is installed.

4-6

X6DH8-XG2/X6DHE-XG2 User's Manual

CHS Format

The following items will be displayed by the BIOS:

TYPE: This item displays the type of IDE or SATA devices. Cylinders: This item indicates the status of Cylinders. Headers: This item indicates the number of headers. Sectors: This item displays the number of sectors. Maximum Capacity: This item displays the maximum storage capacity

of the system.

LBA Format

The following items will be displayed by the BIOS: Total Sectors: This item displays the number of total sectors available

in the LBA Format. Maximum Capacity: This item displays the maximum capacity in the

LBA Format.

Multi-Sector Transfer

This item allows the user to specify the number of sectors per block to be used in multi-sector transfer. The options are Disabled, 4 Sectors, 8 Sectors and 16 Sectors.

LBA Mode Control

This item determines whether the Phoenix BIOS will access the IDE Channel 0 Master Device via the LBA mode. The options are Enabled and

Disabled.

32 Bit I/O

This option allows the user to enable or disable the function of 32-bit data transfer. The options are Enabled and Disabled.

Transfer Mode

Selects the transfer mode. The options are Standard, Fast PIO1, Fast PIO2, Fast PIO3, Fast PIO4, FPIO3/DMA1 and FPIO4/DMA2.

Ultra DMA Mode

Selects Ultra DMA Mode. The options are Disabled, Mode 0, Mode 1, Mode 2, Mode 3, Mode 4 and Mode 5.

Chapter 4: BIOS

4-7

System Memory This display informs you how much system memory is recognized as being

present in the system.

Extended Memory

This display informs you how much extended memory is recognized as being present in the system.

4-4 Advanced Setup

Choose Advanced from the Phoenix BIOS Setup Utility main menu with the arrow keys. You should see the following display. The items with a triangle beside them have sub menus that can be accessed by highlighting the item and pressing <Enter>. All Advanced BIOS Setup options are described in this section.

4-8

X6DH8-XG2/X6DHE-XG2 User's Manual

XX

XBoot Features

Access the submenu to make changes to the following settings.

Quick Boot Mode

If enabled, this feature will speed up the POST (Power On Self Test) routine by skipping certain tests after the computer is turned on. The settings are Enabled and Disabled. If Disabled, the POST routine will run at normal speed.

Quiet Boot

This setting allows you to Enable or Disable the graphic logo during bootup.

ACPI Mode

Use the setting to determine if you want to employ ACPI (Advanced Configuration and Power Interface) power management on your system. The options are Yes and No.

Power Button Behavior

If set to Instant-Off, the system will power off immediately as soon as the user hits the power button. If set to 4-sec, the system will power off when the user presses the power button for 4 seconds or longer. The options are instant-off and 4-sec override.

Resume On Modem Ring

Select On to “wake your system up” when an incoming call is received by your modem. The options are On and Off.

After Power Failure

This setting allows you to choose how the system will react when power returns after an unexpected loss of power. The options are Stay Off and Power On.

Watch Dog

This setting is for enabling the Watch Dog feature. The options are Enabled and Disabled.

Summary Screen

This setting allows you to Enable or Disable the summary screen which displays the system configuration during bootup.

Chapter 4: BIOS

4-9

XX

XMemory Cache

Cache System BIOS Area

This setting allows you to designate a reserve area in the system memory to be used as a System BIOS buffer to allow the BIOS write (cache) its data into this reserved memory area. Select "Write Protect" to enable this function, and this area will be reserved for the BIOS ROM access only. Select "Uncached" to disable this function and make this area available for other devices.

Cache Video BIOS Area

This setting allows you to designate a reserve area in the system memory to be used as a Video BIOS buffer to allow the BIOS write (cache) its data into this reserved memory area. Select "Write Protect" to enable the function and this area will be reserved for the BIOS ROM access only. Select "Uncached" to disable this function and make this area available for other devices.

Cache Base 0-512K

If enabled, this feature will allow the data stored in the base memory area: block 0-512K to be cached (written) into a buffer, a storage area in the Static DRM (SDROM) or written into L1, L2, L3 cache inside the CPU to speed up CPU operations . Select "Uncached" to disable this function. Select "Write Through" to allow data to be cached into the buffer and written into the system memory at the same time. Select "Write Protect" to prevent data from being written into the base memory area of Block 0-512K. Select "Write Back" to allow CPU to write data back directly from the buffer without writing data to the System Memory for fast CPU data processing and operation. The options are Uncached, Write Through, Write Protect, and

Write Back"

Cache Base 512K-640K

If enabled, this feature will allow the data stored in the memory area: 512K640K to be cached (written) into a buffer, a storage area in the Static DRM (SDROM) or written into L1, L2, L3 cache inside the CPU to speed up CPU operations . Select "Uncached" to disable this function. Select "Write Through" to allow data to be cached into the buffer and written into the system memory at the same time. Select "Write Protect" to prevent data from being written into the base memory area of Block 0-512K. Select "Write Back" to allow CPU to write data back directly from the buffer without writing data to the System Memory for fast CPU data processing and operation. The options are Uncached, Write Through, Write Protect, and

Write Back"

4-10

X6DH8-XG2/X6DHE-XG2 User's Manual

Cache Extended Memory If enabled, this feature will allow the data stored in the extended memory

area to be cached (written) into a buffer, a storage area in the Static DRM (SDROM) or written into L1, L2, L3 cache inside the CPU to speed up CPU operations . Select "Uncached" to disable this function. Select "Write Through" to allow data to be cached into the buffer and written into the system memory at the same time. Select "Write Protect" to prevent data from being written into the base memory area of Block 0-512K. Select "Write Back" to allow CPU to write data back directly from the buffer without writing data to the System Memory for fast CPU data processing and operation. The options are Uncached, Write Through, Write Protect, and

Write Back.

Discrete MTRR Allocation

If enabled, MTRRs (-Memory Type Range Registers) are configured as distinct, separate units and cannot be overlapped. If enabled, the user can achieve better graphic effects when using a Linux graphic driver that requires the write-combining configuration with 4GB or more memory. The options are Enabled and Disabled.

XX

XPCI Configuration

Access the submenu to make changes to the following settings for PCI devices.

Onboard GLAN (Gigabit- LAN) OPROM Configure

Enabling this option provides the capability to boot from GLAN. The options are Enabled and Disabled.

Onboard SCSI OPROM Configure

Enabling this option provides the capability to boot from SCSI HDD. The options are Disabled and Enabled.

Default Primary Video Adapter

This item allows the user to select the Primary Video Adapter between two adapters instead of selecting among three or more adapters. The options are Other and Onboard Video.

PCI Parity Error Forwarding

Enable this item to forward the PCI errors occurring behind P2P bridges to the South Bridge, so NMI can be asserted. The options are Enabled and Disabled.

Chapter 4: BIOS

4-11

ROM Scan Ordering

This feature allows the user to decide which Option ROM to be activated first. The options are Onboard first and Add-On first.

Reset Configuration Data

If set to Yes, this setting clears the Extended System Configuration Data(ESCD) area. The options are Yes and No.

Frequency for PCIX#1-#2/SCSI

This option allows the user to change the bus frequency for the devices installed in the slot indicated. The options are Auto, PCI 33 MHz, PCI 66 MHz, PCI-X 66 MHz, PCI-X 100 MHz, and PCI-X 133 MHz.

Frequency for PCIX#3/G-LAN

This option allows the user to change the bus frequency of the devices installed in the slot indicated. The options are Auto, PCI 33 MHz, PCI 66 MHz, PCI-X 66 MHz, PCI-X 100 MHz, and PCI-X 133 MHz.

Frequency for PCI-X #4/PCI-X #5

This option allows the user to change the bus frequency of the devices installed in the slot indicated. The options are Auto, PCI 33 MHz, PCI 66 MHz, PCI-X 66 MHz, PCI-X 100 MHz, and PCI-X 133 MHz.

XX

XPCI-X 100MHz ZCR Slot #1/PCI-X 100MHz Slot#2/PCI-X 133MHz

Slot #3/PCI-X 133MHz Slot#4/ PCI-X 133MHz Slot#5/PCI-Exp x8 Slot#6

Access the submenu for each of the settings above to make changes to the following:

Option ROM Scan

When enabled, this setting will initialize the device expansion ROM. The options are Enabled and Disabled.

Enable Master

This setting allows you to enable the selected device as the PCI bus master. The options are Enabled and Disabled.

4-12

X6DH8-XG2/X6DHE-XG2 User's Manual

Latency Timer

This setting allows you to set the clock rate for Bus Master. A highpriority, high-throughout device may benefit from a greater clock rate. The options are Default, 0020h, 0040h, 0060h, 0080h, 00A0h, 00C0h, and 00E0h. For Unix, Novelle and other Operating Systems, please select

the option: other. If a drive fails after the installation of a new software, you might want to change this setting and try again. A different OS requires a different Bus Master clock rate.

Large Disk Access Mode

This setting determines how large hard drives are to be accessed. The options are DOS or Other (for Unix, Novelle NetWare and other operating systems).

XX

XAdvanced Chipset Control

Access the submenu to make changes to the following settings.

Force Compliance Mode

If enabled, this feature sets the device specified to comply with the PCIExpress Compliance 1.0 Mode. The options are: Disabled and Enabled.

Memory RAS Feature Control

Select this option to enable the Memory RAS Feature Control. The options are Standard, Sparing, and Mirroring.

Clock Spectrum Feature

If "Enabled", the BIOS will monitor the level of Electromagnetic Interference caused by the components and will attempt to decrease the interference whenever needed. The options are Enabled and Disabled.

Memory Remap Function Control

PCI memory resources will overlap with the physical memory if 4GB of memory or above is installed on the motherboard. When this occurs, enable this function to reallocate the overlapped physical memory to a location above 4GB to resolve the memory overlapping situation.

DRAM Data Integrity Mode

If enabled, this feature allows the data stored in the DRAM memory to be integrated for faster data processing. The options are 72-bit ECC, 144-bit ECC, Auto and Disabled.

Chapter 4: BIOS

4-13

ECC Error Type

This setting lets you select which type of interrupt to be activated as a result of an ECC error. The options are None, NMI (Non-Maskable Interrupt),

SMI (System Management Interrupt) and SCI (System Control Interrupt.)

SERR Signal Condition

This setting specifies the ECC Error conditions that an SERR# is to be asserted. The options are None, Single Bit, Multiple Bit, and Both.

Enabling Multi-Media Timer

Select Yes to activate a set of timers that are alternative to the traditional 8254 timers for the OS use. The options are Yes and No.

USB Function

Select Enabled to enable the function of USB devices specified. The settings are Enabled and Disabled.

Legacy USB Support

This setting allows you to enable support for Legacy USB devices. The settings are Enabled and Disabled.

XX

XAdvanced Processor Options

Access the submenu to make changes to the following settings.

CPU Speed

This is a display that indicates the speed of the installed processor.

Hyper-threading (*Available when supported by the CPU.)

Set to Enabled to use the Hyper-Threading Technology, which will result in increased CPU performance. The options are Disabled and Enabled.

Machine Checking (*Available when supported by the CPU.)

Set to Enabled to activate the function of Machine Checking and allow the CPU to detect and report hardware (machine) errors via a set of modelspecific registers (MSRs). The options are Disabled and Enabled.

C1 Enhanced Mode (*Available when supported by the CPU.)

Set to Enabled to enable Enhanced Halt State to lower CPU voltage/frequency to prevent overheat. The options are Enabled and Disabled. (*Note: please refer to Intel’s web site for detailed information.)

4-14

X6DH8-XG2/X6DHE-XG2 User's Manual

No Execute Mode Memory Protection (*Available when supported

by the CPU and the OS.)

Set to Enabled to enable Execute Disable Bit and allow the processor to classify areas in memory where an application code can execute and where it cannot, and thus preventing a worm or a virus from inserting and creating a flood of codes to overwhelm the processor or damage the system during an attack.

(*Note: this feature is available when your OS and your CPU support the function of Execute Disable Bit.) The options are Disabled and Enabled. (Note: For more information regarding hardware/software support for this function, please refer to Intel's and Microsoft's web sites.)

Thermal Management 2 (*Available when supported by the CPU.)

Set to Enabled to use Thermal Management 2 (TM2) which will lower CPU voltage and frequency when the CPU temperature reaches a predefined overheat threshold. Set to Disabled to use Thermal Manager 1 (TM1), allowing CPU clocking to be regulated via CPU Internal Clock modulation

when the CPU temperature reaches the overheat threshold.

Adjacent Cache Line Prefetch (*Available when supported by the

CPU.)

The CPU fetches the cache line for 64 bytes if this option is set to Disabled. The CPU fetches both cache lines for 128 bytes as comprised if Enabled. The options are Disabled and Enabled.

Processor Power Management

This feature allows the user to determine the processor power management mode. The options are Disabled and C States Only. If set to Disabled, C States and GV1/GV3 are disabled. If set to C States only, the processor power will be controlled through CPU power states in the APCI setting.

XX

XI/O Device Configuration

Access the submenu to make changes to the following settings.

KBC Clock Input

This setting allows you to select clock frequency for KBC. The options are 6MHz, 8MHz, 12MHz, and 16MHz.

Onboard COM 1

This setting allows you to assign control of serial port A. The options are Enabled (user defined), Disabled and Auto (BIOS controlled).

Chapter 4: BIOS

4-15

Base I/O Address

Select the base I/O address for serial port A. The options are 3F8/IRQ4, 2F8/IRQ3, 3E8/IRQ4 and 2E8/IRQ3.

Onboard COM 2

This setting allows you to assign control of serial port B. The options are

Enabled (user defined), Disabled and Auto (BIOS controlled).

Base I/O Address

Select the base I/O address for serial port B. The options are 3F8/IRQ4,

2F8/IRQ3, 3E8/IRQ4 and 2E8/IRQ3.

Floppy Disk Controller

This setting allows you to assign control of the floppy disk controller. The options are Enabled (user defined), Disabled, Auto (BIOS controlled) and OS Controlled.

XX

XDMI Event Logging

Access the submenu to make changes to the following settings.

Event Log Validity

This is a display to inform you of the event log validity. It is not a setting.

Event Log Capacity

This is a display to inform you of the event log capacity. It is not a setting.

View DMI Event Log

Highlight this item and press <Enter> to view the contents of the event log.

Event Logging

This setting allows you to Enable or Disable event logging.

ECC Event Logging

This setting allows you to Enable or Disable ECC event logging.

Mark DMI Events as Read

Highlight this item and press <Enter> to mark the DMI events as read.

Clear All DMI Event Logs

Select Yes and press <Enter> to clear all DMI event logs. The options are Yes and No.

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XX

XConsole Redirection

Access the submenu to make changes to the following settings.

COM Port Address

Specifies to redirect the console to Onboard COM A or Onboard COM B. This setting can also be Disabled.

BAUD Rate

Select the BAUD rate for console redirection. The options are 300, 1200, 2400, 9600, 19.2K, 38.4K, 57.6K and 115.2K.

Console Type

Choose from the available options to select the console type for console redirection. The options are VT100, VT100,8bit, PC-ANSI, 7bit, PC ANSI, VT100+, VT-UTF8.

Flow Control

Choose from the available options to select the flow control for console redirection. The options are: None, XON/XOFF, and CTS/RTS.

Console Connection

Select the console connection: either Direct or Via Modem.

Continue CR after POST

Choose whether to continue with console redirection after the POST routine. The options are On and Off.

XX

XHardware Monitor Logic

CPU Temperature Threshold

This option allows the user to set a CPU temperature threshold that will activate the alarm system when the CPU temperature reaches this preset

temperature threshold. The options are 75oC, 80oC, 85oC and 90oC.

Highlight this and hit <Enter> to see monitor data for the following items:

CPU1/2 Temperatures: This item displays the temperatures of CPU1/2. LM 93 Temperature: This item displays the temperature of LM93.

LM 30 Temperature: This item displays the temperature of LM30.

Chapter 4: BIOS

4-17

Fan Speed Control Modes

This feature allows the user to decide how the system controls the speeds of the onboard fans. The CPU temperature and the fan speed are correlative. When the CPU on-die temperature increases, the fan speed will also increase, and vise versa. If the option is set to “3-pin fan”, the fan speed is controlled by voltage. If the option is set to “4-pin”, the fan speed will be controlled by Pulse Width Modulation (PWM). Select “3-pin” if your chassis came with 3-pin fan headers. Select “4-pin” if your chassis came with 4-pin fan headers. Select “Workstation” if your system is used as a Workstation. Select “Server” if your system is used as a Server. Select “Disable” to disable the fan speed control function to allow the onboard fans to run at the full speed (12V) at all the time. The Options are: 1. Disable, 2. 3-pin

The following items will be also displayed:

Fan 1-FAN6/Fan 7(CPU Fan1)/Fan 8(CPU Fan2) Speeds

P12V_CPU1_SCALED: This item displays the voltage status of CPU1

+12V power. P12V_CPU2_SCALED: This item displays the voltage status of CPU2

+12V Power.

P12V_SCALED: This item displays the voltage status of CPU 12V power. CPU Vio: This item displays the voltage status of onboard CPU I/Os. MCH/PXH Vcore: This item displays the voltage status of MCH (North

Bridge) and PXH (I/O Hub).

ICH Vcore: This item displays the voltage status of ICH (South Bridge).

CPU1/CPU2 Vcore: This item displays the voltage status of CPU1/2 core

power.

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4-5 Security

Choose Security from the Phoenix BIOS Setup Utility main menu with the arrow keys. You should see the following display. Security setting options are displayed by highlighting the setting using the arrow keys and pressing <Enter>. All Security BIOS settings are described in this section.

Supervisor Password Is:

This displays whether a supervisor password has been entered for the system. Clear means such a password has not been used and Set means a supervisor password has been entered for the system.

User Password Is:

This displays whether a user password has been entered for the system. Clear means such a password has not been used and Set means a user password has been entered for the system.

Set Supervisor Password

When the item "Set Supervisor Password" is highlighted, hit the <Enter> key. When prompted, type the Supervisor's password in the dialogue box to set or to change supervisor's password, which allows access to the BIOS.

Chapter 4: BIOS

4-19

Set User Password

When the item "Set User Password" is highlighted, hit the <Enter> key. When prompted, type the user's password in the dialogue box to set or to change the user's password, which allows access to the system at bootup.

Fixed Disk Boot Sector This setting may offer some protection against viruses when set to Write

Protect, which protects the boot sector on the hard drive from having a virus written to it. The other option is Normal.

Password on Boot

This setting allows you to require a password to be entered when the system boots up. The options are Enabled (password required) and Disabled (password not required).

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4-6 Boot

Choose Boot from the Phoenix BIOS Setup Utility main menu with the arrow keys. You should see the following display. Highlighting a setting with a + or - will expand or collapse that entry. See details on how to change the order and specs of boot devices in the Item Specific Help window. All Boot BIOS settings are described in this section.

+Removable Devices

Highlight and press <Enter> to expand the field. See details on how to change the order and specs of devices in the Item Specific Help window.

CD-ROM Drive

See details on how to change the order and specs of the CD-ROM drive in the Item Specific Help window.

+Hard Drive

Highlight and press <Enter> to expand the field. See details on how to change the order and specs of hard drives in the Item Specific Help window.

Chapter 4: BIOS

4-21

4-7 Exit

Choose Exit from the Phoenix BIOS Setup Utility main menu with the arrow keys. You should see the following display. All Exit BIOS settings are described in this section.

Exit Saving Changes

Highlight this item and hit <Enter> to save any changes you made and to exit the BIOS Setup utility.

Exit Discarding Changes

Highlight this item and hit <Enter> to exit the BIOS Setup utility without saving any changes you may have made.

Load Setup Defaults

Highlight this item and hit <Enter> to load the default settings for all items in the BIOS Setup. These are the safest settings to use.

Discard Changes

Highlight this item and hit <Enter> to discard (cancel) any changes you made. You will remain in the Setup utility.

Save Changes

Highlight this item and hit <Enter> to save any changes you made. You will remain in the Setup utility.

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Notes

A-1

Appendix A: BIOS POST Messages

Appendix A

BIOS POST Messages

During the Power-On Self-Test (POST), the BIOS will check for problems. If a problem is found, the BIOS will activate an alarm or display a message. The following is a list of such BIOS messages.

Failure Fixed Disk

Fixed disk is not working or not configured properly. Check to see if fixed disk is attached properly. Run Setup. Find out if the fixed-disk type is correctly identified.

Stuck key

Stuck key on keyboard.

Keyboard error

Keyboard not working.

Keyboard Controller Failed

Keyboard controller failed test. May require replacing keyboard controller.

Keyboard locked - Unlock key switch

Unlock the system to proceed.

Monitor type does not match CMOS - Run SETUP

Monitor type not correctly identified in Setup

Shadow Ram Failed at offset: nnnn

Shadow RAM failed at offset nnnn of the 64k block at which the error was detected.

System RAM Failed at offset: nnnn

System RAM failed at offset nnnn of in the 64k block at which the error was detected.

Extended RAM Failed at offset: nnnn Extended memory not working or not configured properly at offset nnnn.

System battery is dead - Replace and run SETUP

The CMOS clock battery indicator shows the battery is dead. Replace the battery and run Setup to reconfigure the system.

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System CMOS checksum bad - Default configuration used

System CMOS has been corrupted or modified incorrectly, perhaps by an application program that changes data stored in CMOS. The BIOS installed Default Setup Values. If you do not want these values, enter Setup and enter your own values. If the error persists, check the system battery or contact your dealer.

System timer error

The timer test failed. Requires repair of system board.

Real time clock error

Real-Time Clock fails BIOS hardware test. May require board repair.

Check date and time settings

BIOS found date or time out of range and reset the Real-Time Clock. May require setting legal date (1991-2099).

Previous boot incomplete - Default configuration used

Previous POST did not complete successfully. POST loads default values and offers to run Setup. If the failure was caused by incorrect values and they are not corrected, the next boot will likely fail. On systems with control of wait states, improper Setup settings can also terminate POST and cause this error on the next boot. Run Setup and verify that the waitstate configuration is correct. This error is cleared the next time the system is booted.

Memory Size found by POST differed from CMOS

Memory size found by POST differed from CMOS.

Diskette drive A error Diskette drive B error

Drive A: or B: is present but fails the BIOS POST diskette tests. Check to see that the drive is defined with the proper diskette type in Setup and that the diskette drive is attached correctly.

Incorrect Drive A type - run SETUP

Type of floppy drive A: not correctly identified in Setup.

Incorrect Drive B type - run SETUP

Type of floppy drive B: not correctly identified in Setup.

A-3

Appendix A: BIOS POST Messages

System cache error - Cache disabled

RAM cache failed and BIOS disabled the cache. On older boards, check the cache jumpers. You may have to replace the cache. See your dealer. A disabled cache slows system performance considerably.

CPU ID:

CPU socket number for Multi-Processor error.

EISA CMOS not writeable

ServerBIOS2 test error: Cannot write to EISA CMOS.

DMA Test Failed

ServerBIOS2 test error: Cannot write to extended DMA (Direct Memory Access) registers.

Software NMI Failed

ServerBIOS2 test error: Cannot generate software NMI (Non-Maskable Interrupt).

Fail-Safe Timer NMI Failed

ServerBIOS2 test error: Fail-Safe Timer takes too long.

device Address Conflict Address conflict for specified device.

Allocation Error for: device

Run ISA or EISA Configuration Utility to resolve resource conflict for the specified device.

CD ROM Drive

CD ROM Drive identified.

Entering SETUP ...

Starting Setup program

Failing Bits: nnnn

The hex number nnnn is a map of the bits at the RAM address which failed the memory test. Each 1 (one) in the map indicates a failed bit. See errors 230, 231, or 232 above for offset address of the failure in System, Extended, or Shadow memory.

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Fixed Disk n Fixed disk n (0-3) identified.

Invalid System Configuration Data

Problem with NVRAM (CMOS) data.

I/O device IRQ conflict

I/O device IRQ conflict error.

PS/2 Mouse Boot Summary Screen:

PS/2 Mouse installed.

nnnn kB Extended RAM Passed Where nnnn is the amount of RAM in kilobytes successfully tested.

nnnn Cache SRAM Passed Where nnnn is the amount of system cache in kilobytes successfully tested.

nnnn kB Shadow RAM Passed

Where nnnn is the amount of shadow RAM in kilobytes successfully tested.

nnnn kB System RAM Passed Where nnnn is the amount of system RAM in kilobytes successfully tested.

One or more I2O Block Storage Devices were excluded from the Setup Boot Menu

There was not enough room in the IPL table to display all installed I2O blockstorage devices.

Operating system not found

Operating system cannot be located on either drive A: or drive C:. Enter Setup and see if fixed disk and drive A: are properly identified.

Parity Check 1 nnnn

Parity error found in the system bus. BIOS attempts to locate the address and display it on the screen. If it cannot locate the address, it displays ????. Parity is a method for checking errors in binary data. A parity error indicates that some data has been corrupted.

A-5

Appendix A: BIOS POST Messages

Parity Check 2 nnnn

Parity error found in the I/O bus. BIOS attempts to locate the address and display it on the screen. If it cannot locate the address, it displays ????.

Press <F1> to resume, <F2> to Setup, <F3> for previous

Displayed after any recoverable error message. Press <F1> to start the boot process or <F2> to enter Setup and change the settings. Press <F3> to display the previous screen (usually an initialization error of an Option ROM, i.e., an add-on card). Write down and follow the information shown on the screen.

Press <F2> to enter Setup

Optional message displayed during POST. Can be turned off in Setup.

PS/2 Mouse:

PS/2 mouse identified.

Run the I2O Configuration Utility

One or more unclaimed block storage devices have the Configuration Request bit set in the LCT. Run an I2O Configuration Utility (e.g. the SAC utility).

System BIOS shadowed

System BIOS copied to shadow RAM.

UMB upper limit segment address: nnnn

Displays the address nnnn of the upper limit of Upper Memory Blocks, indicating released segments of the BIOS which can be reclaimed by a virtual memory manager.

Video BIOS shadowed

Video BIOS successfully copied to shadow RAM.

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Notes

Appendix B: BIOS POST Codes

B-1

This section lists the POST (Power On Self Test) codes for the PhoenixBIOS. POST codes are divided into two categories: recoverable and terminal.

Recoverable POST Errors

When a recoverable type of error occurs during POST, the BIOS will display an POST code that describes the problem. BIOS may also issue one of the following beep codes:

1 long and two short beeps - video configuration error 1 repetitive long beep - no memory detected

Terminal POST Errors

If a terminal type of error occurs, BIOS will shut down the system. Before doing so, BIOS will write the error to port 80h, attempt to initialize video and write the error in the top left corner of the screen. The following is a list of codes that may be written to port 80h.

Appendix B

BIOS POST Codes

POST Code Description

01h IPMI Initialization 02h Verify Real Mode 03 h Disable Non-Maskable Interrupt (NMI) 04h Get CPU type 06h Initialize system hardware 07 h Disable shadow and execute code from the ROM. 08 h Initialize chipset with initial POST values 09h Set IN POST flag 0Ah Initialize CPU registers 0Bh Enable CPU cache 0C h Initialize caches to initial POST values 0Eh Initialize I/O component 0Fh Initialize the local bus IDE 10 h Initialize Power Management 11 h Load alternate registers with initial POST values 12 h Restore CPU control word during warm boot 13 h Reset PCI Bus Mastering devices 14 h Initialize keyboard controller 16 h 1-2-2-3 BIOS ROM checksum 17 h Initialize cache before memory Auto size

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X6DH8-XG2/X6DHE-XG2 User's Manual

POST Code Description

18h 8254 timer initialization 1Ah 8237 DMA controller initialization 1Ch Reset Programmable Interrupt Controller 20 h 1-3-1-1 Test DRAM refresh 22 h 1-3-1-3 Test 8742 Keyboard Controller 24 h Set ES segment register to 4 GB 28h Auto size DRAM 29h Initialize POST Memory Manager 2Ah Clear 512 kB base RAM 2Ch 1-3-4-1 RAM failure on address line xxxx* 2Eh 1-3-4-3 RAM failure on data bits xxxx* of low byte of

memory bus 2Fh Enable cache before system BIOS shadow 32 h Test CPU bus-clock frequency 33 h Initialize Phoenix Dispatch Manager 36 h Warm start shut down 38 h Shadow system BIOS ROM 3Ah Auto size cache 3C h Advanced configuration of chipset registers 3D h Load alternate registers with CMOS values 41 h Initialize extended memory for RomPilot (optional) 42 h Initialize interrupt vectors 45 h POST device initialization 46 h 2-1-2-3 Check ROM copyright notice 48 h Check video configuration against CMOS 49 h Initialize PCI bus and devices 4Ah Initialize all video adapters in system 4Bh QuietBoot start (optional) 4Ch Shadow video BIOS ROM 4Eh Display BIOS copyright notice 4Fh Initialize MultiBoot 50 h Display CPU type and speed 51 h Initialize EISA board (optional) 52 h Test keyboard 54h Set key click if enabled 55 h Enable USB devices 58 h 2-2-3-1 Test for unexpected interrupts 59 h Initialize POST display service 5Ah Display prompt “Press <ESC> to enter SETUP” 5Bh Disable CPU cache

Appendix B: BIOS POST Codes

B-3

POST Code Description

5Ch Test RAM between 512 and 640 kB 60 h Test extended memory 62h Test extended memory address lines 64h Jump to UserPatch1 66h Configure advanced cache registers 67 h Initialize Multi Processor APIC 68 h Enable external and CPU caches 69h Setup System Management Mode (SMM) area 6Ah Display external L2 cache size 6Bh Load custom defaults (optional) 6Ch Display shadow-area message 70h Display error messages 72 h Check for configuration errors 76 h Check for keyboard errors 7C h Set up hardware interrupt vectors 7D h Initialize Intelligent System Monitoring (optional) 7Eh Initialize coprocessor if present 80 h Disable onboard Super I/O ports and IRQs (optional) 81 h Late POST device initialization 82 h Detect and install external RS232 ports 83 h Configure non-MCD IDE controllers 84 h Detect and install external parallel ports 85 h Initialize PC-compatible PnP ISA devices 86 h Re-initialize onboard I/O ports. 87h Configure Motherboard Configurable Devices

(optional) 88h Initialize BIOS Data Area 89 h Enable Non-Maskable Interrupts (NMIs) 8Ah Initialize Extended BIOS Data Area 8Bh Test and initialize PS/2 mouse 8C h Initialize floppy controller 8Fh Determine number of ATA drives (optional) 90h Initialize hard-disk controllers 91h Initialize local-bus hard-disk controllers 92h Jump to UserPatch2 93 h Build MPTABLE for multi-processor boards 95h Install CD ROM for boot 96 h Clear huge ES segment register 97 h Fix up Multi Processor table 98 h 1-2 Search for option ROMs and shadow if successful.

One long, two short beeps on checksum failure

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X6DH8-XG2/X6DHE-XG2 User's Manual

POST Code Description

99h Check for SMART Drive (optional) 9C h Set up Power Management 9D h Initialize security engine (optional) 9Eh Enable hardware interrupts 9Fh Determine number of ATA and SCSI drives A0h Set time of day A2h Check key lock A4h Initialize typematic rate A8h Erase <ESC> prompt AAh Scan for <ESC> key stroke ACh Enter SETUP AEh Clear Boot flag B0h Check for errors B1h Inform RomPilot about the end of POST (optional) B2h POST done - prepare to boot operating system B4h 1 One short beep before boot B5h Terminate QuietBoot (optional) B6h Check password (optional) B7h Initialize ACPI BIOS and PPM Structure B9h Prepare Boot BA h Initialize SMBIOS BCh Clear parity checkers BDh Display MultiBoot menu BEh Clear screen (optional) BFh Check virus and backup reminders C0h Try to boot with INT 19 C1h Initialize POST Error Manager (PEM) C2 h Initialize error logging C3 h Initialize error display function C4 h Initialize system error handler C6h Console redirection init. C7 h Unhook INT 10h if console redirection enabled C8 h Force check (optional) C9h Extended checksum (optional) CDh Reclaim console redirection vector

Appendix B: BIOS POST Codes

B-5

POST Code Description

D2h Unknown interrupt D4 h Check Intel Branding string D8 h Alert Standard Format initialization D9h Late init for IPMI DEh Log error if micro-code not updated properly

The following are for boot block in Flash ROM

POST Code Description

E0h Initialize the chipset E1h Initialize the bridge E2h Initialize the CPU E3h Initialize system timer E4h Initialize system I/O E5h Check force recovery boot E6h Checksum BIOS ROM E7h Go to BIOS E8h Set Huge Segment E9h Initialize Multi Processor EAh Initialize OEM special code EBh Initialize PIC and DMA ECh Initialize Memory type EDh Initialize Memory size EEh Shadow Boot Block EFh System memory test F0h Initialize interrupt vectors F1h Initialize Run Time Clock F2h Initialize video F3h Initialize System Management Manager F4h Output one beep F5h Clear Huge Segment F6h Boot to Mini DOS F7h Boot to Full DOS

* If the BIOS detects error 2C, 2E, or 30 (base 512K RAM error), it displays an additional word-bitmap (xxxx) indicating the address line or bits that failed. For example, “2C 0002” means address line 1 (bit one set) has failed. “2E 1020" means data bits 12 and 5 (bits 12 and 5 set) have failed in the lower 16 bits. The BIOS also sends the bitmap to the port-80 LED display. It first displays the checkpoint code, followed by a delay, the high-order byte, another delay, and then the loworder byte of the error. It repeats this sequence continuously.

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Notes

Appendix C: Software Installation Instructions

C-1

Appendix C

Installing Software Drivers and Windows

Operating System

After all the hardware has been installed, you must first configure the Adaptec Embedded Serial ATA RAID Driver before you install the Windows operating system. The necessary drivers are all included on the Supermicro bootable CDs that came packaged with your motherboard. (*The following

section provides information on Adaptec's SATA RAID Driver based on the Intel ICH5R Controller.)

C-1 Introduction to the Adaptec Embedded Serial ATA RAID Controller Driver

Serial ATA (SATA)

Serial ATA(SATA) is a physical storage interface. It uses a single cable with a minimum of four wires to create a point-to-point connection between devices. It is a serial link which supports SATA Transfer rates from 150MBps. Because the serial cables used in SATA are thinner than the traditional cables used in Parallel ATA(PATA), SATA systems have better airflow and can be installed in smaller chassis than Parallel ATA. In addition, the cables used in PATA can only extend to 40cm long, while Serial ATA cables can extend up to one meter. Overall, Serial ATA provides better functionality than Parallel ATA.

Introduction to the Intel ICH5R I/O Controller Hub

Located in the South Bridge of the Intel E7520 (Lindenhurst)Chipset, the ICH5R I/O Controller Hub provides the I/O subsystem with access to the rest of the system. It supports 2-channel Ultra ATA/100 Bus Master IDE controller (PATA) and two Serial ATA (SATA) Host Controllers, which support up to two Serial ATA ports and up to two RAID drives. The ICH5R I/O Controller Hub supports the following Parallel ATA (PATA) and Serial (SATA) device configurations:

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X6DH8-XG2/X6DHE-XG2 User's Manual

ATA Operate Mode You can select from the following two modes: Combined Mode and En-

hanced Mode.

Combined Mode:

In this mode, system BIOS assigns the traditional IRQ 14 and IRQ 15 for the use of HDD. Up to 4 ATA devices are supported by this mode.

Within the Combined Mode, the following three modes are supported: *Non-Combined Mode: Parallel ATA only:with the maximum of 4 devices

supported; *Non-Combined Mode: Serial ATA only:with the maximum of 2 devices

supported; *Combined Mode: SATA devices and PATA: with the support of 2 devices

each (total: 4 devices maximum). (For IDE/SATA configurations, please refer to the table below.)

Primary Master(=PM) Yes Yes No No No No Primary Slave(=PS) Yes No Yes No No No Secondary Master(=SM) Yes No No Yes No No Secondary Slave(=SS) Yes No No No Yes No SATA Port0 No SM SM PM PM PM SATA Port1 No SS SS PS PS PS *Note: (No=Not Present, Yes=Present) Also, if Logical Primary is selected, the IDE channels are no longer available.

Enhanced Mode:

In this mode, system BIOS will automatically search for all available IRQs for the use of HDD. For newer Operating Systems that support the Enhanced Mode, such as Windows XP, Windows 2000, and Windows 2003, you can set SATA and PATA to the Enhanced Mode. (*The newer Operating Systems can accommodate both Enhanced Mode and Combined Mode and support up to 6 ATA devices.)

(*Please refer to the "Advanced Chipset Control" under the "Advanced" Setup in the BIOS for the selection of Combined Mode or Enhanced Mode,).

Appendix C: Software Installation Instructions

C-3

Configuring BIOS settings for the SATA RAID Functions (Enhanced Mode)

1. Press the <Del> key during system bootup to enter the BIOS Setup Utility.

(*Note: If it is the first time to power on the system, we recommend that you load the Optimized Default Settings. If you have already done so, please skip to Step 3.

2. Use the arrow keys to select the "Exit" Menu. Once in the "Exit" Menu, scroll down the menu to select the item- "Load Setup Default" and press the <Enter> key. Select "Yes" to confirm the selection. Press the <Enter> key to load the default settings to the BIOS.

3. Use the arrow keys to select the "Main" Menu in the BIOS.

4. Scroll down to "SATA RAID Enable" and press the <Enter> Key to select this option.

5. From this submenu, select "Enable" and press <Enter>.

6. Tap the <Esc> key and scroll down to "Exit". Select "Save and Exit" from the "Exit" menu. Press the <Enter> key to save the changes and exit the BIOS.

7. Once you've exited the BIOS Utility, the system will re-boot.

8. During the system startup, press the <Ctrl> and the <A> keys simultaneously to run the Adaptec RAID Configuration Utility when prompted by the following message:

Press <Ctrl><A> for Adaptec RAID Configuration Utility

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X6DH8-XG2/X6DHE-XG2 User's Manual

The Adaptec Embedded Serial ATA with HostRAID Controller Driver

Adaptec's Embedded Serial ATA RAID with HostRAID controller adds RAID functionality to the Serial ATA I/O controller by supporting RAID 0 (Striping) or RAID 1 (Mirroring) to enhance the industry's pioneer PCI-to-e host controller products. RAID striping (RAID 0) can greatly improve hard disk I/O performance because of its capability in striping data across multiple drives. RAID mirroring (RAID 1) allows the data to be simultaneously written to two drives, so critical data is always available even if a single hard disk fails. Due to the built-in functionality, the X6DH8-XG2/ X6DHE-XG2 is specially designed to keep pace with the increasing performance demands of computer systems by improving disk I/O throughput and providing data accessibility regardless of a single disk failure. By incorporating the Adaptec Embedded Serial ATA into the motherboard design, Supermicro's X6DH8-XG2/X6DHE-XG2 offers the user with the benefits of SATARAID without the high costs associated with hardware RAID applications.

(*Note: For Adaptec's RAID Driver Installation Instructions, please refer to the Adaptec RAID Controller User's Guide: "Emb_SA_RAID_UG.pdf" in the CD that came with this motherboard. You can also download a copy of Adaptec's User's Guide from our web site at www.supermicro.com.)

Using the Adaptec RAID Configuration Utility (ARC)

The Adaptec RAID Configuration Utility is an embedded BIOS Utility, including:

*Array Configuration Utility: Use this utility when you want to create, configure and manage arrays.

* Disk Utilities: Use this option to format or verify disks. To run the Adaptec RAID Configuration Utility, you will need to enable the

RAID function in the system BIOS (refer to Chapter 4 for System BIOS Configurations), and then, press the <Ctrl> and <A> keys simultaneously when prompted to do so during the system startup. (Refer to the previous page for detailed instructions.)

(*Note: To select an option, use the arrow keys to highlight the item and then press the <Enter> key to select it. To return to the previous menu, press the <ESC> key.)

A. Using the Array Configuration Utility (ACU)

The Array Configuration Utility (ACU) enables you to create, manage, and delete arrays from the controller’s BIOS, add and delete spare drives, and initialize drives. During the system startup, press <Ctrl> and <A> key

simultaneously, and the main menu will appear.

Appendix C: Software Installation Instructions

C-5

Managing Arrays

Select this option to view array properties, and delete arrays. The following sections describe the operations Of "Managing Arrays".

To select this option, use the arrow keys and the <enter> key to select "Managing Arrays" from the main menu (as shown above).

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Viewing Array Properties

To view the properties of an existing array:

1. At the BIOS prompt, press Ctrl+A.

2. From the ARC menu, select Array Configuration Utility (ACU).

3. From the ACU menu, select Manage Arrays (as shown on the

previous screen.)

4. From the List of Arrays dialog box, select the array you want to view and press Enter.

The Array Properties dialog box appears, showing detailed information on the array. The physical disks associated with the array are

displayed here.

5. Press Esc to return to the previous menu.

Deleting Arrays

*Warning: Back up the data on an array before you delete it to prevent the loss of data. Deleted arrays cannot be restored.

To delete an existing array:

1. Turn on your computer and press Ctrl+A when prompted to access the ARC utility.

2. From the ARC main menu, select Array Configuration Utility (ACU).

3. From the ACU menu, select Manage Arrays.

4. Select the array you wish to delete and press Delete.

5. In the Array Properties dialog box, select Delete and press Enter. The following prompt is displayed:

*Warning!! Deleting the array will render array unusable. Do you want to delete the array?(Yes/No):

RAID 1 only—the following prompt is also displayed:

Deleting the partition will result in data loss! Do you also want to delete the partition? (Yes/No):

6. Press Yes to delete the array or partition or No to return to the previous menu.

7. Press Esc to return to the previous menu.

Appendix C: Software Installation Instructions

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Creating Arrays

Before creating arrays, make sure the disks for the array are connected and installed in your system. Note that disks with no usable space, or disks that are un-initialized are shown in gray and cannot be used. See Initializing Disk Drives.

To create an array: 1 Turn on your computer and press Ctrl+A when prompted to

access the ARC utility.

2 From the ARC menu, select Array Configuration Utility Main Menu (ACU) (as shown on the first screen on page C-5).

3 From the ACU menu, select Create Array. 4 Select the disks for the new array and press Insert (as the screen

shown below).

(*Note: To deselect any disk, highlight the disk and press Delete.)

5 Press Enter when both disks for the new array are selected. The

Array Properties menu displays (as the screen shown on the next page).

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X6DH8-XG2/X6DHE-XG2 User's Manual

Assigning Array Properties

Once you've create a new array, you are ready to assign the properties to the array.

*Caution: Once the array is created and its properties are assigned, you cannot change the array properties using the ACU. You will need to use the Adaptec Storage Manager - Browser Edition. (Refer to Adaptec's User's Guide in the enclosed CD.)

To assign properties to the new array:

1. In the Array Properties menu (as shown in the following screen), select an array type and press Enter.

Note that only the available array types: RAID 0, and RAID1, are displayed on the screen. (*RAID 0 or RAID 1 requires two drives.)

Appendix C: Software Installation Instructions

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2. Under the item "Arrays Label", type in an label and press Enter. (*Note: The label shall not be more than 15 characters.)

3. For RAID 0, select the desired stripe size. (*Note: Available stripe sizes are 16, 32, and 64 KB-default. It is recommended that you do not change the default setting.)

4. The item: "Create RAID via" allows you to select between the different creating methods for RAID 0 and RAID 1.

The following table gives examples of when each is appropriate.

(*Note: If you select Migrate for RAID 0, or Build for RAID 1, you will be

asked to select the source drive. The contents of the source drive will be preserved. However, the data on the new drive will be lost.)

Raid Level Create Via When Appropriate

RAID 0 No Init Creating a RAID 0 on new drives RAID 0 Migrate

(*Note)

Creating a RAID 0 from one new drive and one drive with data you wish to preserve

RAID 1 Build1 Any time you wish to create a RAID 1, but especially if

you have data on one drive that you wish to preserve

RAID 1 Clear Creating a RAID 1 on new drives, or when you want to

ensure that the array contains no data after creation.

RAID 1 Quick

RAID 1 Init

Fastest way to create a RAID 1. Appropriate when using new drives

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X6DH8-XG2/X6DHE-XG2 User's Manual

Notes:

1. Before adding a new drive to an array, back up any data contained on the new drive. Otherwise, all data will be lost.

2. If you stop the Build or Clear process on a RAID 1 from ACU, you can restart it by pressing Ctrl+R.

3. A RAID 1 created using the Quick Init option may return some data miscompares if you later run a consistency check. This is normal and is not a cause for concern.

4. The ACU allows you to use drives of different sizes in a RAID . However, during a build operation, only the smaller drive can be selected as the source or first drive.

5. When migrating from single volume to RAID 0, migrating from a larger drive to a smaller drive is allowed. However, the destination drive must be at least half the capacity of the source drive.

6. Adaptec does not recommend that you migrate or build an array on Windows dynamic disks (volumes), as it will result in data loss.

Warning: Do not interrupt the creation of a RAID 0 using the Migrate option. If you do, you will not be able to restart, or to recover the data

that was on the source drive.

5. When you are finished, press Done (as the screen shown below).

Appendix C: Software Installation Instructions

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Adding a Bootable Array

To make an array bootable:

1. From the Main menu, select Manage Arrays.

2. From the List of Arrays, select the array you want to make bootable, and press Ctrl+B.

3. Enter Y to create a bootable array when the following message is

displayed: "This will make all other existing bootable array non-bootable. Do you want to make this array bootable? (Yes/No):" Then, a bootable array will be created. An asterisk will appear next to the bootable array (as

shown in the picture below:)

Deleting a Bootable Array

To delete a bootable array:

1. From the Main menu, select Manage Arrays.

2. From the List of Arrays, select the bootable array (*) you want to delete,

and press Ctrl+B. (* a bootable array is the array marked with an asterisk (as shown in the picture above.)

3. Enter Y to delete a bootable array when the following message is displayed: "The array is already marked bootable. Do you want to make this array as not bootable? (Yes/No):" Then, the bootable array will be deleted and the asterisk will disappear.

(*Note: do not use the delete key to delete the bootable array.)

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X6DH8-XG2/X6DHE-XG2 User's Manual

Adding/Deleting Hotspares

(*Note: In order to rebuild a RAID (RAID 0 or RAID 1), you would need to add a new HDD as a hotspare.)

1. Turn on your computer and press Ctrl+A as prompted to access the ARC Utility.

2. From the ARC menu, select Array Configuration Utility (ACU).

3. From the ACU menu, select Add/Delete Hotspares.

4. Use the up and down arrow keys to highlight and select the disk you want to designate as a hotspare, and press <Insert>, and then, press <Enter>.

5. Press yes when the following prompt is displayed: "Do you want to create spare?" (Yes/No?)

The spare you have selected will appear in the Select Drive Menu.

Appendix C: Software Installation Instructions

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Initializing Disk Drives

If an installed disk does not appear in the disk selection list for creating a new array, or if it appears grayed out, you may have to initialize it before you can use it as part of an array. Drives attached to the controller must be initialized before they can be used in an array.

Caution: Initializing a disk overwrites the partition table on the disk and makes any data on the disk inaccessible. If the drive is used in an array, you may not be able to use the array again. Do not initialize a disk that is part of a boot array. To determine which disks are associated with a particular array, please refer to Viewing Array Properties.

To initialize drives:

1. Turn on your computer and press Ctrl+A when prompted to

access the ARC utility.

2. From the ARC menu, select Array Configuration Utility (ACU) (as shown in the screen below).

3. Select Initialize Drives (as shown in the screen below).

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X6DH8-XG2/X6DHE-XG2 User's Manual

4. Use the up and down arrow keys to highlight the disk you wish to initialize and press Insert (as shown in the screen below).

Supermicro Super X6DH8-XG2, X6DHE-XG2 User Manual

Specifications and Main Features

Frequently Asked Questions

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