The information in this User’s Manual has been carefully reviewed and is believed to be accurate.
The vendor assumes no responsibility for any inaccuracies that may be contained in this document,
makes no commitment to update or to keep current the information in this manual, or to notify any
person or organization of the updates. Please Note: For the most up-to-date version of this
manual, please see our web site at www.supermicro.com.
Super Micro Computer, Inc. ("Supermicro") reserves the right to make changes to the product
described in this manual at any time and without notice. This product, including software, if any,
and documentation may not, in whole or in part, be copied, photocopied, reproduced, translated or
reduced to any medium or machine without prior written consent.
IN NO EVENT WILL SUPER MICRO COMPUTER, INC. BE LIABLE FOR DIRECT, INDIRECT,
SPECIAL, INCIDENTAL, SPECULATIVE OR CONSEQUENTIAL DAMAGES ARISING FROM THE
USE OR INABILITY TO USE THIS PRODUCT OR DOCUMENTATION, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGES. IN PARTICULAR, SUPER MICRO COMPUTER, INC.
SHALL NOT HAVE LIABILITY FOR ANY HARDWARE, SOFTWARE, OR DATA STORED OR USED
WITH THE PRODUCT, INCLUDING THE COSTS OF REPAIRING, REPLACING, INTEGRATING,
INSTALLING OR RECOVERING SUCH HARDWARE, SOFTWARE, OR DATA.
Any disputes arising between manufacturer and customer shall be governed by the laws of Santa
Clara County in the State of California, USA. The State of California, County of Santa Clara shall
be the exclusive venue for the resolution of any such disputes. Super Micro's total liability for all
claims will not exceed the price paid for the hardware product.
FCC Statement: This equipment has been tested and found to comply with the limits for a Class B
digital device pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable
protection against harmful interference in a residential installation. This equipment generates,
uses, and can radiate radio frequency energy and, if not installed and used in accordance with the
manufacturer’s instruction manual, may cause interference with radio communications. However,
there is no guarantee that interference will not occur in a particular installation. If this equipment
does cause harmful interference to radio or television reception, which can be determined by turning
the equipment off and on, you are encouraged to try to correct the interference by one or more of
the following measures:
*Reorient or relocate the receiving antenna.
*Increase the separation between the equipment and the receiver.
*Connect the equipment into an outlet on a circuit different from that to which the receiver is
connected.
*Consult the dealer or an experienced radio/television technician for help.
California Best Management Practices Regulations for Perchlorate Materials: This Perchlorate
warning applies only to products containing CR (Manganese Dioxide) Lithium coin cells. “Perchlorate
Material-special handling may apply. See www.dtsc.ca.gov/hazardouswaste/perchlorate”.
WARNING: Handling of lead solder materials used in this
product may expose you to lead, a chemical known to
the State of California to cause birth defects and other
reproductive harm.
Manual Revision 1.1c
Release Date: July 18, 2008
Unless you request and receive written permission from Super Micro Computer, Inc., you may not
copy any part of this document.
Information in this document is subject to change without notice. Other products and companies
referred to herein are trademarks or registered trademarks of their respective companies or mark
holders.
When front panel headphones are plugged in, the back panel audio output is disabled.
This is done through the FP Audio header (J12). If the front panel interface card is
not connected to the front panel audio header, jumpers should be installed on the
header (J12) pin pairs: 1-2, 5-6, and 9-10. If these jumpers are not installed, the
back panel Line-out connector will be disabled and microphone input Pin 1 will be
left fl oating, which can result in excessive back panel microphone noise and cross
talk. See the table below for pin defi nitions.
AC’97 FP Audio Header Signal Names
Pin#SignalDescription
1MICFP microphone input signal
2AUD_GNDGround used by analog audio circuits
3MIC_BIASMicrophone power
4AUD_VCCAnalog audio VCC+5V
5FP_OUT_RRight channel audio signal to front panel
6FP_RETURN_R
7NCNC (*NC=no connection)
8KeyNo pin
9FP_OUT_L Left channel audio signal to front panel
10FP_RETURN_L Left channel audio signal return from front panel
(headphone drive capable)
Right channel audio signal return from front
panel (when headphones unplugged)
(headphone drive capable)
(when headphones unplugged)
Ethernet Port (RJ45
Connector)
One Ethernet port (Gigabit LAN) is
located on the IO backplane of the
motherboard.
Ethernet Port
FP Audio
KB/MS
J28
J31
COM1
VGA
(*PDSLA )
JG1
USB
3/4/5/6
RJ45
USB1/2
Audio
J45
LAN
CTRL
®
GLAN Enable
UPER DSLA/PDSLE
S
J41
4-Pin ATX PWR
Parallel Port
J30
J44
J11
AC97
CD inAux.In
FPAud
J12
JPL1
JPUSB1
Fan3
Clock
Slot#7
Slot#6
Slot#5
Slot#4
PCI#4
Slot#3
PCI#3 -33MHz
Slot#2
PCI#2-33MHz
Slot#1
PCI#1-33MHz
PCI-E x1
PCI-Ex1
-33MHz
LGA 775 Processor
J
FUSB1
J
FUSB
PCI-Ex16
2
J
7
J
8
JP
1
JP
2
BWake
US
P
F/
945G/P
(Lakeport)
North Bridge
P
C
I
P
C
I
P
C
I2
PU
J
-u
P
C
I
Fan1/CPU
DIMM#1A
DIMM#1B
DIMM#2A
J1
COM2
J13
JW
O
R
4
ICH7
3
South Bridge
CL CMOS
2
B
S
p
1
BIOS
F/P USB7/8
I-SATA0
I-SATA2
JBT1
I-SATA3
I-SATA1
4
J43
2
Buzzer
WOL
D
DIMM#2B
Battery
JL1
JLED
J9
O
I/
r
e
p
u
S
4-PinATXPWR
2
J40
Floppy
J2
7
DE
I
J3
J
F1
RL
CT
P
F
L
E
1
JWD
2
n
a
F
2-13
Page 32
PDSLA/PDSLE User's Manual
Pin
Number
1
2
Definition
Intrusion Input
Ground
Chassis Intrusion
Pin Definitions (JL1)
Fan Header Pin Definitions
(CPU, Chassis and Overheat)
Pin#
1
2
3
Definition
Ground (black)
+12V (red)
Tachometer
Caution: These fan headers use DC power.
4PWM_Control
Fan Headers
There are three fan headers (Fan
1, Fan 2 and Fan3) on the PDSLA/
PDSLE. These are 4-pin fan headers;
however, the traditional 3-wire fans
are also supported. (Pins #1-#3 of the
fan headers are backward compatible
with the traditional 3-pin fans.) When
a 3-wire fan is used, it will be set to
run at the full speed by default. When
a 4-wire fan is used, the CPU and
chassis fan speeds will be automati-
cally controlled by the control circuit
inside the fan based upon the CPU
temperature. (See the table on the
right for pin defi nitions.)
Chassis Intrusion
The Chassis Intrusion header is locat-
ed at JL1. See the board layout below
for the location of JL1 and the table on
the right for pin defi nitions.
KB/MS
J28
J41
4-Pin ATX PWR
J31
COM1
Parallel Port
VGA
J30
(*PDSLA )
JG1
USB
3/4/5/6
RJ45
USB1/2
Audio
®
GLAN Enable
UPER DSLA/PDSLE
S
LAN
CTRL
JPUSB1
J44
Fan3
J11
J45
AC97
FP Aud
Clock
Slot#7
Slot#6
Slot#5
Slot#4
PCI#4 -33MHz
Slot#3
PCI#3 -33MHz
CD inAux.In
Slot#2
PCI#2-33MHz
JPL1
Slot#1
J12
PCI#1-33MHz
PCI-E x1
PCI-E x1
LGA 775 Processor
JF
US
B
1
JF
US
B
PCI-E x16
2
F
J
J8
/
7
J
P
J
P2
USB Wa
P
945G/P
(Lakeport)
North Bridge
1
ke-up
P
PC I3
P
PC
C
C
JPUS
Fan 1(CPU Fan)Fan 3
DIMM#1B
Buzzer
DIMM#2B
Battery
JL1
JLED
JWD
J9
O
Su per I/
ATX PW R
n
Pi
4
2
J40
Floppy
J
2
7
E
D
I
J3
JF 1
Chassis Intrusion
FP CTRL
L
E1
2
Fan 2
Fan
Fan1/CPU
DIMM#1A
DIMM#2A
J
1
COM2
J13
J
W
OR
I
4
ICH7
South Bridge
I
2
CL CMOS
2
B
BIOS
I
1
F/P USB7/8
I-SATA0
I-SATA2
JBT1
I-SATA3
I-SATA1
J43
24
WOL
D
2-14
Page 33
Pin# Definition
1 +5V
2 P0-
3 P0+
4 Ground
Pin
Number
2
4
6
8
10
Definition
+5V
PO-
PO+
Ground
Ground
Pin
Number
1
3
5
7
Definition
+5V
PO-
PO+
Ground
USB Pin Definition
J43
J44 & J11
ATX PS/2 Keyboard and
PS/2 Keyboard
and Mouse Port
Pin Definitions
(J28)
Pin
Number
1
2
3
4
5
6
Definition
Data
NC
Ground
VCC
Clock
NC
PS/2 Mouse Ports
The ATX PS/2 keyboard and the PS/2
mouse are located at J28. See the
table on the right for pin defi nitions.
(The mouse port is above the key-
board port.)
Universal Serial Bus (USB)
There are six Universal Serial Bus
ports located at (J44, J11) on the I/O
Backpanel and additional two USB
ports are located at (J43) on the
motherboard. The additional ports,
labeled USB7 to USB8, can be used
to provide front side access (Cables
are not included). See the tables on
the right for pin defi nitions.
Chapter 2: Installation
KB/Mouse
USB 3/4/5/6
USB 1/2
KB/MS
J28
J41
4-Pin ATX PWR
J31
COM1
Parallel Port
VGA
J30
(*PDSLA )
JG1
USB
3/4/5/6
RJ45
USB1/2
Audio
LAN
CTRL
®
GLAN Enable
UPER DSLA/PDSLE
S
J44
J11
J45
AC97
CD inAux.In
JPL1
FP Aud
J12
JPUSB1
Fan3
Clock
Slot#7
Slot#6
Slot#5
Slot#4
PCI#4 -33MHz
Slot#3
PCI#3 -33MHz
Slot#2
PCI#2-33MHz
Slot#1
PCI#1-33MHz
PCI-E x1
PCI-E x1
LGA 775 Processor
JF
U
S
B1
JFUSB2
PCI-E x16
J
7
J
8
J
P
JP
USB
F/P
945G/P
(Lakeport)
North Bridge
1
2
W
DIMM#1B
Buzzer
DIMM#2B
Battery
JL1
JLED
JWD
J9
O
Su per I/
TX PW R
A
n
i
P
24-
J40
Floppy
J
2
7
IDE
J3
J
F
1
FP CTRL
L
E1
an 2
F
FP USB 7/8
Fan1/CPU
DIMM#1A
DIMM#2A
J
1
COM2
J13
J
W
O
R
PC
I
4
PC
I
3
PC I
2
JPUS
p
u
ake-
PC I
1
B
2
BIOS
F/P USB7/8
ICH7
South Bridge
CL CMOS
JBT1
J43
I-SATA0
I-SATA1
I-SATA2
I-SATA3
WOL
D24
2-15
Page 34
PDSLA/PDSLE User's Manual
Pin
Number
1
2
3
Definition
+5V Standby
Ground
Wake-up
Wake-On-LAN Pin
Definitions (WOL)
Pin
Number
1
2
Definition
Ground
Wake-up
Wake-On-Ring Pin Definitions
Wake-On-Ring
The Wake-On-Ring header is located
at JWOR. This function allows your
computer to wake up when it receives
an incoming call to the modem while
in the suspend state. You must also
have a WOR card and cable to use
WOR.See the table on the right for
pin defi nitions.
Wake-On-LAN
The Wake-On-LAN header is desig-
nated WOL on the motherboard. You
must enable the LAN Wake-Up setting
in the BIOS and also have a LAN card
with a Wake-On-LAN connector and a
cable to use this feature. See the table
on the right for pin defi nitions.
KB/MS
J28
J41
4-Pin ATX PWR
J31
COM1
Parallel Port
VGA
J30
(*PDSLA )
JG1
USB
3/4/5/6
RJ45
USB1/2
Audio
®
GLAN Enable
UPER DSLA/PDSLE
S
J45
LAN
CTRL
JPUSB1
J44
Fan3
J11
Slot#7
Slot#6
Slot#5
Slot#4
PCI#4
Slot#3
AC97
PCI#3 -33MHz
CD inAux.In
Slot#2
PCI#2-33MHz
JPL1
Slot#1
FP Aud
J12
PCI#1-33MHz
Clock
PCI-E x1
PCI-E x1
-33MHz
LGA 775 Processor
J
F
U
S
B
1
JFUS
B
2
PCI-E x16
F
945G/P
(Lakeport)
North Bridge
J
7
J8
J
P
1
J
P
2
ke-up
a
SB W
PU
/
P
PC I3
P
P
DIMM#1B
Buzzer
DIMM#2B
Battery
JL1
JLED
JWD
J9
O
uperI/
S
PW R
ATX
Pin
24
J40
Floppy
J2
7
WOR
E
ID
J3
JF
1
L
R
FP CT
L
E
1
2
n
a
F
WOL
Fan1/CPU
DIMM#1A
DIMM#2A
J1
COM2
J13
J
WO
R
C
I
4
ICH7
South Bridge
C
I
2
CL CMOS
B2
S
U
JP
BIOS
C
I1
F/P USB7/8
I-SATA0
I-SATA2
JBT1
I-SATA3
I-SATA1
4
J43
2
WOL
D
2-16
Page 35
VGA Connector (For PDSLA
only)
A VGA connector (JG1) is located next
to the COM1 on the IO backplane.
Refer to the board layout below for
the location.
AC'97 Audio
AC'97 provides high quality onboard
audio connection on the I/O Backplane.
This motherboard features a 6-channel
sound for front L&R, rear L&R, center and
subwoofer speakers. You can activate this
function through an advanced software
program stored in the CD-ROM that came
with your motherboard shipment. Sound is
then output through the Line-in, Line-out
and MIC jacks on the backplane.
Chapter 2: Installation
Blue:
Line In(surround L/R)
Green:
Pink:
Line Out(Front L/R)
MIC In (Center/subwoofer)
VGA
Audio
KB/MS
J28
J31
COM1
VGA
J30
(*PDSLA )
JG1
USB
J44
3/4/5/6
RJ45
USB1/2
J11
Audio
J45
LAN
CTRL
®
GLAN Enable
UPER DSLA/PDSLE
S
J41
4-Pin ATX PWR
Parallel Port
AC97
CD inAux.In
JPL1
FP Aud
J12
JPUSB1
Fan3
Clock
Slot#7
Slot#6
Slot#5
Slot#4
PCI#4
Slot#3
PCI#3 -33MHz
Slot#2
PCI#2-33MHz
Slot#1
PCI#1-33MHz
PCI-E x1
PCI-E x1
-33MHz
LGA 775 Processor
JF
U
SB1
JF
U
SB2
PCI-E x16
J
7
J
8
J
P
J
P
PUSB W
F/
945G/P
(Lakeport)
North Bridge
1
2
DIMM#2B
DIMM#1B
Battery
JLED
J9
O
per I/
Su
R
W
in ATX P
-P
4
2
J40
Floppy
J
2
7
DE
I
J3
J
F
1
JL1
TRL
C
FP
LE
1
JWD
Fan 2
Fan1/CPU
DIMM#1A
DIMM#2A
J
1
COM2
J13
J
WO
R
PC I4
PC
I3
PC
I2
USB
P
J
p
ke-u
a
PC I1
2
BIOS
F/P USB7/8
ICH7
South Bridge
CL CMOS
JBT1
J43
I-SATA0
I-SATA1
I-SATA2
I-SATA3
24
Buzzer
WOL
D
2-17
Page 36
PDSLA/PDSLE User's Manual
2-7 Jumper Settings
Explanation of
Jumpers
To modify the operation of the mother-
board, jumpers can be used to choose
between optional settings. Jumpers
create shorts between two pins to
change the function of the connector.
Pin 1 is identifi ed with a square solder
pad on the printed circuit board. See
the motherboard layout pages for
jumper locations.
Note: On a two-pin jumper, "Closed"
Pins 1-2 short
means the jumper is on both pins and
"Open" means the jumper is either on
only one pin or completely removed.
CMOS Clear
JBT1 is not actually a jumper but consists of two contact pads. To clear the contents
of CMOS, short these pads together by touching them both with a metal conductor
such as the head of a small screwdriver. JBT1 is located near the SATA header on
the PDSLA/PDSLE. Note: for ATX power supplies, you must completely shut down
the system and remove the AC power cord before clearing CMOS.
KB/MS
J28
J31
COM1
VGA
J30
(*PDSLA )
JG1
USB
J44
3/4/5/6
RJ45
USB1/2
J11
Audio
J45
LAN
CTRL
®
GLAN Enable
UPER DSLA/PDSLE
S
J41
4-Pin ATX PWR
Parallel Port
AC97
CD inAux.In
JPL1
FP Aud
J12
JPUSB1
Fan3
Clock
Slot#7
PCI-E x1
Slot#6
Slot#5
Slot#4
PCI#4 -33MHz
Slot#3
PCI#3 -33MHz
Slot#2
PCI#2-33MHz
Slot#1
PCI#1-33MHz
PCI-Ex16
PCI-E x1
LGA 775 Processor
JF
US
B
1
JFU
S
B
2
J
7
J8
J
JP 2
F/P
P
1
SB
U
945G/P
(Lakeport)
North Bridge
PC
I4
PC
I3
PC
I2
JPUSB 2
up
e-
k
a
W
P
C
I
Fan1/CPU
DIMM#1A
DIMM#2A
J
1
COM2
J13
J
W
O
R
ICH7
South Bridge
CL CMOS
I-SATA0
I-SATA2
JBT1
BIOS
1
F/P USB7/8
I-SATA3
I-SATA1
4
J43
2
WOL
D
DIMM#1B
Buzzer
DIMM#2B
Battery
JL1
JLED
JWD
J9
O
I/
r
upe
S
R
PW
ATX
-Pin
4
2
J40
Floppy
J2
7
E
D
I
J3
JF 1
CTRL
FP
L
E
1
2
n
Fa
Clear CMOS
2-18
Page 37
USB Wake-Up
Jumper
Position
1-2
2-3
Definition
Enabled
*Disabled
USB Wake-Up
Jumper Settings
(JPUSB1/JPUSB2)
(*Default)
Use JPUSB jumpers to enable the function
of "System Wake-Up via USB devices",
which allows you to "wake-up" the system by
pressing a key on the USB keyboard or by
clicking the USB mouse of your system. The
JPUSB jumpers are used together with the
USB Wake-Up function in the BIOS. Enable
both the jumpers and the BIOS setting to al-
low the system to wake-up via USB devices.
See the table on the right for jumper settings
and jumper connections. (Note: JPUSB1 is
for Back Panel USB ports:1/2/3/4/5/6, and
JPUSB2 is for Front Panel USB ports:7/8.)
(Note: The default jumper setting for the USB
ports is "Disabled". However, when the "USB
Wake-Up" function is enabled in the BIOS
and the desired USB ports are enabled via
the JPUSB jumper, please be sure to remove
all USB devices from the USB ports whose
USB jumpers are set to Disabled before the
system goes into the standby mode.)
Chapter 2: Installation
JPUSB1
KB/MS
J28
J41
4-Pin ATX PWR
J31
COM1
VGA
J30
(*PDSLA )
JG1
USB
3/4/5/6
RJ45
USB1/2
J11
Audio
J45
LAN
CTRL
®
GLAN Enable
UPER DSLA/PDSLE
S
J44
Parallel Port
AC97
FP Aud
JPUSB1
Fan3
Slot#4
PCI#4
Slot#3
PCI#3 -33MHz
CD inAux.In
Slot#2
PCI#2-33MHz
JPL1
Slot#1
J12
PCI#1-33MHz
Clock
Slot#7
Slot#6
Slot#5
PCI-E x1
-33MHz
PCI-E x1
LGA 775 Processor
J
FUSB1
J
F
U
SB2
PCI-E x16
945G/P
(Lakeport)
North Bridge
J
7
J
8
JP
1
JP 2
F/P USBWak
DIMM#1B
Buzzer
DIMM#2B
Battery
JL1
JLED
JWD
J9
O
I/
r
e
p
u
S
J40
J
2
J3
JF
L
E
1
n2
Fa
PW R
X
T
nA
4-Pi
2
Floppy
7
DE
I
1
CTRL
P
F
JPUSB2
Fan1/CPU
DIMM#1A
DIMM#2A
J1
COM2
J13
J
WO
R
P
C
I4
ICH7
P
C
I3
South Bridge
P
CI
2
CL CMOS
SB 2
PU
J
p
u
-
e
P
CI1
BIOS
F/P USB7/8
I-SATA0
I-SATA2
JBT1
I-SATA3
I-SATA1
J43
WOL
D24
2-19
Page 38
PDSLA/PDSLE User's Manual
Jumper
Position
Pins 1-2
Pins 2-3
Definition
Enabled
Disabled
GLAN
Enable/Disable
Jumper Settings
Jumper
Position
Pins 1-2
Pins 2-3
Open
Definition
WD to Reset
WD to NMI
Disabled
Watch Dog
Jumper Settings
Watch Dog Enable/Disable
JP5 enables Watch Dog Timer. Watch
Dog is a system monitor that can
reboot the system when a software
application hangs. Close pins 1-2
to reset the system if an application
hangs. Close pins 2-3 to generate a
non-maskable interrupt signal for the
application that hangs. See the table
on the right for jumper settings.
Gigabit LAN Enable
A header for GLAN Enable is located
at JPL1. Close Pins 1 & 2 of JPL1 to
enable the function of LAN. See the
table on the right for pin defi nitions.
GLAN Enable
KB/MS
J28
J41
4-Pin ATX PWR
J31
LGA 775 Processor
COM1
Parallel Port
VGA
J30
(*PDSLA )
JG1
USB
3/4/5/6
RJ45
USB1/2
Audio
J45
LAN
CTRL
®
GLAN Enable
UPER DSLA/PDSLE
S
J11
J44
AC97
FP Aud
JPUSB1
Fan3
CD inAux.In
JPL1
J12
Clock
Slot#7
PCI-E x1
Slot#6
Slot#5
PCI-E x1
Slot#4
-33MHz
PCI#4
Slot#3
PCI#3 -33MHz
Slot#2
PCI#2-33MHz
Slot#1
PCI#1-33MHz
JF
U
JF
PCI-E x16
SB1
U
SB
2
J
7
J
8
J
P
J
P2
PUSB W
F/
945G/P
(Lakeport)
North Bridge
1
PC
PC
PC I2
ake-up
PC
Fan1/CPU
DIMM#1A
DIMM#2A
J
1
COM2
J13
J
WO R
I4
I3
JPU
I1
ICH7
South Bridge
CL CMOS
2
SB
BIOS
F/P USB7/8
JBT1
J43
I-SATA0
I-SATA1
I-SATA2
I-SATA3
24
Buzzer
WOL
D
DIMM#2B
DIMM#1B
Battery
JL1
JLED
J9
JWD
I/O
r
e
p
Su
R
W
in ATX P
-P
24
J40
Floppy
J
2
7
E
D
I
J3
J
F
1
TRL
C
FP
L
E
1
WD
Fan 2
2-20
Page 39
SMBus to PCI/PCI-Exp. Slots
Jumper
Position
closed
*Open
Definition
Enabled
Disabled
SMBus to PCI/PCI-Exp
(*Default)
Close: Pins 3 &4
connect w/a
4-pin header
Internal
Buzzer
Speaker Connector
External
Speaker
Chapter 2: Installation
Jumpers JP1, JP2 allow you to connect
PCI/PCI-E slots to the System Management Bus. The default setting is Open
to disable the connection. See the table
on the right for jumper settings.
Speaker Connector
The speaker connector is located at
J9. Close pins 3 & 4 to use as a inter-
nal buzzer. Use a 4-pin cable to con-
nect to an external speaker. See the
table on the right for pin defi nitions.
Jumper Setting
Jumper Setting
KB/MS
J28
J41
4-Pin ATX PWR
J31
LGA 775 Processor
COM1
Parallel Port
VGA
J30
(*PDSLA )
JG1
USB
J44
3/4/5/6
RJ45
USB1/2
J11
Audio
J45
LAN
CTRL
®
GLAN Enable
UPER DSLA/PDSLE
S
AC97
FP Aud
J12
JPUSB1
Fan3
Slot#4
CD inAux.In
JPL1
Clock
Slot#7
PCI-E x1
Slot#6
Slot#5
PCI-E x1
PCI#4 -33MHz
Slot#3
PCI#3 -33MHz
Slot#2
PCI#2-33MHz
Slot#1
PCI#1-33MHz
JF
U
JF
U
PCI-E x16
S
B1
S
B2
SMB to PCI /PCIE slots
J
/P
F
J
7
8
JP
JP
1
2
USB W a
945G/P
(Lakeport)
North Bridge
PC
I
4
PC
I
3
P
C
I
2
JPUS
up
-
ke
PC
I1
J1
B
COM2
2
Fan1/CPU
J13
J
WO
BIOS
F/P USB7/8
R
ICH7
South Bridge
CL CMOS
JBT1
J43
DIMM#1A
I-SATA0
I-SATA1
2-21
DIMM#2A
I-SATA2
I-SATA3
24
WOL
D
DIMM#1B
Buzzer
DIMM#2B
Battery
JL1
JLED
JWD
J9
LE
n2
Fa
I/O
r
e
Su p
R
ATX PW
-Pin
4
2
J40
Floppy
J2
7
E
D
I
J3
JF 1
L
TR
FP C
1
Speaker
Page 40
PDSLA/PDSLE User's Manual
1-2
Front Side Bus Speeds:
JFSB1, JFSB2
1-2*Auto
2-3
266 MHz
Open
200 MHz
166 MHz
JFSB1
2-3
2-3
2-3
133 MHz
JFSB2
Frequency
Open
Open
Open
CPU Front Side Bus Speed
JFSB1 and JFSB2 allow you to set the
Front Side Bus Frequency. See the table
on the right for pin defi nitions. (The default
setting is Auto.)
KB/MS
CPU FSB Speed
J28
J41
4-Pin ATX PWR
J31
COM1
Parallel Port
VGA
J30
(*PDSLA )
JG1
USB
3/4/5/6
RJ45
USB1/2
Audio
®
GLAN Enable
UPER DSLA/PDSLE
S
J45
LAN
CTRL
JPUSB1
J44
Fan3
J11
Slot#7
Slot#6
Slot#5
Slot#4
PCI#4 -33MHz
Slot#3
AC97
PCI#3 -33MHz
CD inAux.In
Slot#2
PCI#2-33MHz
JPL1
Slot#1
FP Aud
J12
PCI#1-33MHz
Clock
PCI-E x1
PCI-E x1
LGA 775 Processor
J
FU
S
B1
J
FU
SB
2
PCI-E x16
945G/P
(Lakeport)
North Bridge
J
7
J
8
JP
1
JP 2
P
C
I
P
C
I
P
C
I
P
J
-up
e
k
a
W
B
/P US
F
P
C
I1
DIMM#1B
Buzzer
DIMM#2B
Battery
JL1
JLED
JWD
J9
O
I/
r
upe
S
R
W
ATXP
in
-P
4
2
J40
Floppy
J
2
7
IDE
J3
JF
1
CTRL
FP
L
E
1
an 2
F
Fan1/CPU
DIMM#1A
DIMM#2A
J1
COM2
J13
J
W
O
R
4
ICH7
3
South Bridge
2
CL CMOS
B2
S
U
BIOS
F/P USB7/8
I-SATA0
I-SATA2
JBT1
I-SATA3
I-SATA1
J43
24
WOL
D
2-22
Page 41
Chapter 2: Installation
Pin
Number
1
2
3
Definition
Anode
Key
Cathode
JLED
Pin Definitions
LED
Color
Off
Green
Amber
Definition
10 MHz
100 MHz
1 GHz
1 Gb LAN Left LED
Indicator (Speed LED)
LED
Color
Amber
Definition
Blinking
10/100MHz/
1GHz
1 Gb LAN Right LED
Indicator(Activ ity LED)
2-8 Onboard Indicators
GLAN LEDs
The Gigabit Ethernet LAN port (located
beside the Video port) has two LEDs. The
yellow LED indicates activity, while the other
LED may be green, amber or off to indicate
the speed of the connection. See the table
at right for the functions associated with the
second LED.
Power LED
The Power LED header is located at
JLED.This header provides LED indi-
cation of power being supplied to the
system. See the table on the right for
pin defi nitions.
GLAN LED
ActivityLink
Rear View
GLAN LED
KB/MS
J28
J41
4-Pin ATX PWR
J31
COM1
Parallel Port
VGA
J30
(*PDSLA )
JG1
USB
3/4/5/6
RJ45
USB1/2
Audio
®
GLAN Enable
UPER DSLA/PDSLE
S
J45
LAN
CTRL
JPUSB1
J44
Fan3
J11
AC97
FP Aud
Clock
Slot#7
Slot#6
Slot#5
Slot#4
PCI#4 -33MHz
Slot#3
PCI#3 -33MHz
CD inAux.In
Slot#2
PCI#2-33MHz
JPL1
Slot#1
J12
PCI#1-33MHz
PCI-E x1
PCI-E x16
PCI-E x1
LGA 775 Processor
JFUS
B
1
J
F
US
B
2
J
7
J8
J
P1
J
P2
PUSB Wa
/
F
945G/P
(Lakeport)
North Bridge
ke-up
P
PC I
P
PC I1
DIMM#1B
Buzzer
DIMM#2B
Battery
JL1
JLED
JWD
J9
O
rI/
e
up
S
ATX PW R
4-Pin
2
J40
Floppy
J2
7
E
D
I
J3
JF
1
FP CTRL
L
E
1
Fan 2
PWR LED
Fan1/CPU
DIMM#1A
DIMM#2A
J1
COM2
J13
J
WO
R
C
I
4
ICH7
3
South Bridge
C
I
2
CL CMOS
2
B
S
U
P
J
BIOS
F/P USB7/8
I-SATA0
I-SATA2
JBT1
I-SATA3
I-SATA1
4
J43
2
WOL
D
2-23
Page 42
PDSLA/PDSLE User's Manual
Pin Number Function
1Strobe 3Data Bit 0
5Data Bit 1
7Data Bit 2
9Data Bit 3
11Data Bit 4
13Data Bit 5
15Data Bit 6
17Data Bit 7
19ACK
21BUSY
23PE
25SLCT
Pin Number Function
2Auto Feed 4Error 6Init 8SLCT IN 10GND
12GND
14GND
16GND
18GND
20GND
22GND
24GND
26NC
Parallel (Printer) Port Pin Definitions
(J30)
2-9 Parallel Port, Floppy Drive, and HDD Connections
Use the following information to connect the fl oppy and hard disk drive cables.
• The fl oppy disk drive cable has seven twisted wires.
• A red mark on a wire typically designates the location of pin 1.
• A single fl oppy disk drive ribbon cable has 34 wires and two connectors to provide
for two fl oppy disk drives. The connector with twisted wires always connects to
drive A, and the connector that does not have twisted wires always connects to
drive B.
• The 80-wire ATA100/66 IDE hard disk drive cable that came with your system
has two connectors to support two drives. This special cable should be used
to take advantage of the speed this new technology offers. The blue connector
connects to the onboard IDE connector interface and the other connector(s) to
your hard drive(s). Consult the documentation that came with your disk drive for
details on actual jumper locations and settings for the hard disk drive.
Parallel Port Connector
The parallel port is located at J30. Re-
fer to Figure 2-3 for location. See the
table on the right for pin defi nitions.
Parallel Port
KB/MS
J28
J41
4-Pin ATX PWR
J31
COM1
Parallel Port
VGA
J30
(*PDSLA )
JG1
USB
3/4/5/6
Audio
RJ45
USB1/2
JPUSB1
J44
Fan3
J11
J45
LAN
CTRL
AC97
CD inAux.In
®
GLAN Enable
JPL1
UPER DSLA/PDSLE
FPAud
S
J12
Clock
Slot#7
PCI-E x1
Slot#6
Slot#5
PCI-Ex1
Slot#4
PCI#4 -33MHz
Slot#3
PCI#3 -33MHz
Slot#2
PCI#2-33MHz
Slot#1
PCI#1-33MHz
JF
J
PCI-Ex16
U
S
F
U
S
LGA 775 Processor
B
1
B
2
J
7
J
8
J
P
1
J
P
2
USB Wa
P
/
F
945G/P
(Lakeport)
North Bridge
PC
I
P
C
I
P
C
I
JP
up
e-
k
PC
I1
Fan1/CPU
J
1
COM2
J13
J
W
4
3
2
2
B
S
U
BIOS
F/P USB7/8
O
R
ICH7
South Bridge
CL CMOS
JBT1
O
/
I
r
e
p
Su
R
XPW
T
nA
i
-P
24
I-SATA2
I-SATA3
DIMM#1B
Buzzer
DIMM#2B
Battery
JL1
JLED
J9
J40
Floppy
J
27
E
D
I
J3
J
F1
L
R
PCT
F
LE 1
JWD
n2
Fa
DIMM#1A
DIMM#2A
I-SATA0
I-SATA1
J43
WOL
D24
2-24
Page 43
Pin NumberFunction
1Reset IDE
3Host Data 7
5Host Data 6
7Host Data 5
9Host Data 4
11Host Data 3
13Host Data 2
15Host Data 1
17Host Data 0
19GND
21DRQ3
23I/O Write 25I/O Read 27IOCHRDY
29DACK3 31IRQ14
33Addr 1
35Addr 0
37Chip Select 0
39Activity
Pin NumberFunction
2GND
4Host Data 8
6Host Data 9
8Host Data 10
10Host Data 11
12Host Data 12
14Host Data 13
16Host Data 14
18Host Data 15
20Key
22GND
24GND
26GND
28BALE
30GND
32IOCS16 34GND
36Addr 2
38Chip Select 1 40GND
IDE Connector Pin Definitions
(J3)
Floppy Connector
The fl oppy connector is located
at J27. Refer to Figure 2-3 for
location. See the table on the
right for pin defi nitions.
Chapter 2: Installation
IDE Connector
There are no jumpers to con-
fi gure the onboard IDE inter-
faces Pins 3, 5 of JF1. See the
table on the left for pin defi ni-
tions. Note: You must use the
ATA100/66 cable included with
your system to benefi t from the
ATA100/66 technology.
KB/MS
J28
J41
4-Pin ATX PWR
J31
COM1
Parallel Port
VGA
J30
(*PDSLA )
JG1
USB
J44
3/4/5/6
Fan3
RJ45
USB1/2
J11
Audio
J45
LAN
CTRL
AC97
CD inAux.In
®
GLAN Enable
JPL1
UPER DSLA/PDSLE
FPAud
S
J12
JPUSB1
Clock
Slot#7
Slot#6
Slot#5
Slot#4
PCI#4 -33MHz
Slot#3
PCI#3 -33MHz
Slot#2
PCI#2-33MHz
Slot#1
PCI#1-33MHz
PCI-E x1
PCI-Ex1
LGA 775 Processor
JF
U
SB1
JFU
SB2
PCI-Ex16
945G/P
(Lakeport)
North Bridge
J
7
J1
COM2
J8
JP
1
J
P
2
P
CI4
PC I
3
PC I2
2
B
S
PU
J
p
-u
ke
BWa
S
U
P
/
F
PC I1
J13
BIOS
Fan1/CPU
J
WO
F/P USB7/8
R
ICH7
South Bridge
CL CMOS
JBT1
J43
I-SATA0
I-SATA1
DIMM#1A
4
2
WOL
D
DIMM#2A
I-SATA2
I-SATA3
Buzzer
DIMM#2B
DIMM#1B
Battery
JLED
/O
I
r
e
p
Su
PW R
TX
A
Pin
4
2
J40
Floppy
Floppy
J27
IDE
DE
I
J3
J
F1
L
R
JL1
T
PC
F
L
E
1
JWD
J9
2
an
F
2-25
Page 44
PDSLA/PDSLE User's Manual
2-10 Installing the Operating System and Software
Programs
After all the hardware has been installed, you must fi rst install the operating system,
and then, other software drivers. The necessary drivers are all included on the
Supermicro CDs that came packaged with your motherboard.
Drivers/Tool Installation Display Screen
Note: Click on the icons showing a hand writing on the paper to view the readme
fi les for each item. Click the computer icons to the right of these items to install each
item (from top to the bottom) one at a time. After installing each item, you must
re-boot the system before moving on to the next item on the list. The bottom
icon with a CD on it allows you to view the entire contents of the CD.
2-26
Page 45
Chapter 2: Installation
Introduction to Serial ATA (SATA)
Serial ATA(SATA) is a physical storage interface. It uses a single cable with a mini-
mum of four wires to create a point-to-point connection between devices. It is a serial
link which supports SATA Transfer rates from 150MBps. The second generation
SATA can support up to 300 MBps theoretically. Because the serial cables used
in SATA are thinner than the traditional cables used in Parallel ATA(PATA), SATA
systems have better airfl ow and can be installed in smaller chassis than Parallel
ATA. In addition, the cables used in PATA can only extend to 40cm long, while
Serial ATA cables can extend up to one meter. Overall, Serial ATA provides better
functionality than Parallel ATA.
Introduction to the Intel ICH7 I/O Controller Hub
Located in the South Bridge of the Intel Lakeport (945G/P) chipset, the ICH7 I/O
Controller Hub provides the I/O subsystem with access to the rest of the system.
It supports 1-channel Ultra ATA/100 Bus Master IDE controller (PATA) and four
Serial ATA (SATA) Second Generation Host Controllers, which support up to four
Serial ATA ports and four hard drives. The ICH7 I/O Controller Hub supports the
following Parallel ATA (PATA) and Serial (SATA) device confi gurations:
SATA Operation Modes
You can select from the following SATA modes: Auto, Combined, Enhanced, and
SATA Only Mode. The number of devices supported by these modes are listed
below:
SATA Only: The maximum of 4 devices are supported (4 SATA)
•
Auto Mode: The maximum of 6 devices supported (4 SATA + 2 IDE)
•
Enhanced Mode: The maximum of 6 devices supported (4 SATA + 2 IDE)
•
Combined Mode: The maximum of 4 devices supported (2 SATA + 2 IDE)
•
2-27
Page 46
PDSLA/PDSLE User's Manual
Supero Doctor III
The Supero Doctor III program is a Web-based management tool that supports
remote system management. It includes Remote and Local Management tools. The
local management is called SD III Client. The Supero Doctor III program included on
the CDROM that came with your motherboard allows you to monitor the environment
and operations of your system. Supero Doctor III displays crucial system information
such as CPU temperature, system voltages and fan status. See the graphics below
for the displays of the Supero Doctor III interface.
Note 1: The default user name and password are ADMIN.
Note 2: In the Windows OS environment, the Supero Doctor III settings take pre-
cedence over the BIOS settings. When fi rst installed, Supero Doctor III adopts the
temperature threshold settings previously set in the BIOS. Any subsequent changes
to these thresholds must be made within Supero Doctor, since the SD III settings
override the BIOS settings. For the Windows OS to adopt the BIOS temperature
threshold settings, please change the SDIII settings to be the same as those set
in the BIOS.
Supero Doctor III Interface Display Screen-I (Health Information)
2-28
Page 47
Chapter 2: Installation
Supero Doctor III Interface Display Screen-II (Remote Control)
Note: SD III Software Revision 1.0 can be downloaded from our Website at: ftp://
ftp.supermicro.com/utility/Supero_Doctor_III/. You can also download SDIII User's
Guide at: http://www.supermicro.com/PRODUCT/Manuals/SDIII/UserGuide.pdf. For
Linux, we will still recommend Supero Doctor II.
2-29
Page 48
PDSLA/PDSLE User's Manual
Notes
2-30
Page 49
Chapter 3: Troubleshooting
Chapter 3
Troubleshooting
3-1 Troubleshooting Procedures
Use the following procedures to troubleshoot your system. If you have followed all
of the procedures below and still need assistance, refer to the ‘Technical Support
Procedures’ and/or ‘Returning Merchandise for Service’ section(s) in this chapter.
Always disconnect the AC power cord before adding, changing or installing any
hardware components.
Before Power On
1. Check if the Standby Power LED is not lit (LE1 on motherboard).
2. Make sure that there are no short circuits between the motherboard and chas-
sis.
3. Disconnect all ribbon/wire cables from the motherboard, including those for the
keyboard and mouse.
4. Remove all add-on cards.
5. Install a CPU and heatsink (-making sure it is fully seated) and connect the
chassis speaker and the power LED to the motherboard. Check all jumper
settings as well.
6. Make sure the 4-pin 12v power connector at J41 is connected to your power
supply.
No Power
1. Make sure that there are no short circuits between the motherboard and the
chassis.
2. Make sure that all jumpers are set to their default positions.
3. Make sure that the 115V/230V switch on the power supply is properly set.
4. Turn the power switch on and off to test the system.
5. The battery on your motherboard may be old. Check to verify that it still supplies
~3VDC. If it does not, replace it with a new one.
No Video
1. If the power is on but you have no video, remove all the add-on cards and
cables.
2. Use the speaker to determine if any beep codes exist. Refer to Appendix A for
details on beep codes.
3-1
Page 50
PDSLA/PDSLEUser's Manual
NOTE
If you are a system integrator, VAR or OEM, a POST diagnostics
card is recommended. For I/O port 80h codes, refer to App. B.
Memory Errors
1. Make sure that the DIMM modules are properly and fully installed.
2. You should be using unbuffered DDRII memory. Also, it is recommended that
you use the same memory speed for all DIMMs in the system. See Section
2-4 for memory limitations.
3. Check for bad DIMM modules or slots by swapping modules between slots and
noting the results.
4. Check the power supply voltage 115V/230V switch.
Losing the System’s Setup Confi guration
1. Make sure that you are using a high quality power supply. A poor quality power
supply may cause the system to lose the CMOS setup information. Refer to
Section 1-6 for details on recommended power supplies.
2. The battery on your motherboard may be old. Check to verify that it still supplies
~3VDC. If it does not, replace it with a new one.
3. If the above steps do not fi x the Setup Confi guration problem, contact your
vendor for repairs.
3-2 Technical Support Procedures
Before contacting Technical Support, please take the following steps. Also, note that
as a motherboard manufacturer, Supermicro does not sell directly to end-users, so
it is best to fi rst check with your distributor or reseller for troubleshooting services.
They should know of any possible problem(s) with the specifi c system confi guration
that was sold to you.
1. Please go through the ‘Troubleshooting Procedures’ and 'Frequently Asked Ques-
tion' (FAQ) sections in this chapter or see the FAQs on our web site (
www.supermicro.com/support/faqs/
) before contacting Technical Support.
http://
2. BIOS upgrades can be downloaded from our web site at
com/support/bios/
Note: Not all BIOS can be fl ashed; it depends on the modifi cations to the
boot block code.
(http://www.supermicro.
).
3-2
Page 51
Chapter 3: Troubleshooting
3. If you still cannot resolve the problem, include the following inform-
ation when contacting Super Micro for technical support:
• Motherboard model and PCB revision number
• BIOS release date/version (-this can be seen on the initial display when your
system fi rst boots up)
•System confi guration
An example of a Technical Support form is on our web site at
supermicro.com/support/contact.cfm).
4. Distributors: For immediate assistance, please have your account number ready
when placing a call to our technical support department. We can be reached
by e-mail at [email protected], by phone at:(408) 503-8000, option 2,
or by fax at (408)503-8019.
(http://www.
3-3 Frequently Asked Questions
Question: What type of memory does my motherboard support?
Answer: The PDSLA/PDSLE supports unbuffered, non-ECC, DDR2-400/533/667
MHz memory modules. See Section 2-4 for details on installing memory.
Question: How do I update my BIOS?
It is recommended that you do not upgrade your BIOS if you are not experiencing
any problems with your system. Updated BIOS fi les are located on our web site at
If enabled, this option allows the BIOS to load the OS from another device rather
than the ones that have been specifi ed as the fi rst, second and third boot up devices.
The settings are Enabled and Disabled.
4-14
Page 69
Chapter 4: BIOS
4-7 Exit
Choose Exit from the Award BIOS main menu with the Left/Right arrow keys. You
should see the following display:
Save & Exit Setup
When the item Save & Exit Setup is highlighted, press <Enter> to save the changes
you've made in the BIOS program (CMOS) and exit. Your system should, then,
continue with the boot-up procedure.
Exit without Saving
When the item Exit without Saving is highlighted, press <Enter> to exit the Setup
routine without saving any changes you may have made. Your system should then
continue with the boot-up procedure.
Load Fail-Safe Defaults
Highlight this item and hit <Enter> to load the default settings for all items in the
BIOS Setup. These are the safest settings to use.
Load Optimized Defaults
Highlight this item and hit <Enter> to load the optimized settings for all items in the
BIOS Setup. These settings provide you with optimal system performance.
Discard Changes
When the item Discard Changes is highlighted, press <Enter> to discard any
changes you made to the BIOS settings and to stay in BIOS Setup. Your system
should then continue with the boot-up procedure.
4-15
Page 70
PDSLA/PDSLEUser's Manual
Notes
4-16
Page 71
Appendix A: BIOS POST Messages
Appendix A
BIOS Error Beep Codes
During the Power-On Self-Test (POST), the BIOS will check for problems. If a prob-
lem is found, the BIOS will activate an alarm or display a message. The following is
a list of such BIOS messages.
BIOS Error Beep Codes
Beep CodeError MessageDescription
1 beepRefreshCircuits have been reset.
(Ready to power up)
5 short beeps, 1 long
beep
8 beepsDisplay memory
1 continuous beep
(with the front panel
OH LED on)
Memory errorNo memory detected in the
read/write error
System Overheat1 continuous beep with the
system
Video adapter missing or with
faulty memory
front panel OH LED on)
A-1
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PDSLA/PDSLE User's Manual
Notes
A-2
Page 73
Appendix B: Award BIOS POST Codes
Appendix B
Award BIOS POST Codes
This section lists the POST (Power On Self Testing) Codes for the Award BIOS.
POST (hex) Description
CFhTest CMOS R/W functionality.
C0hEarly chipset initialization:
C1hDetect memory
C3hExpand compressed BIOS code to DRAM.
C5hCall chipset hook to copy BIOS back to E000 & F000 shadow RAM.
0h1Expand the Xgroup codes located in physical address 1000:0
02hReserved
03hInitial Superio_Early_Init switch
04hReserved
05h1. Blank out screen.
06hReserved
07h1. Clear 8042 interface.
08h1. Test special keyboard controller for Winbond 977 series Super I/O chips.
09hReserved
- Disable shadow RAM
- Disable L2 cache (socket 7 or below)
- Program basic chipset registers
- Auto detection of DRAM size, type and ECC.
- Auto detection of L2 cache (socket 7 or below)
2. Clear CMOS error fl ag.
2. Initialize 8042 self-test.
2. Enable keyboard interface.
0Ah1. Disable PS/2 mouse interface (optional).
2. Auto detect ports for keyboard and mouse followed by a port and interface swap
(optional).
3. Reset keyboard for Winbond 977 series Super I/O chips.
0BhReserved
0ChReserved
0DhReserved
0EhTest F000h segment shadow to see whether it is R/W-able or not. If test fails, keep
beeping the speaker.
0FhReserved
10hAuto detect fl ash type to load appropriate fl ash R/W codes into the run time area in
F000 for ESCD & DMI support.
B-1
Page 74
POST (hex) Description
11hReserved
PDSLA/PDSLE User's Manual
12hUse walking 1's algorithm to check out interface in CMOS circuitry. Also set real-time
13hReserved
14hProgram chipset defaults into chipset. Chipset default values are MODBINable by
15hReserved
16hInitial Early_Init_Onboard_Generator switch.
17hReserved
18hDetect CPU information including brand, SMI type (Cyrix or Intel) and CPU level
19hReserved
1AhReserved
1BhInitial interrupts vector table, If no special specifi ed, all H/W interrupts are directed
1ChReserved
1DhInitial EARLY_PM_INIT switch.
1EhReserved
1FhLoad keyboard matrix (notebook platform).
20hReserved
clock power status, and then check for override.
OEM customers.
(586 or 686).
to SPURIOUS_INT_HDLR & S/W interrupts to SPURIOUS_soft_HDLR.
21hHPM initialization (notebook platform)
22hReserved
23h1. Check validity of RTC value, e.g. a value of 5Ah is an invalid value for RTC
24hReserved
25hReserved
26hReserved
27hInitialize INT 09 buffer.
28hReserved
29h1. Program CPU internal MTRR (P6 & PII) for 0-64K memory address.
minute
2. Load CMOS settings into BIOS stack. If CMOS checksum fails, use default value
instead.
3. Prepare BIOS resource map for PCI and PnP use. If ESCD is valid, take into
consideration of the ESCD's legacy information.
4. Onboard clock generator initialization. Disable respective clock resource to
empty PCI and DIMM slots.
5. Early PCI initialization:
- Enumerate PCI bus number.
- Assign memory and I/O resource.
- Search for a valid VGA device and VGA BIOS and put it into C000:0.
2. Initialize the APIC for Pentium clas CPU.
3. Program early chipset according to CMOS setup. Example: onboard IDE controller.
4. Measure CPU speed.
5. Invoke video BIOS.
B-2
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POST (hex) Description
2AhReserved
2BhReserved
2ChReserved
Appendix B: Award BIOS POST Codes
2Dh1. Initialize multi-language.
2EhReserved
2FhReserved
30hReserved
31hReserved
32hReserved
33hReset keyboard except Winbond 977 series Super I/O chips.
34hReserved
35hReserved
36hReserved
37hReserved
38hReserved
39hReserved
3AhReserved
3BhReserved
3ChTest 8254
2. Put information on screen display, including Award title, CPU type, CPU speed,
etc.
3DhReserved
3EhTest 8259 interrupt mask bits for channel 1.
3FhReserved
40hTest 8259 interrupt mask bits for channel 2.
41hReserved
42hReserved
43hTest 8259 functionality.
44hReserved
45hReserved
46hReserved
47hInitialize EISA slot.
48hReserved
49h1. Calculate total memory by testing the last double word of each 64K page.
4AhReserved
4BhReserved
2. Program writes allocation for AMD K5 CPU.
B-3
Page 76
POST (hex) Description
4ChReserved
4DhReserved
PDSLA/PDSLE User's Manual
4Eh1. Program MTRR of M1 CPU.
4FhReserved
50hInitialize USB.
51hReserved
52hTest all memory (clear all extended memory to 0).
53hReserved
54hReserved
55hDisplay number of processors (multi-processor platform).
56hReserved
57h1. Display PnP logo.
58hReserved
59hInitialize the combined Trend Anti-Virus code.
5AhReserved
2. Initialize L2 cache for P6 class CPU & program CPU with proper cacheable
range.
3. Initialize the APIC for P6 class CPU.
4. On MP platform, adjust the cacheable range to smaller one in case the cacheable ranges between each CPU are not identical.
2. Early ISA PnP initialization.
- Assign CSN to every ISA PnP device.
5BhShow message for entering AWDFLASH.EXE from FDD (optional feature)
5ChReserved
5Dh1. Initialize Init_Onboard_Super_IO switch.
5EhReserved
5FhReserved
60hOk to enter setup utility; i.e. not until this POST stage can users enter the CMOS
61hReserved
62hReserved
63hReserved
64hReserved
65hInitialize PS/2 mouse.
66hReserved
67hPrepare memory size information for function call: INT 15h ax=E820h
68hReserved
69hTurn on L2 cache.
70hReserved
2. Initialize Init_Onboard_AUDIO switch.
utility.
B-4
Page 77
POST (hex) Description
71hReserved
72hReserved
Appendix B: Award BIOS POST Codes
73h(Optional feature)
74hReserved
75hDetect and install all IDE devices: HDD, LS120, ZIP, CD-ROM, etc.
76hReserved
77hDetect serial ports and parallel ports.
78hReserved
79hReserved
7AhDetect and install co-processor.
7BhReserved
7ChReserved
7DhReserved
7EhReserved
7Fh1. Switch back to text mode if full screen logo is supported.
80hReserved
Enter AWDFLASH.EXE if:
- AWDFLASH is found in fl oppy drive.
- ALT+F2 is pressed
- If errors occur, report errors and wait for keys.
- If no errors occur or F1 key is pressed to continue:
Clear EPA or customization logo.
81hReserved
82h1. Call chipset power management hook.
83hSave all data in stack back to CMOS.
84hInitialize ISA PnP boot devices.
85h1. USB fi nal initialization.
86hReserved
87hReserved
88hReserved
89hReserved
90hReserved
91hReserved
92hReserved
2. Recover the text font used by EPA logo (not for full screen logo).
2. NET PC: Build SYSID structure.
3. Switch screen back to text mode.
4. Set up ACPI table at top of memory.
5. Invoke ISA adapter ROMS.
6. Assign IRQs to PCI devices.
7. Initialize APM.
8. Clear noise of IRQs.
B-5
Page 78
POST (hex) Description
93hRead HDD boot sector information for Trend Anti-Virus.
PDSLA/PDSLE User's Manual
94h1. Enable L2 cache.
95h1. Program daylight saving
96h1. Build MP table.
FfhBoot attempt (INT 19h).
2. Program boot up speed.
3. Chipset fi nal initialization.
4. Power management fi nal initialization.
5. Clear screen and display memory table.
6. Program K6 write allocation.
7. Program P6 class write combining.
2. Update keyboard LED and typematic rate.
2. Build and update ESCD.
3. Set CMOS century to 20h or 19h.
4. Load CMOS time into DOS timer tick.
5. Build MSIRQ routing table.
B-6
Page 79
(Disclaimer continued)
The products sold by Supermicro are not intended for and will not be used in life support systems, medical equipment, nuclear facilities or systems, aircraft, aircraft devices, aircraft/emergency communication
devices or other critical systems whose failure to perform be reasonably expected to result in signifi cant
injury or loss of life or catastrophic property damage. Accordingly, Supermicro disclaims any and all liability, and should buyer use or sell such products for use in such ultra-hazardous applications, it does
so entirely at its own risk. Furthermore, buyer agrees to fully indemnify, defend and hold Supermicro
harmless for and against any and all claims, demands, actions, litigation, and proceedings of any kind
arising out of or related to such ultra-hazardous use or sale.
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