Sun Microsystems STP2002QFP User Manual
STP2002QFP
Revision 1.0–April 1996
STP2002QFP
Fast Ethernet, Parallel Port, SCSI
(FEPS)
USER’S GUIDE
OVERVIEW 1
1.1 Introduction
The STP2002QFP FEPS (Fast Ethernet®, Parallel, SCSI) is an ASIC that provides integrated high-performance SCSI, 10/100 Base-T Ethernet, and a Centronics compatible parallel port.
1.2 Features
FEPS features include the following:
• IEEE 1496 SBus master interface with support for 64-bit mode access
• IEEE 1496 SBus slave interface, 32-bit mode only
• 20 MB/s fast and wide single-ended SCSI using a QLogic FAS366 core
• 10/100-Mb/sec Ethernet on the motherboard
• MII (Media Independent Interface) interface to support external transceivers
• DMA2-compatible Centronics parallel port with a maximum throughput of 4
MB/s
• Supports use on an SBus card device
• Provides a path to an FCode PROM for use on SBus boards
• JTAG support for boundary and internal scan testing
1.3 Overview
FEPS contains four major blocks: SBus Adapter (SBA), SCSI_Channel,
ENET_Channel, and PP_Channel. Each channel uses the Channel Engine In-
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terface (CEI) for slave and DMA transfers with the SBus (via SBA). The SBA
provides buffering and bus conversion between the SBus and the channel engine interface. Interrupts from the channel engine go directly to the SBus. The
SBA contains no software-accessible registers.
The channel engine interface provides a common interface to the three
channel engines thus reducing verification time. This interface limits the
amount of “awareness” that the SBA has concerning DMA transactions.
The SBA supports only 32-bit programmed I/O on the SBus. There are two
64-byte DMA write buffers, to allow buffered writes. A round-robin arbitration scheme will be used between the three channel engines.
The SCSI_Channel contains the SCSI DVMA and the FAS366. The SCSI
channel can perform 64-bit SBus DMA transfer. The SCSI DVMA provides
the two 64-byte buffers to transfer data to/from FAS366. The FAS366 allows
for a 16-bit SCSI data path and a throughput of 20 Mbytes/sec. The programming model of the SCSI DVMA follows the DMA2’s SCSI. All programmed
I/O access to the FAS366 is driven by the SCSI DMA.
The Ethernet DMA can perform 64-bit SBus DMA transfers.The Ethernet
DMA has two 2K-byte FIFOs (one for transmit and one for receive). The
transmit portion of the Ethernet DMA can assist in TCP checksum generation. This requires the entire frame to be loaded into the TxFIFO before the
checksum can be inserted into the frame (that resides in the TxFIFO). The
receive portion of the Ethernet DMA can assist in checking the checksum of
an incoming frame. The receive DMA can also pass incoming frames from
the BigMac (Media Access Conmtroller) before the entire frame has been
buffered in the RxFIFO.
1.4 Technology Information
Technology features of FEPS are as follows:
• 240-pin PQFP
• 112K gates + 4K bytes dual-ported RAM
• 5-V operation only
• 1.5-W maximum power consumption
• 16–25-MHz SBus interface and parallel port, 40-MHz SCSI core, 25-MHz Fast
Ethernet core
• 48-mA SCSI, 16-mA MII direct interconnect-capable drivers
1.5 Compliance
This part is fully compliant with IEEE 1496 SBus, ANSI SCSI-2 X3T9.2/86-
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109 rev10h, ISO/IEC 8802-3, IEEE 802.3u 100 Base-T, IEEE 1149.1 (
JTAG), Centronics-protocol-compatible parallel port, and the Sun4u system
architecture.
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SBus
SBA
Channel Engine Interface
SCSI_IRQ
SCSI DVMA ENET DMA PP DMA
FAS366 BigMac PP Core
SCSI_Channel ENET_Channel PP_Channel
SCSI
Bus
MII
Interface
ENET_IRQ
Parallel Port
Figure 1. STP2002QFP Block Diagram
PP_IRQ
Boot PROM
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STP2002QFP
1.6 Pin Descriptions
The signal pins are grouped by function in the following tables.
Table 1: SBus Signals
Signal Name Type Pin Count Description
SB_D[31:0] I/O 32 SBus data
SB_A[27:0] I/O 28 SBus address
SB_SEL I 1 SBus slave select
SB_BR O 1 SBus DVMA request
SB_BG I 1 SBus DVMA grant
SB_ACK[2:0] I/O 3 SBus acknowledge codes
SB_SIZ[2:0] I/O 3 SBus transfer size
SB_RD I/O 1 SBus direction
SB_CLK I 1 SBus clock
SB_RESET I 1 SBus reset
SB_AS I 1 SBus address strobe
SB_LERR I 1 SBus late error
SB_DATAPAR I/O 1 SBus data parity
SB_SC_INT O 1 SCSI interrupt request to the system
SB_ET_INT O 1 Ethernet interrupt request to the system
SB_PP_INT O 1 Parallel port interrupt request to system
Total SBus 78
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Table 2: SCSI Signals
Signal Name Type Pin Count Description
SCSI_D[15:0] I/O 16 SCSI data
SCSI_DP[1:0] I/O 2 SCSI data parity
SCSI_SEL I/O 1 SCSI select
SCSI_BSY I/O 1 SCSI busy
SCSI_REQ I/O 1 SCSI request
SCSI_ACK I/O 1 SCSI acknowledge
SCSI_MSG I/O 1 SCSI message phase
SCSI_CD I/O 1 SCSI command/not data
SCSI_IO I/O 1 SCSI direction
SCSI_ATN I/O 1 SCSI attention
SCSI_RST I/O 1 SCSI reset
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Table 2: SCSI Signals
Signal Name Type Pin Count Description
SCSI_XTAL2 O 1 SCSI crystal output
SCSI_XTAL1 I 1 SCSI crystal input
POD I 1 SCSI power detect
Total SCSI 30
Table 3: Ethernet Signals
Signal Name Type Pin Count Description
ENET_TX_CLK I 1 Ethernet transmit clock input
ENET_TXD[3:0] O 4 Ethernet transmit data
ENET_TX_EN O 1 Ethernet transmit enable
ENET_COL I 1 Ethernet transmit collision detected
ENET_CRS I 1 Ethernet carrier sense
ENET_RX_CLK I 1 Ethernet receive clock
ENET_RXD[3:0] I 4 Ethernet receive data
ENET_RX_DV I 1 Ethernet receive data valid
ENET_RX_ER I 1 Ethernet receive error
ENET_MDC O 1 Ethernet management device clock
ENET_MDIO0 I/O 1 Ethernet management device I/O data for
on-board transceiver
ENET_MDIO1 I/O 1 Ethernet management device I/O data for
on-board transceiver
ENET_BUFFER_EN
_0
ENET_TX_CLKO O 1 Ethernet transmit clock output
Total Ethernet 20
O 1 Ethernet buffer enable
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Table 4: Parallel Port Signals
Signal Name Type Pin Count Description
PP_DATA[7:0] I/O 8 Parallel port data bus
PP_STB I/O 1 Parallel port data strobe
PP_BSY I/O 1 Parallel port busy
PP_ACK I/O 1 Parallel port acknowledge
PP_PE I 1 Parallel port paper error
PP_SLCT I 1 Parallel port select
PP_ERROR I 1 Parallel port error
PP_INIT O 1 Parallel port initialize/ALE high address byte
PP_SLCT_IN O 1 Parallel port select in
PP_AFXN O 1 Parallel port audio feed/ALE low address byte
PP_DSDIR O 1 Parallel port data strobe direction
PP_BSYDIR O 1 Parallel port busy direction
PP_ACKDIR O 1 Parallel port ack direction
PP_DDIR O 1 Parallel port data direction
ID_CS I/O 1 ID PROM chip select
Total Parallel Port 22
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Table 5: JTAG/Miscellaneous Signals
Signal Name Type Pin Count Description
JTAG_TDO O 1 JTAG test data out
JTAG_TDI I 1 JTAG test data in
JTAG_TMS I 1 JTAG test mode select
JTAG_CLK I 1 JTAG clock
JTAG_RESET I 1 JTAG TAP reset
STOP_CLOCK I 1 Stop clock input
CLK_10M O 1 10-MHz clock output
Total JTAG 7
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Table 6: Power/Ground/Other Signals
Signal Name Type Pin Count Description
VDD_CORE 4
VSS_CORE 4
V
DD
V
SS
Reserved 1
MODE 1 Mode select (stand alone/chipset)
Total 83
21
52
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STP2002QFP
SBUS ADAPTER 2
2.1 Introduction
The SBus Adapter (SBA) is the layer between the Channel Engine Interface
(CEI) and the SBus. It provides one master port on the SBus side to funnel
three DMA channel engines (CE) onto the SBus, and one slave port for SBus
accesses to the CEs. The SBA can be viewed as a block of data path and flow
control between SBus and channel engine interface.
2.2 SBus Capabilities
2.2.1 Slave Accesses
• Supports byte/half-word/word access, but not burst transfer
• Supports 32-bit transfer mode
• Parity generation/checking
• Does not generate late error
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• Does not generate Rerun Ack
• Maximum latency < 22 SBus clocks
2.2.2 Master Accesses
• Compliant to IEEE 1496
• Supports 64-bit/32-bit transfer mode
• Supports byte/half-word/word transfer size
• Supports burst transfer size from 8 bytes to 64 bytes
• Parity generation/checking
• Does not issue atomic transaction
• Does not support bus sizing
2.2.3 Address Decoding
In order to eliminate the need of NEXUS driver in between FEPS device driver and the kernel there are no registers insides the SBA block (a register inside
SBA would be a global register which means a NEXUS driver is needed).
However, SBA does decode the physical address input and the access size for
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slave accesses from SBus. The physical address is decoded to select a target
CE to respond to the access. A physical address that cannot be resolved to the
selection of any channel engine will cause SBus Adapter to return Error Ack.
The access size is decoded to Error Ack 64-bit transfer mode or burst transfer
that is not supported by FEPS.
2.3 Theory of Operation
2.3.1 Master Operations
All master operations are originated from the channel engines. The operations
start when one or more bus requests are asserted on the channel engine interface.
2.3.1.1 DVMA Write
DVMA write cycle starts when the channel engine with highest priority asserts BR signal on CEI with RD (bit[63] of CE_DOUT signal) signal de-asserted. The arbiter inside SBA asserts grant signal (BG) to the requesting CE
and kick off the CEI write state machine. CEI write state machine first latches
the DVMA address, transfer size and channel ID from the requesting CE and
then begin to move data from CEI and write them to the current DVMA data
write buffer. When the whole burst of write data are written to the write buffer, the CEI state machine places a write request into the request command
queue of the SBus Master Port State machine and, at the mean time, it release
the arbiter to arbitrate the next request on the CEI. The master port state machine wakes up and requests the SBus whenever there is a request in the
queue. When the whole burst of Data is written to the SBus, the master port
state machine return the acknowledgment (MEMDONE) and status
(CE_DWERR) to the corresponding CE.
When a CE is granted for DMA write, the CEI bus is locked until the whole
burst of write data is moved over to the write data buffer. During this period,
only the slave write operation from the SBus can occur on the CEI. A slave
read would have to wait until the DMA write cycle is done. On the other hand,
a slave read operation will have the same effect as DMA write that will also
lock up the CEI for the duration of the whole transaction.
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2.3.1.2 DVMA Read
DVMA Read cycle starts with the highest priority channel engine asserts BR
signal on CEI with RD (bit[63] of CE_DOUT signal) signal asserted. The arbiter latches the DVMA address, transfer size and channel ID and places a
Read request into the request command queue of the SBus master port state
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machine. After this the arbiter is available to arbitrate and grant the next request on the CEI provided that there is a DMA write or read buffer still available. The master port state machine wakes up and request the SBus whenever
there is a request in the queue. When SBus is granted, the master port state
machine asserted BG to the corresponding CE and pass the read data over to
the CEI bus.
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2.3.2 Slave Operation
When both AS and SEL input signals are asserted, the slave port begin to respond to the slave access from the SBus. Based on the physical address, one
of the channel engines is selected to respond to the slave access. Slave writes
goes directly through to the CEI bus without arbitration because it share the
CEI data-in data bus with DVMA read which is mutually exclusive to slave
operation. Slave reads share the CEI data-out bus with all other CEI operations and have to go through arbiter to compete with channel engines.
Because a SBus DVMA read operation may encounter a retry, there is condition that a CE is being granted with DVMA read and a slave access still
comes in. The CE has to make sure that it can still respond to this slave access
under this condition.
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SCSI CHANNEL 3
3.1 Introduction
The SCSI channel consists of SCSI DVMA (also referred to as SCSI channel
engine) and FAS366, a “Fast and Wide” SCSI controller core. The SCSI
DVMA provides two 64-byte buffers used to transfer data to/from the
FAS366. The FAS366 supplies a 16-bit SCSI data path and a throughput of
20 MB/sec. All programmed I/O access to the FAS366 is driven by the SCSI
DVMA.
Several programmable registers can be used by the SCSI device driver to
direct the SCSI engine and FAS366 to move blocks of data to/from host
memory or to/from devices on the SCSI bus. Once the transfer is complete,
an interrupt is generated on the SBus to inform the driver that block movement is complete, freeing it to initiate further transfers.
3.2 SCSI DVMA
SCSI DVMA is responsible for data movement between FAS366 and the host
memory. It contains two 64-byte buffers. The purpose for providing these
buffers is to have prefetch capability. With this scheme of prefetch buffers,
one buffer can be used for writing/reading data on SBus, while the other buffer can be used for reading/writing data from/to FAS366. For SCSI write operation (reading from host memory and writing to FAS366), a chunk of data
is moved from the host memory and stored in the buffers. When FAS366 is
ready to accept data, this data is written to FAS366. For SCSI read operation
(reading from FAS366 and writing to host memory), data being read from
FAS366 is stored in the buffers. This data is written into host memory at a later time. The whole idea of providing buffers is to absorb the difference in data
transfer rate, between SBus and SCSI bus.
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3.3 FAS366
FAS366 is a Fast and Wide SCSI controller core and is integrated into FEPS
as a hard macro.
The following are some of the features of the FAS366 core:
• Supports ANSI X3T9.2/86-109 (SCSI-2) standard
• Sustained SCSI data transfer rates:
- 10-MHz synchronous (fast SCSI)
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- 5-MHz synchronous (normal SCSI)
- 6-MHz asynchronous
• REQ/ACK programmable assertion/deassertion control
• Power-on connect/disconnect to SCSI bus (hot plugging)
• Target block transfer sequence
• Initiator block transfer sequence
• Bus idle timer
• Reduced SCSI bus overhead
• On-chip, single-ended SCSI drivers (48 mA)
• Target and initiator modes
• 16-bit recommand counter
• Differential mode support
For more information on FAS366, refer to the FAS366 specification from
Emulex.
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3.4 Test Support
The SCSI DVMA will support full internal and boundary scan. The FAS366
core does not support full internal scan. SCSI I/O pads will support boundary
scan.
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PARALLEL PORT CHANNEL 4
4.1 Introduction
The parallel port interface implementation of FEPS is almost identical to the
one on the STP2000 Master I/O controller chip to leverage the existing device
driver. The only difference is that the DIR bit has to be set during a memory
clear operation. It allows the CPU to send data to the standard Centronics
printer in both programmed I/O and DMA modes. The parallel interface can
support bidirectional transfers using Xerox and IBM schemes. A 64-byte
buffer is used to buffer data to and from the channel engine interface and the
parallel port in DMA mode, depending on the direction of the transaction. In
synchronous mode, the port can support data transfer rate up to 4 Mbytes/s.
The parallel port interface also provides the data path to read the FCode
PROM when the FEPS chip is used on a SBus extended card. Two external
8-bit latches are needed to latch the MSB and LSB of the EPROM address.
Refer to the FEPS Application note for more details on this mode.
4.2 Parallel Port FIFO Operation
Between the parallel port and the SBus interface is a 64-byte FIFO (P_FIFO).
This FIFO is bypassed for slave accesses to the parallel port registers. Consistency control ensures that all data written by the external device gets to
main memory in a deterministic manner, and is handled completely in hardware. One of the consistency control mechanisms used on transfers to memory is draining of all P_FIFO data upon the access of any parallel port register.
The conditions that cause data in the P_FIFO to be drained to memory are
as follows:
1. 4, 16, or 32 bytes (depending on P_BURST_SIZE) have been
written into the P_FIFO.
2. The P_INT_PEND bit in the P_CSR is set.
3. The CPU does a slave write to a parallel port internal register
other than the P_TST_CSR (writing P_ADDR does not cause
draining if P_DIAG is set).
4. The P_RESET or P_INVALIDATE bit in the P_CSR is set.
5. The P_ADDR register is loaded from P_NEXT_ADDR when
P_DIAG is not set.
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None of these conditions will cause draining if P_ERR_PEND = 1, indicating that a memory error has occurred. If condition 4 or 5 occurs when the
P_ERR_PEND bit is 1, the P_FIFO will be invalidated and all dirty data will
be discarded.
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4.3 Bidirectional Parallel Port Interface
The parallel port can operate unidirectionally or bidirectionally in either a
programmed I/O mode or in a DMA mode. The hardware interface can be
configured to operate with a wide range of devices through the following
mechanisms:
• Bidirectional signal configuration for the interface control signals—
data strobe, acknowledge, and busy. Each control signal can be individually configured as a unidirectional or bidirectional signal.
• Programmable pulse widths for all generated signals and programma-
ble data setup time for data transfers.
• Programmable protocol definition for all combinations of acknowl-
edge and busy handshaking.
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This interface configuration capability will allow operation over a wide
range of data transfer rates and protocol definitions.
4.3.1 DMA Mode
Since no software intervention is required for data transfer, the interface protocol and timing required must be programmed via the configuration registers. DMA transfers are initiated/enabled by setting the P_EN_DMA bit of
the P_CSR. The operation of the interface is dependent on the direction of
transfer and the protocol selected as described below.
4.3.1.1 Unidirectional Operation (Transfers to the Peripheral Device)
This mode of operation is the Centronics implementation of a unidirectional
parallel port. Operation of the parallel port in this mode requires the direction
control bit (DIR) of the transfer control register (TCR) to be 0. Timing variations are handled via the DSS (data setup to data strobe) and DSW (data
strobe width) bits of the hardware configuration register. The timebase for
programmability is the SBus clock. The DSS parameter (7 bits) can be programmed from a minimum of 0 SBus clocks to 127 SBus clocks in steps of
one SBus clock. The DSW parameter (7 bits) is also programmed in steps of
one SBus clocks, however when DSW= 0, 1, 2, or 3, data strobe width is de-
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fined as three SBus clocks. That is, the minimum data strobe width is three
SBus clocks. The following table shows the nominal range of programmability for different SBus clock speeds.
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STP2002QFP
Table 7:
SBus Clock DSS DSW
16.67 MHz 0–7.62 µs 180.0 ns–7.62 µs
20 MHz 0–6.35 µs 150.0 ns–6.3 µs
25 MHz 0–5.08 µs 120.0 ns–5.08 µs
The desired handshake protocol can be selected using the ACK_OP
(acknowledge operation) and BUSY_OP (busy operation) bits of the opera-
tions configuration register (OCR). The function of these bits is defined as
follows:
ACK_OP 1 = Handshake complete with receipt of P_ACK (PP_ACK).
0 = P_ACK (PP_ACK) is ignored.
BUSY_OP 1 = Handshake complete with receipt of P_BSY (PP_BSY).
0 = P_BSY (PP_BSY) is not used for handshaking.
These two bits allow selection of one of four possible protocols, however
only three of these protocols make sense and are valid selections. The case of
ACK_OP=BUSY_OP=1, is not supported. For all protocol selections, if
P_BSY (PP_BSY) is active, further data transfers will not occur until P_BSY
(PP_BSY) is negated. The following table summarizes the protocol definitions for transfers to the peripheral device.
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Table 8:
BUSY_OP ACK_OP Protocol Definition
0 0 No handshaking occurs
0 1 Acknowledge is required for each byte transferred
10P_BSY is used as acknowledge and is required for each byte
transferred. ACK is ignored
1 1 Invalid
The transfer modes are shown and discussed in the following sections.
4.3.1.1.1 No Handshake (BUSY_OP=0, ACK_OP=0)
Data transfers are controlled by the use of P_D_STRB (PP_STB) and optionally P_BSY (PP_BSY). There is no acknowledge in this mode and P_ACK
(PP_ACK) is a don’t care. P_BSY (PP_BSY) is used to gate further transfers
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P_DATA (O)
P_D_STRB (O)
P_ACK (I)
P_BSY (I)
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
when the peripheral device cannot receive another byte of data. P_BSY
(PP_BSY) is sampled before data strobe becomes active and after data strobe
becomes inactive, to ensure that a data transfer is not attempted while the device is busy.
It is this mode, which provides the fastest transfer of data over the interface, the fastest cycle time is six SBus clocks per byte. This transfer time is
arrived at as follows: DSS=0, DSW=3 (minimum width of DSW is three
SBus clocks), and three SBus clocks between consecutive data strobes. This
assumes that P_BSY (PP_BSY) is not asserted during the transfer cycle. Reference Figure 2.
1
DSS
2
DSW
3
Don’t Care
4
1
DSS
2
DSW
5
1. Data setup as defined in the hardware configuration register.
2. Data strobe width as defined in the hardware configuration register.
3. There is a three SBus clock delay from the end of data strobe to the next byte of data being clocked onto the P_DATA
bus.
4. Acknowledge is a don’t care condition for all data transfers.
P_BSY is active, it gates further data transfers.
5. When
Figure 2.
4.3.1.1.2 Handshake with Ack: BUSY_OP=0, ACK_OP=1)
Data transfers are controlled by the use of P_D_STRB (PP_STB), P_ACK
(PP_ACK), and optionally P_BSY (PP_BSY). P_ACK (PP_ACK) is required for each byte transferred. If P_BSY (PP_BSY) is active at the end of
the cycle, further data transfers will be gated until P_BSY (PP_BSY) becomes inactive. If P_BSY (PP_BSY) is not present, then data transfers will
proceed. P_BSY (PP_BSY) is also sampled immediately before P_D_STRB
(PP_STB) is generated to ensure that a data transfer is not attempted while the
device is busy. Reference the data transfer diagram in Figure 3.
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P_D_STRB
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1
DSS
2
DSW
3
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5
P_ACK (I)
1. Data setup as defined in the hardware configuration register.
2. Data strobe width as defined in the hardware configuration register.
3. Acknowledge is required for each byte transferred.
P_BSY is active, it gates further data transfers.
4. When
P_BSY is not present, the next data byte will be gated on to the bus following ACK (there is a minimum of three SBus clocks between
5. If
the trailing edge of ACK and the next data byte).
6. All signal polarities shown are at the HIOD pins. Polarities on the interface cable should be inverted (except P_DATA).
4
Figure 3.
4.3.1.1.3 Handshake with Busy (ACK_OP=0, BUSY_OP=1)
Data transfers are controlled by the use of P_D_STRB (PP_STB) and P_BSY
(PP_BSY). P_ACK (PP_ACK) is a don’t care in this mode. P_BSY
(PP_BSY) is required as an acknowledge after P_D_STRB (PP_STB) and
will gate any further data transfers while it is active. P_BSY (PP_BSY) is also
sampled immediately before P_D_STRB (PP_STB) is generated to ensure
that a data transfer is not attempted while the device is busy. Reference the
data transfer diagram in Figure 4.
P_DATA (O)
P_D_STRB
(O)
P_ACK (I)
1
DSS
DSW
2
3
Don’t Care
4
5
1. Data setup as defined in the hardware configuration register.
2. Data strobe width as defined in the hardware configuration register.
3. Acknowledge is a don’t care condition for all data transfers.
P_BSY is required as an acknowledge for each byte transferred. While P_BSY is present, it gates fuirther data transfers.
4.
5. The next byte of data will be gated on to the bus following the trailing edge of
the trailing edge of
6. All signal polarities shown are at the HIOD pins. Polarities on the interface cable should be inverted (except P_DATA).
P_BSY and the next byte of data).
P_BSY (there is a minimum of three SBus clocks between
Figure 4.
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4.3.1.2 Bidirectional Operation
Bidirectional data transfer over the parallel port can be accomplished by the
use of either of two master/slave protocols. The “master write” protocol or the
“master read/write” protocol. The IBM implementation of a bidirectional parallel port uses the master write protocol in which the master always writes
data to the slave and when the direction of data transfer needs to be reversed,
mastership is exchanged. The Xerox implementation uses the master
read/write protocol where data transfer is performed in either direction under
control of the fixed master. The parallel port will operate as either master or
slave when configured for master write protocol, and only as the master when
configured for the master read/write protocol.
The selection of one of these bidirectional transfer methods is accomplished indirectly through the specification of the bidirectional nature of the
data strobe signal. Since in both methods data strobe resides with the master,
a bidirectional data strobe implies the IBM master write scheme and a fixed
data strobe (output only) implies the Xerox master read/write scheme.
The interface control signals—data strobe, acknowledge, and busy—are
individually configurable as bidirectional or unidirectional pins. The bidirectional signal configuration bits are located in the operation configuration
register. The functions of the bits are as follows:
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DS_DSEL 1 = P_DS (PP_DSDIR) is bidirectional, master write protocol selected.
0 = P_DS (PP_DSDIR) is fixed as output. Master read/write protocol
selected.
ACK_DSEL 1 = P_ACK (PP_ACK) is bidirectional.
0 = P_ACK (PP_ACK) is fixed as an input.
BUSY_DSEL 1 = P_BSY (PP_BSY) is bidirectional.
0 = P_BSY (PP_BSY) is fixed as an input.
To allow external driver/receiver connection, each of these control signals
and the data bus has a corresponding direction control pin. The DIR bit of the
transfer control register is used to switch the direction of the data bus and the
pins that have been configured as bidirectional. The state of the DIR bit is
reflected on the P_D_DIR (PP_DDIR) pin for external transceiver control
and direction control communication to the attached device. While DIR=0,
all pins remain in their unidirectional sense which is defined to be consistent
with the unidirectional parallel port as follows:
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Table 9:
Signal I/O DIR_Pin State
P_D_STRB (PP_STB) O P_DS_DIR (PP_DSDIR) 1
P_ACK (PP_ACK) I P_ACK_DIR (PP_ACKDIR) 0
P_BSY (PP_BSY) I P_BSY_DIR (PP_BSYDIR) 0
P_DATA (PP_DATA) O P_D_DIR (PP_DDIR) 1
When DIR is set to 1, the pins configured as bidirectional change direction
and their corresponding direction control pins are set accordingly. Note that
the input status pins (ERR, SLCT, PE), which are readable in the input regis-
ter, are not configurable. They are fixed as inputs. Similarly, the output pins
(PP_AFXN, PP_INIT, PP_SLCT_IN) of the output register are fixed as
outputs.
The transfer modes are shown and discussed in the following sections.
4.3.1.3 Master Write Protocol, Slave Operation
This section describes the parallel port operation as a slave when it is configured for master write protocol (DS_DSEL=1). Operation as a master is the
same as is described in the “Unidirectional Operation (Transfers to the Peripheral Device)” section on page 15.
In this mode, acknowledge and/or busy can be generated in response to a
data strobe. The width of the P_ACK (PP_ACK) pulse can be defined using
the DSW bits of the hardware configuration register. The P_BSY (PP_BSY)
hold time and P_ACK (PP_ACK) positioning after the trailing edge of data
strobe are defined using the DSS bits. However, note that in this mode DSS
has a tolerance of +3 to 4 SBus clocks, due to synchronization delays. The
nominal programmability range is the same as was specified in the “Unidirectional Operation (Transfers to the Peripheral Device)” section on page 15.
The ACK_OP and BUSY_OP bits are used to specify handshake protocol.
The function of the bits take on a new meaning when the parallel port is a
slave.
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ACK_OP 1 = Generate P_ACK (PP_ACK) in response to a data strobe.
0 = P_ACK (PP_ACK) is not generated. P_ACK is held in an inactive state.
BUSY_OP 1 = Generate P_BSY (PP_BSY) as an acknowledge, in response to data strobe.
0 = P_BSY (PP_BSY) is not generated for each byte transferred, but is asserted
as required.
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These two bits allow selection of one of four possible handshake protocols.
The following table summarizes the protocol definitions for transfers to the
parallel port from the peripheral device.
For all protocol selections, P_BSY (PP_BSY) will become active if one of
the following conditions occur: The P_DMA_ON bit is reset indicating
DMA cannot proceed; or the
P_FIFO is unable to accept more data. Internally, P_BSY (PP_BSY) will
always be generated for these conditions. However, if the P_BSY (PP_BSY)
pin is not configured as an output, it will not be driven and the external interface will not be able to detect the busy condition. In this case, data could be
lost. In all cases, if P_BSY (PP_BSY) is asserted it will have the following
timing characteristics:
P_D_STRB
(I)
1. WHen data strobe is detected, P_BSY will be generated within 3 SBus clocks, if required.
P_BSY hold time after data strobe is configurable via DSS.
2.
1
2
DSS
Figure 5.
The transfer modes are shown and discussed in the following sections.
4.3.1.3.1 No Handshake: (BUSY_OP=0, ACK_OP=0)
No handshake signals are generated in this mode. If P_ACK (PP_ACK) is
configured as an output, it will remain low or inactive. P_BSY (PP_BSY) will
be generated as required to gate further transfers, but not as a handshake signal. The operation of the interface as defined assumes the bidirectional sense
of each signal has been configured as follows: DIR=1, DS_DSEL=1,
ACK_DSEL=X, BUSY_DSEL=1. If P_ACK (PP_ACK) is configured as
an output, it will remain low or inactive. The configuration of P_BSY
(PP_BSY) as an output is suggested to avoid potential data loss. Reference
the parallel port timing section for detailed timing requirements for this mode.
4.3.1.3.2 Handshake with ACK: (BUSY_OP=0, ACK_OP=1)
Data transfers are acknowledged using P_ACK (PP_ACK). The position of
P_ACK (PP_ACK) relative to the trailing edge of data strobe is set using
DSS. Note that in this mode, the actual positioning of P_ACK (PP_ACK) will
be DSS plus 3 to 4 SBus clocks, due to synchronization delays. The width of
P_ACK (PP_ACK) is set using DSW. P_BSY (PP_BSY) will be generated
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as required to gate further transfers but not as a handshake signal. The operation of the interface as defined assumes the bidirectional sense of each signal
has been configured as follows: DIR=1, DS_DSEL=1, ACK_DSEL=1,
BUSY_DSEL=1. The configuration of P_BSY (PP_BSY) as an output is
suggested to avoid potential data loss. Reference the data transfer diagram in
Figure 6.
P_DATA (I)
P_D_STRB
(I)
P_ACK (O)
3
1. Acknowledge position relative to data strobe (DSS - hardware configuration register).
2. Acknowledge width (DSW - hardware configuration register).
P_BSY will be asserted if required.
3.
4. All signal polarities shown are at the HIOD pins. Polarities on the interface cable should be inverted (except P_DATA).
1
DSS
2
DSW
Figure 6.
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4.3.1.3.3 Handshake with BUSY: (BUSY_OP=1, ACK_OP=0)
Data transfers are acknowledged using P_BSY (PP_BSY). P_BSY
(PP_BSY) will be generated off of the leading edge of P_D_STRB (PP_STB)
and will remain active for the period specified by DSS (plus 3 to 4 SBus
clocks) beyond the end of P_D_STRB (PP_STB). The operation of the interface as defined assumes the bidirectional sense of each signal has been configured as follows: DIR=1, DS_DSEL=1, ACK_DSEL=X,
BUSY_DSEL=1. The configuration of P_ACK as an input will not hinder the
operation of the interface as far as handshaking is concerned. If P_ACK is
configured as an output, it will remain low or inactive. Reference the data
transfer diagram Figure 7.
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STP2002QFP
P_DATA (I)
P_D_STRB
(I)
P_ACK (O)
1. P_BSY hold time after data strobe (DSS - hardware configuration register)
2. All signal polarities shown are at the HIOD pins. Polarities on the interface cable should be inverted (except P_DATA).
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
Logic 0
1
DSS
Figure 7.
4.3.1.3.4 Handshake with ACK and BUSY: (BUSY_OP=1, ACK_OP=1)
Both P_ACK (PP_ACK) and P_BSY (PP_BSY) are generated in response to
a data strobe. P_BSY (PP_BSY) will be generated off of the leading edge of
P_D_STRB (PP_STB) and will remain active for 3 SBus clocks beyond the
end of P_ACK (PP_ACK). The position of P_ACK (PP_ACK) relative to the
trailing edge of data strobe is defined by DSS (again DSS has a tolerance of
+3 to 4 SBus clocks). The width of P_ACK (PP_ACK) is set usingDSW. The
operation of the interface as defined assumes the bidirectional sense of each
signal has been configured as follows: DIR=1, DS_DSEL=1,
ACK_DSEL=1, BUSY_DSEL=1. Reference the data transfer diagram in
Figure 8.
P_DATA (I)
P_D_STRB
(I)
P_ACK (O)
1. Acknowledge position relative to data strobe (DSS - hardware configuration register).
2. Acknowledge width (DSW - hardware configuration register).
P_BSY is deasserted 3 SBus clocks following the trailing edge of ACK.
3.
4. All signal polarities shown are at the HIOD pins. Polarities on the interface cable should be inverted (except P_DATA).
1
DSS
2
DSW
3
Figure 8.
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4.3.1.4 Master Read/Write Protocol (Xerox Mode)
This section describes the parallel port operation while master read cycles are
performed. Operation while master write cycles are performed is the same as
is described in the “Unidirectional Operation (Transfers to the Peripheral Device)” section on page 15.
Data transfer for master read cycles is accomplished by the master generating a data strobe (request for data) with no data present on the P_DATA
(PP_DATA) bus. The peripheral responds by placing data on the P_DATA
(PP_DATA) bus and generating an P_ACK (PP_ACK) which functions as a
strobe. Only one handshake protocol is valid for master read cycles and is
described below.
4.3.1.4.1 Handshake with ACK: (BUSY_OP=0, ACK_OP=1)
Data is transferred to the HIOD by the use of P_ACK (PP_ACK).
P_D_STRB (PP_STB) width is defined by DSW. DSS is used to define the
required interval from P_ACK (PP_ACK) to the next P_D_STRB (PP_STB).
P_BSY (PP_BSY) will gate further data transfers if present. The operation of
the interface as defined assumes the bidirectional sense of each signal has
been configured as follows: DIR=1, DS_DSEL=0, ACK_DSEL=0,
BUSY_DSEL=0. Reference the data transfer diagram in Figure 9.
P_DATA (I)
P_D_STRB
(O)
P_ACK (I)
1. Data strobe width as defined in the hardware configuration register.
2. DSS is used for ACK to P_D_STRB stiming (Hardware configuration register).
3. Acknowledge is used as a strobe and is required for each byte transferred.
P_BSY is active, it gates further data transfers.
4. If
5. All signal polarities shown are at the HIOD pins. Polarities on the interface cable should be inverted (except P_DATA).
1
DSW
3
2
DSS
4
Figure 9.
4.3.2 Programmed I/O Mode
Programmed I/O mode is intended to allow the parallel port to operate primarily under software control. Data latching, interrupt, and busy generation are
performed in hardware as required. The following two sections describe op-
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eration for transfers to and from the peripheral device.
4.3.2.1 PIO on Transfers to the Peripheral Device
For transfers to the peripheral device, all signals are under the control of software. There is no hardware assist other than interrupt generation.
4.3.2.2 PIO on Transfers From the Peripheral Device
The two modes of bidirectional operation previously discussed are supported
with hardware-assisted data latching. The bidirectional select bits
(DS_DSEL, ACK_DSEL, BUSY_DSEL) should be set according to the desired configuration. The handshake protocol bits (ACK_OP, BUSY_OP)
have no function in PIO mode.
During operation as a slave under the master write protocol (DS_DSEL=1,
DIR=1), data is sampled and latched once data strobe has been detected.
P_BSY (PP_BSY) becomes active at the same time that data is latched and
must be made inactive under software control.
During operation under master read/write protocol (DS_DSEL=0,
DIR=1), master reads are assisted by sampling and latching the data once
P_ACK (PP_ACK) has been detected. P_BSY (PP_BSY) is not generated in
this mode.
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4.4 Differences from STP2000 (MACIO) Parallel Port
• PP_INIT and PP_AFXN have extra functions: high and low address
latch clocks
• EPROM address is given by parallel port data bus
• DIR bit in the TCR register must be set during memory clear operation
4.5 Test Support
The TST_CSR provides a way for the user to test the DMA engine. The test
consists of moving one block data of the size of a read burst from the host
memory into the FIFO. The user then instructs the engine to drain data back
to the host memory at an address which is programmable.
The maximum size of a read burst is 32 bytes. Since the starting address of
the FIFO register cannot be programmed, the user has no control over which
FIFO registers should be tested. And since the maximum size of the burst is
limited to 32 bytes, the entire FIFO (64 bytes) cannot be tested.
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ETHERNET CHANNEL 5
5.1 Introduction
The Ethernet channel is a dual-channel intelligent DMA controller on the system side, and an IEEE 802.3 Media Access Control (MAC) on the network
side. It is designed as a high-performance full-duplex device, allowing for simultaneous transfers of data from/to host memory to/from the “wire.” The
two main functions of the Ethernet channel are to provide MAC function for
a 10-/100-Mbps CSMA/CD protocol based network and to provide a highperformance two-channel DVMA host interface between the MAC controller
and the SBus. The Ethernet channel supports 10/100-Mbit Fast Ethernet. The
Fast Ethernet standard is backwards compatible with the standard 10-Mb/s
Ethernet standard. The speed is auto-sensed. An RJ-45 connector supports
twisted-pair style of Ethernet. In addition, a Media Independent Interface
(MII) connection is supported through an external transceiver to allow adaptation to any other form of Ethernet (AUI/TP/ThinNet).
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5.2 Functional Description
5.2.1 Overview
Packets scheduled for transmission are transferred over the SBus into a local
transmit FIFO and are later transferred to the TX_MAC core for protocol processing and transmission over the medium. A programmable transmit threshold is provided to enable the transmission of the frame. The reverse process
takes place in the receive path. Packets received from the medium are processed by the RX_MAC, loaded into the receive FIFO, and are later transferred to the host memory over the SBus. The receive threshold for data
transfers is 128 bytes.
At the device driver level, the user deals with transmit and receive descriptor-ring data structures for posting packets and checking status. In the
transmit case, packets may be posted to the hardware in multiple buffers
(descriptors), and the transmit DMA engine will perform “data gather.” In the
receive case, the receive DMA engine will store an entire packet in each
buffer that was allocated by the host. “Data scatter” is not supported, but
instead a programmable first byte-alignment offset within a burst is
implemented.
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For TCP packets, hardware support is provided for TCP checksum computation. On transmit, it is assumed that the entire packet is loaded into the local
FIFO before its transmission begins. The checksum is computed on-the-fly
while the packet is being transferred from the host memory into the local
FIFO. The checksum result is then stuffed into the appropriate field in the
packet, and the transmission of the frame begins. On receive, checksum is
computed on the incoming data stream from the MAC core, and the result is
posted to the device driver as part of the packet status in the descriptor.
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5.2.2 Functional Blocks
The Ethernet channel is comprised of five major blocks:
• BigMAC core
• Management interface (MIF)
• Ethernet transmit (ETX)
• Ethernet receive (ERX)
• Shared Ethernet block (SEB)
5.2.2.1 BigMAC Core
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The BigMAC core implements the IEEE 802.3 MAC protocol for 10-/100Mbps CSMA/CD networks. It consists of four major functional modules:
• Host interface buffer
Implements the programmed I/O interface between the SEB and BigMAC core
• Transmit MAC (TX_MAC)
- Implements the IEEE 802.3 transmit portion of the protocol
- Implements the slave interface handshake between the ETX and
TX_MAC for frame data transfers
- Performs the synchronization between the system clock domain and
the transmit media clock domain in the transmit data path
• Receive MAC (RX_MAC)
- Implements the IEEE 802.3 receive portion of the protocol
- Implements the slave interface handshake between the ERX and
RX_MAC for frame data transfers
- Performs the synchronization between the system clock domain and
the receive media clock domain in the receive data path
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• Transceiver interface (XIF)
- Implements the MII interface protocol (excluding the management
interface)
- Performs the nibble-to-byte and byte-to-nibble conversion between
the protocol engine and the MII
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