SUD®
microsystems
Sun
3400 CPU
Board
Configuration
Manual
Part
No:
Part
Number:
813-2055-11
Revision A
of
15
May
1989
#+sun®
• microsystems
Sun
3400
CPU
Board
Configuration Manual
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are registered trademarks
of
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Sun, Sun-2, Sun-3, Sun-4, Sun386i, NFS, Suninstall, SunLink,
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are trademarks
of
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All other products
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or
seivice marks
of
their
respective companies
or
organizations, and Sun Microsystems, Inc. disclaims any responsibility for specifying which
marks are owned by which companies
or
organizations.
CAUTION
This equipment generates, uses,
and
can
radiate
radio frequency energy
and
if
not installed
and
used in accor-
dance with the instructions manual,
may
cause interference to
radio
communications.
It
has been tested
and
found to comply with the limits for a Class A computing device
pursuant
to
Subpart
J
of
Part
15
of
FCC
Rules,
which
are
designed to provide reasonable protection against such interference when
operated
in a commercial
environment.
Operation
of
this equipment in a residential
area
is likely to cause interference in which case the
user
at
his own expense will be
required
to take whatever measures may be
required
to
correct
the interfer-
ence.
This digital
apparatus
does
not
exceed the Class A limits for radio noise emissions from digital
apparatus
set
out in the Radio Interference Regulations
of
the Canadian
Department
of
Communications.
Le present
appareil
numerique
n'emet
pas de bruits radioelectriques depassant
les limites applicables
aux
appareils numeriques de
la classe
A prescrites dans le Reglement
sur
le
brouillage radioelectrique
edicte
par
le
ministere des Communications
du
Canada.
WARNING
There
is a
Lithium
Battery, Matsushita Electric Type No. BR2325, located on the
Sun
CPU
Board. This bat-
tery is
NOT
a customer replaceable
part.
The
battery
is
marked
as follows:
"Warning-
Replace
battery
with
MATSUSHITA
ELECTRIC,
PANASONIC,
or
RA YOVAC
Part
No. BR2325
only."
The
battery
may
explode
if
mistreated. Do not dispose
of
the
battery
in fire.
Do
not disassemble it
or
recharge
it.
Copyright© 1989 Sun
Microsystem~.
Inc. - Printed in
U.S.A.
All rights reserved. No part
of
this work covered by copyright hereon may
be
reproduced in any form
or
by any
means - graphic, electronic,
or
mechanical - including photocopying, recording, taping,
or
storage in an information
retrieval system, without the prior written permission
of
the copyright owner.
Restricted rights legend: use, duplication,
or
disclosure by the U.S. government is subject to restrictions set forth in
subparagraph (c)(l)(ii)
of
the Rights in Technical Data and Computer Software clause at DFARS 52.227-7013 and in
similar clauses in the FAR and NASA FAR Supplement.
The Sun Graphical
User
Interface was developed by Sun Microsystems Inc. for its users and licensees. Sun ack-
nowledges the pioneering efforts
of
Xerox in researching and developing the concept
of
visual
or
graphical user inter-
faces for the computer industry. Sun holds a non-exclusive license from Xerox to the Xerox Graphical
User
Interface,
which license also covers Sun's licensees.
Contents
Chapter 1
General Description
and
Configuration.......................................... 3
Introduction
......................................................................................................................
3
General
Sun 3400
CPU
Board Description
......................................................
3
Video Daughter Boards
.............................................................................................
4
Configuration
of
the Jumpers on the 3400
CPU
Board
............................
4
ECC Memory Configuration
..................................................................................
4
-m-
Tables
Table
1-1
Factory Con.figuration
of
Jumpers on the
3400 CPU
Board.......... 5
-v-
Figures
Figure
1-1
Section
A-Hof
the
Board..................................................................................
6
Figure 1-2
Section
1-0
of
the
Board...................................................................................
7
-vii-
1
General Description and Configuration
General Description and Configuration
.......................................................................
3
Introduction
......................................................................................................................
3
General Sun 3400
CPU Board Description
......................................................
3
Video Daughter Boards
.............................................................................................
4
Configuration
of
the Jumpers on the 3400
CPU
Board............................
4
ECC Memory Configuration
..................................................................................
4
Introduction
General
Sun
3400
CPU
Board
Description
1
General Description and Configuration
This document identifies jumper-block locations and describes required jumper
configurations on the
Sun 3400
CPU
Board.
Instructions for the removal and installation
of
your boards are contained in their
respective board installation manuals. Instructions for board access and backplane jumper access are contained in your system installation manual. Instructions for the configuration
of
your backplane jumpers are contained in your
Sun-
31460
and
31480
Cardcage
Slot
Assignments
and
Backplane Con.figuration Pro-
cedures
manual
(P/N 813-2056), CCSA
and BCA
(PIN
2004)
or
in your
Sun-
31470
Cardcage
Slot
Assignments
and
Backplane Con.figuration Procedures
manual (P/N
813-2073).
Instructions for the configuration
of
your memory boards
or
your frame buff er
boards are covered in their respective memory board
or
frame
buff
er
board
manuals.
Standard features
of
the Sun 3400
CPU
board include:
o
A
68030
central processor with separate internal 256 byte instruction and
data caches and an address translation cache (ATC) for
CPU
address transla-
tion. The data cache
is
designed as a write-through cache. Both the data and
instruction caches are structured
as
32 blocks
of
16 bytes each. The
68030
runs at
33
MHz.
o
A central cache configured
as
a 64 kbyte writeback cache.
o
An
1/0
cache that supports
16
byte blocks.
o
A 68882 Floating
Point
Coprocessor (FPC) running on the same 33MHz
clock as the
CPU
and enabled by the system enable register bit.
o
A
VMEbus
arbitration and diagnostic mode for
DVMA
interface testing on the
board.
o
64-bit multiplexed address/data bus memory with support for both 8MB and
32MB ECC memory boards and the
Sun-3
Floating
Point
Accelerator (FPA)
board.
o
P4
bus support that allows a variety
of
video daughter boards to be used.
o
P2
MEZZ
bus support that allows the
FP
A+ to be used.
3
Revision A
of
15
May
1989
4
Sun
3400
CPU
Board Configuration Manual
Video Daughter Boards
Configuration
of
the Jumpers
on the
3400
CPU
Board
ECC
Memory Configuration
o
Interface circuitry that supports the
VMEbus,
Ethernet, two serial ports, the
keyboard, and the mouse.
An optional feature is the Data Ciphering Protocol
(OCP)
Processor chip set. This
chip set provides additional security for your sensitive files by encrypting network data.
The Sun
3400
CPU
board will be paired with either a monochrome video daughter
board
or
one
of
three color video daughter boards. In some systems, a separate
terminal will
be
connected to one
of
the serial ports
on
the rear edge
of
the
3400
CPU
board.
In
other systems, a monitor will operate from a separate color or
graphics board.
Table 1 on the following page shows the factory configuration
of
the
jumper-blocks on the Sun
3400
CPU
board.
Each board has grid markings that form an
X-Y
coordinate system. Letters
of
the alphabet define the X coordinate and numbers define the Y coordinate
of
the
grid. Table 1 lists the location coordinates
of
pin 1
of
each
jumper-block.
For
example, referring to Table
1,
pin 1
of
jumper-block
1100
is located at the inter-
section
of
coordinates
"L"
and
"34".
In Table
1,
the
Configuration
column indicates which pins can
be
jumpered
together and whether
or
not the board is shipped with the referenced
jumper
con-
~
nection installed on the indicated pins. For example,
"1-2"
in the Configuration
column means that a
jumper
is installed across pins 1 and
2.
"IN"
means that the
CPU
board is shipped with the
jumper
connection installed.
"OUT"
means that
the board is shipped with the
jumper
connection not installed.
Again referring to Table
1,
the
Description
column lists the effect
of
each
jumper-block when it
is
installed in the indicated position. With one exception,
when a jumper is
"IN'', a function is enabled
or
selected.
The
exception is
jumper-block
J100
which disables functions when installed.
To find pin 1 on a given jumper-block,
tum
the board
over
to the solder side and
look closely at the pins.
Pin
1
is
soldered into a square shaped pad while the
other pins are soldered into circular shaped pads.
Figures 1 and 2 show where
jumper-blocks
are located on the
Sun 3400
CPU
board.
When the
Sun 3400
CPU
board is shipped with the 8MB
or
the 32MB
ECC
memory board installed, no reconfiguration
of
the
Sun 3400
CPU
board
or
the
ECC
memory board is required. However,
if
you install another memory board, you
will need to configure that memory board at the time
of
installation.
Revision A
of
15
May 1989
Jumper
J100
J100
J200
J200
J200
J200
J400
J400
J400
J400
J400
J400
J400
J400
J2000
J2000
J2000
J2000
J2100
J2100
J2501
J2501
J2501
J2501
Chapter 1 - General Description and Configuration
5
To configure the 8MB memory board refer to the
Sun
501-1102
Memory Board
Con.figuration Procedure, PIN
813-2018.
For information on configuring the 23MB memory board, please refer to the
Ins-
tallation Notes
for
the 32 Mbyte Memory Board,
PIN
800--2123.
Table
1-1
Factory Con.figuration
of
Jumpers on the
3400
CPU
Board
Jumper
Configuration
Location Configuration Description
L-34
1-2,
OUT
Enable
cache on 68030
(IN=
Disable
...
)
L-34
3-4,
OUT
Enable
MM
U
on
68030
(IN
=
Disable
...
)
F-17
1-2,
IN
Enable 68030 clock
F-17
3-4,
OUT
Null
F-17
5-6,
OUT
Null
F-17
7-8,
IN
Enable
SOns
clock
H-31
1-2,
IN
VME Interrupt Level 1
H-31
3-4,
IN
VM
E Interrupt Level 2
H-31
5-6,
IN
VM
E Interrupt Level
3
H-31
7-8,
IN
VME Interrupt Level
4
H-31
9-10,
IN
VME Interrupt Level
5
H-31 11-12,
IN
VME Interrupt Level
6
H-31 13-14,
IN
VME Interrupt Level
7
H-31 15-16, OUT
Null
M-19
1-2,
OUT
Disable
VM
E Requestor
M-19
3-4,
IN
Enable
VM
E Arbiter
M-19
5-6,
OUT
Disable
VME-generated
VME
reset
M-19
7-8,
IN
CPU-generated VME
reset
N-19
1-2,
IN
Enable
VM
E Sys Clock
N-19
3-4,
OUT
Reserved
A-18
1-2,
IN
Enable
Ethernet
Clock
A-18
3-4,
OUT
Null
A-18
5-6,
OUT
Ethernet
Level
2
(IN
=
Level
1)
A-18
7-8,
OUT
Null
Revision A
of
15
May
1989
6 Sun 3400 CPU Board Configuration Manual
Figure
1-1
Section
A-Hof
the Board
A
B c D E
F G H
a=._______..------.
D D
i
c::==:J
01
10
I
I=====
=====
c===:J
======~--~
~
C==:J
DI
I 0 I I
t:=I
====::=:;
I I
C==:J
E::3
.___ _ ___,
~----'
~--~
F-17, J200
1-2 IN, Enable 68030 clock
I
I'
I
.___I
-
3-4 OUT, Null
~
D
5-6 OUT, Null
~
7-8
IN,
Enable 50ns clock
~~~~~~~~~~~~~~~~~~~·~
·---]
I
A-18, J2501
1-2
IN,
Enable Ethernet Clock
3-4 OUT, Null
5-6 OUT, Ethernet Level 2
c==J
~1 -~
..____
__
__.~-~
.___ _ __.
7-8 OUT, Null
------+--+-..,.,.;]:i
c=J
~-~
~--~'----~
~-~
G-24,DCPPAL
~~~~~-r--tr=;-t--~~~~-t-::========:---;::====::::;--r====~-:::-:::::i
__
~
C-32,
ID
PROM
H-31,J400
1-2
IN,
VME lntrupt Lev 1
3-4 IN, VME lntrupt Lev 2
5-6
IN,
VME lntrupt Lev 3
7-8 IN, VME lntrupt Lev 4
9-10
IN,
VME lntrupt Lev 5
11-12
IN,
VME lntrupt Lev 6
13-14
IN,
VME lntrupt Lev7
15-16 OUT, NULL
Revision A
of
15
May 1989
)
Chapter 1 -
General
Description
and
Configuration
7
Section
1-0
of
the
Board
Figure 1-2
.----~
:=E~==::::t--
N-19, J2000
1-2
OUT, Disable
VM E Request
3-4
IN,
Enable
VME Arbiter
5-6 OUT, Disable
VME-generate
VME reset
7-8 IN, Enable
VME-generated
CPU
reset
_
__..
...._____._--+'rtt--------+----
N-19,
J2100
~-~
~-~
I I
L-1
---''-t----t-'
~-~
~-~'
c=:J
'-------'m:::::::::~
I
1c=JJ
c=:J
I
I
c=:J
I
I
c=:Ji
I I
c=:JI
I
I
c=:Jl
Ii
c=JJ
II
~-~c=J
I
I
I
I
I
I
c=:J
I
~~c=J
~~
c=:J
I
I
c::==J
c::==J
c::==J
I
c::==J c::==J
I
11
II
.-------.~I~
:~11~11
lc::::=J
I
I
I
c::::=J
I
I
lc::==J
I
lc=J
I
I
-
I
n
I
I
I
I
I
n
I
I
I
'D
I
I
I
I
":·:·
I
I
ID
00111111
~
~
~
1-2
IN, Enable
VME
Sys Clock
3-4 OUT,
Reserved
L-34,
J100
1-2
OUT, Enable 68030
cache
3-4
OUT, Enable 68030 MMU
Revision A
of
15
May
1989
(
(
Revision History
Revision Dash Date
Comments
Number
01
01
11
April 1988 Alpha Review Draft
02
02
3 October 1988
Second Review Draft.
so
03
14
November 1988 Beta Review and Engineering Release.
so
04
23
January 1989 Review Draft.
)
50
05
29
January 1989 Beta Draft
A 10
17
April 1989
Released for customer shipment
A
11
15
May 1989
FCS
Revision A
of
15
May
1989
(
(
)
Typographical
Errors
)
Technical
Errors
)
SUN
3400
CPU
Board Configuration
Manual Reader Comment Sheet
Dear Reader,
We who work at
Sun Microsystems wish to provide the best possible documenta-
tion for our products. To this end, we solicit
your comments
on
the Sun
3400
CPU
Configuration Manual,
Part
Number 813-2055-11.
We
would appreciate
your critique
of
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if
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of
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or
feel that
pertinent
infoimation
has been omitted.
Please list typographical errors by page number and exactly duplicate the actual
characters when recording and reporting such errors.
Please
list errors
of
fact or technical accuracy by page number
ClJ1d
(}1J0t~
~rrone-
ous passages verbatim.
· · · · · ·
Revision A
of
15
May
1989
Content
Layout
and
Style
SUN 3400 CPU Board Configuration Manual Reader Comment Sheet
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May 1989
(
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