Sundance Spas SMT301A User Manual

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SMT301A

VXI 8 SLOT MOTHERBOARD

User Guide

SU MUTSS TG MT

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Disclaimer

Every effort has been made to ensure the accuracy of this document, however the manufacturer cannot accept responsibility for any loss or damagecausedas a result of usingthis document.

Notice of any mistakes, inconsistencies or comments relating to this document would be gratefullyreceived by fax to Sundance.

Fax No.: +44 (0)1494 793168 All right s reserved. No part of this

document may be reproduced, in any form. or by any means, without the written permission of Sundance.

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TABLE OF CONTENTS

1. Features 2

2. Architectural Overview 3

3. Global Bus Resources 4

4. VXI Interface 6

5. VXI Interface Registers 7

6. Control and Status Registers 10

7. Dual Port RAM (DPR) 14

8. JTAG Debugging Logic 15

9. Comm-port Interface 18

10. Reset Board Register 19

11. ‘C4x Memory Map 20

12. Communications Ports 21

13. TIM Sites 24

14. FIFO and High Speed Interface 25

15. Circuit / Schematic Description 27

16. Physical Characteristics 42

17. References 44

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1 Features

Eightslot TIM motherboard

Flexible communications port linking

All 8 front panel comm-ports fully buffered

Doublepipe architecture- comm-portsunbuffered

Global board resources

1MByteof one-wait-state SRAM accessible by TIM sites or VXI

Memoryexpansion by daughter module (can be zero-wait-state)

On board JTAG debugging circuit - accessed from VXI

On board comm-port interface to VXI

High speed HewlettPackard‘Local Bus’ interface via 32x 2KBytein and out FIFO (100MBytes/s)

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2 Architectural Overview

This description should be read with reference to the diagram titled ‘VXI Motherboard Architecture’. Note thatthe layoutof TIM sites on the board,is in the same order as shown in the diagram.

VXI VME

interrupt

High speed bus i/face

RAM expansion connection

FIFO Bus

RAM Bus

buffer

Arbiter

& buffer

control

41 1

TIM

Slot

TIM

Slot

124

Global Bus 2

320

TIM Slot

TIM

Slot

2145

'C40 link

i/face

JTAG

1MByte

VME address decode

byte swap buffers

RAM

Bi-FIFO

IIOF0 (site 1) IIOF0 (site 5)

link

switch

TDI

TDO

JTAG decode RAM decode link decode

Figure1: VXI MotherboardArchitecture

TIM Slot

4412

053

0053

TIM

Slot

TIM

Slot

link

patch

headers

buffer

TDI

TDO

Front Panel Links

Front Panel JTAG

In and

Out

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3 Global Bus Resources

There are two main global bus resources available on this motherboard. These are thebi-directional FIFOwithitsHewlett Packard‘LocalBus’interfaceandthestatic Dual Port RAM (DPR). Mutually exclusive access to these resources can be made by either of the TIM sites which have a global bus connector (the two nearest the VXI connectors, sites 1 and 5). TIM A can access the FIFO at the sametime as TIM B is accessing the DPR (or vice-versa). A VXI bus master can also access the on board DPR at the same time as a TIM is accessing the FIFO.

The DPR is organised to allow the VXI to perform D8, D16 or D32 cycles, byte swapping buffers are included for this purpose. The DPR access time is 20ns, and the TIMs areconnectedto this DPR through fast (approximately5ns)buffers.This allows ‘C4x accesses to be performed with one- wait -state. The DPR is decoded at TIM addresses0xDF000000 and upward (on ‘C4x STRB1). Extra memory can be added using the DPR expansion site. TIM access to this DPR can be zero- waitstateif 12ns devices are used.

The bi-directional FIFO consists of two separate FIFOs, one for incoming and one for outgoing data. The FIFOs can operate concurrently, although the Hewlett Packard interfaceis not full duplex.

Access to the global resources is selected by arbitration state machines. Two arbiters are present, one controlling access to the FIFO, and the other accesses to the RAM and VXI bus and board control registers. The relevant resource is left granted to the lastresource masterafter the cyclehasfinished.Arbitrationonlyoccurs when two (or more) possible bus masters are requesting the same resource. Arbitration takestwo ‘C4x cycles.

The other Global Bus Resources are VXI bus master access and the board control registers. Because VXI bus arbitration and Global Bus Resource arbitration are separate,adeadlock situation canoccur.Thisdeadlockisonlypossiblewhena TIM starts a VXI bus master cycle around the same time that another VXI bus master starts a cycle to access the SMT301. This situation is resolved by signaling ‘Bus Error’ to the existing VXI bus master, which is forced to abortits’ VXI bus cycle. Thiscyclemay be re-triedaftera shortdelay(a few microseconds)toallowthe TIM VXI cycle to complete. This possibility must be taken into account when designing system software.

3.1 ‘C4x Comm-port

The ‘C4x VXI interface, is designed to allow the VXI to perform D16 or D32 cycles, to access the comm-port interface register. These accesses are converted to the correct protocol for communicating via a ‘C4x comm-port. This logic and associatedcircuitryincludesdoublebufferingonreads and writesnegatingtheneed

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for an external FIFO. The comm-port which is connected to this interface can be switched to either of the two TIMs which have global access (TIM1 or TIM5).

A full duplex comm-portpipeline is hardwiredbetween all of the TIMs, withTIM sites 1 and 5 as the pipeline ends. Thesecomm-ports are unbuffered for maximum speed.All other TIM comm-ports are routed unbufferedto a link patch area,as are the 8 buffered front panel comm-ports.

3.2 JTAG

A Texas InstrumentsTest Bus Controller (TBC) is used to control the JTAG daisy chain between TIMs. This device is accessed from the VXI as a D16 operation only.

3.3 Interrupts

A single FPGA interrupt controller coordinates all interrupts. It contains a status register showing unmasked interrupt sources, and 3 mask registers. These allow the interrupt sources to be masked, before they are logically ORed, to generate 3 separate interrupt inputs, one for each of the global TIM sites and one for the VXI bus.

A VXI interrupt, with programmablelevel,can be generatedbyeitherglobal access TIM. From each of these TIMs, the IIOF0 signal is connected to the interrupt FPGA, and the assertion of this line generates the interrupt if it is unmasked. The interrupt is cleared by the VXI master, when it masks the source of the interrupt.

The FIFO flags appear as interrupt sources for all three interrupt receivers. The Global TIM sites have VXI bus error as an interrupt source. The VXI bus also has the JTAG controllerand the TIM IIOF0 outputs as interrupt sources.

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4 VXI Interface

The VXI interfaceusestheP1 connectorandthecentrerowof the P2 connectorfor additional date and address lines. The interface forms a complete D8/16/32 master/slave. The card does not support slot 0 operation, block transfers or unaligned transfers.

4.1 VXI Slave Interface

VXI address decoding is selected by the setting of the VXI base address configuration register. The base address in VXI A32 space of the DPR is separate to the JTAGand Link Interfaceand Control registers, (see nextsection).

Anyexpansion DPR fittedappears in the VXI memory map abovetheDPRalready presenton theboard. All of these DPR areasareaccessiblebytheVXI masteratthe same speed as theTIM sites.

4.2 VXI Master Interface

The card can support D8, D16 and D32 transfers in A16, A24 and A32 address spaces. The TIM global data bus signalsdrivethe VXI data bus through buffersbut no byte or word swapping is performed. That is a D8 transfer to VXI address 0x0000 would need the significant data to be in the ‘C4x data bits 7..0. A D8 transfertoaddress 0x0001wouldneedthesignificantdata to be in the‘C4xdatabits

15..8.etc. No support is provided for accessing words or longwords across longword

boundaries.i.e.,all transfersmust be within longword boundaries. The ‘C4x address lines A0..A21 drive the VXI address lines A2..23. The VXI DS

signals and the VXI address bits A1, A24-31, AM0-5, LWORD are set by the contents of Control register 4. This requires the use of a 4M Word ‘C4x address regionfor VXI master access.

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5 VXI Interface Registers

The VXI specification defines a register block within A16 address space which is used for control, status and board set-up. These registersare shown below:

Offset Registerdescription

00 ID register 02 04 06 08

0A - 1D Sub-class dependent registers (unused)

20 - 3F

The address of this register block is defined by an 8-bit DIL switch (LK1). They are accessed in A16 address space. The top two address lines (A14 and A15) must be ‘1’. The base address (set on the switches) is compared to address bits A6 to A13. The address bits A1 to A5 select which register to access. Switch1 corresponds to A13 and switch 8 to A6. The switch must be set to ‘ON’ for the corresponding address bit to be recognised as 0.

Device type Status / Control DPR Offset Sub-class Offset register

Sub-class register Sub-class dependent registers (unused)

Switch VXI AddressBit

1 A13 2 A12 3 A11 4 A10 5A9 6A8 7A7 8A6

For example: Address 0xC000 = All on. Address 0xD000 = All on except switch 2

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Address 0xF800 = All on except switches1,2,3. Address 0xFFC0 = All off.

The VXI address modifiers must be set to 0x29 or 0x2D as these define an A16 transfer.

5.1 VXI ID Register (00)

The bit definitionsfor this register are:

Bit Definition

11..0

13..12

15..14

Manufacturer ID (set to 123 decimal Address spaces 01 - A16/A32 Device classes 01 - extended (SMT301 is extended)

Alwaysreadsas 507B hex.

5.2 VXI Device Type Register (02)

The bit definitionsfor this register are:

Bit Definition

11..0

15..12

Model code (set to 301 decimal) Required memory ‘m’ = 0 to 15

With 1MByte of SRAM,alwaysreadsas B12D hex.

5.3 VXI Status Register (04)

The bit definitionsfor the read onlystatusregister are:

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Bit Definition

0..1 2 3 4

5 .. 13 Device dependent ( not used)

14 15

Device dependent ( not used) Passed self tests (always asserted) Ready (connected to TIM CONFIG line) TIM config (normally read as C00C Hex)

- MOD ID line status (inverted MOD ID) A32 active

5.4 VXI Control Register (04)

The bit definitionsfor the write only control register are:

Bit Definition

0 1

14..2 15

Reset (set to reset whole SMT301) Sysfail inhibit(sysfail not implemented) Device dependent (not used) A32 enable

A32 enable MUST be set to allow A32 access to the rest of the board.

5.5 VXI DPR Offset Register (06)

This 16-bit register defines the base address of the DPR (and DPR expansion) for A32 addressing modes. In A32 mode, all ‘m’ bits are compared to VXI address signals A16..31. The number of significant bits is ‘m’, and is specified in the ‘Device Type’ register.

5.6 VXI Sub-class Offset Register (08)

This16-bitregister is usedtoset the base address(in256 byte blocks)of the ‘Other Peripherals’ (JTAG, Link interface, control register etc.). This base address is compared to the incoming A32 address bits 8-23, while bits 24-31are compared to FF hex. A match decodes a 256 byte space which is further decoded to access the ‘OtherPeripherals’.

5.7 VXI Sub-class Register (1E)

The bit definitionsfor this 16-bit read onlyregister are givenbelow:

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Bit Definition

11..0

14..12 15 0 - normal

Manufacturer ID (set to 123 decimal) Manufacturer sub-class(set to 001)

Alwaysreadsas 107B hex.

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6 Control and Status Registers

Thereare 5 controlregisters:

6.1 Control Registers 1 and 2 = TIM Site 1 and 5 Interrupt Masks

TheFIFOflagscan be programmedto producean interrupt whichgoestoTIMsites 1 and 5. The VXI bus error signal can also generatea TIM interrupt.EachTIM site has its own register which is accessible to both the VXI bus and the TIMs. The registers are the general control register 1 for TIM site 1, and general control register 2 for TIM site 5. Note that ‘VXI Bus Error’ is latched by either of thebit 8 masks below. Therefore both must be cleared to unlatch ‘VXI Bus Error’.

Bit Function

8 7 6 5 4 3 2 FIFO in almost full 1 0

VXI bus error FIFO out full FIFO out almost full FIFO out almost empty FIFO out empty FIFO in full

FIFO in almost empty FIFO in empty

General Control Register 1 (TIM1)

Bit Function

8 7 6 5 4 FIFO out empty 3 2 1 0

VXI bus error FIFO out full FIFO out almost full FIFO out almost empty

FIFO in full FIFO in almost full FIFO in almost empty FIFO in empty

General ControlRegister 2 (TIM 5)

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6.2 Control Register 3 = VXI Interrupt Masks

Each of the two TIM sites 1 and 5 can cause an interrupt to the VXI system. The interrupt level is selected by bits 12 ..10 of Control Register 4.. In addition to the IIOF0 lines causing a VXI interrupt, the FIFO flags can also generate a VXI interrupt.

Thesecan be enabled within the general control register3 bits, describedbelow.

Bit Function

9 TIM 1 IIOF0 8 7 6 5 4 3 2 1 0 FIFO in empty

General ControlRegister 3

TIM 5 IIOF0

JTAG FIFO out full FIFO out almost full FIFO out almost empty FIFO out empty FIFO in full FIFO in almost full FIFO in almost empty

6.3 Control Register 4 = VXI Bus Master cycle control

This 32-bit control register is defined as the general control register 4, and the function is described below;

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Bit Function

24 - 31 18 - 23

17 16 15 Link interface switch control (0 = TIM site 1, 1 = TIM site 5) 14 13 12 11 10 VXI bus interrupt level request bit 0

9 8

0-7

VXI address lines A24 to A31 during ‘C4x master cycle Address modifier codes AM0 to AM5 during ‘C4x master cycle VXI LWORD during ‘C4x master cycle VXI A1 during ‘C4x master cycle

VXI bus request level bit 1 VXI bus request level bit 0 VXI bus interrupt level request bit 2 VXI bus interrupt level request bit 1

VXI DS1 during ‘C4x master cycle VXI DS0 during ‘C4x master cycle VXI bus interrupt acknowledge vector

General ControlRegister 4

If no response from the addressed slave is observed within a fixed time (time-out period) then the VXI Slot 0 controller will generate a ‘Bus Error’, the ‘C4x cycle will be terminatedand a VXI Bus Errorinterrupt generated.

6.4 Control Register 5 = General Status Register

A statusregisterisavailableforaccess by the TIMsandtheVXI.Thebitdefinitions are shown below;

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Bit Function

9 8 7 6 FIFO out almost full 5 4 3 2 1 FIFO in almost empty 0

TIM 5 IIOF0 TIM 1 IIOF0 VXI Bus Error (Latched) FIFO out full

FIFO out almost empty FIFO out empty FIFO n full FIFO in almost full

FIFO in empty

General ControlRegister 5

NOTE: The FIFO flags are only valid while the FIFOs receive a read/write clock. This is

either provided by a TIM or by the SMT301 itself when no TIM is granted access to the FIFO bus. During arbitration, this clock may be absent for a maximum of 100ns,duringwhichtime the FIFOflagswill not be updated.

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7 Dual Port RAM (DPR)

The DPR is composedof 1MByte SRAM. This can be accessedasD8, D16 or D32 via the VXI data bus. It can only be accessed in the A32 address space. The base address of this memoryissetbytheVXIoffsetregister, andit resides on a 1MByte boundary.

7.1 DPR Expansion

Memory expansion is provided for by the inclusion of a memory expansion daughter module socket. The memory(or peripheral) associatedwith this daughter module can be up to 512MBytes (using DRAMs) and appears in the VXI address space directly after the 1MByte DPR. This expanded memory option will run at zero-wait-states,when fitted with very highspeedSRAM (12ns or faster).

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8 JTAG Debugging Logic

This device is an SN74ACT8990 Test Bus Controller (TBC). It can only be accessed with a D16 cycle from the VXI host. The address range for access to this deviceisfromthebaseaddress (specifiedin the VXI sub class offsetregister)to the baseaddress+ 0x7F. The following registersare held in of the TBC:

JTAGIN

TBC

JTAGOUT

TDI

TDO

TDI

TDO

TDI

TDO

T C H

S W

I T C H

TDI

TIM SITES

TDO

TDI TDO

Figure2: Routingof TDO and TDI Signals

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Address Register Read/Write

base + 02h base + 06h

base + 0Ah

base + 0Eh base + 12h JTAG Control 4 R/W base + 16h

base + 1Ah

base + 1Eh base + 22h base + 26h JTAG Control 9 R/W

base + 2Ah

base + 2Eh base + 32h base + 36h

base + 3Ah

base + 3Eh base + 42h base + 46h

base + 4Ah JTAG status 2 R

base + 4Eh base + 52h base + 56h base+ 5Ah base + 5Eh J TAG Write Buffer W

JTAG Control 0 JTAG Control 1 JTAG Control 2 JTAG Control 3

JTAG Control 5 JTAG Control 6 JTAG Control 7 JTAG Control 8

JTAG Minor Command JTAG Major Command JTAG counter 1 Update 0 JTAG counter 1 Update 1 JTAG counter 2 Update 0 JTAG counter 2 Update 1 JTAG status 0 JTAG status 1

JTAG status 3 JTAG Capture 0 JTAG Capture 1 JTAG Read Buffer

R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W

R R

R R R R

The Test Bus Controller is capableof drivingtheJTAGscanchainthrough all TIM modules. If a module is not present then the modules SENSE signal is used to enable (or disable) a tri-state buffer inserted in the TDO/TDI (JTAG Data In and Data Out) scan chain. An FCT2244 type device is used which allows for the chain to function correctly with only one module site occupied. Each buffer has a propagation delay of 5ns maximum, which can limit the maximum JTAG clock frequency. The internalJTAG clockis 5MHz, which is slow enough to support the delay around a board with a single TIM fitted. External JTAG controllers should also use 5MHz maximum clock frequency.

Two connectors are present on the front panel. One is the scan chain out, and the other is the scan chain in. If anothermotherboard is connected to the scan chain in

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(JTAG IN), or a TI debugger,then the TBC on thismotherboard must be disabled. This is automatically done by a dedicated pin on the JTAG IN connector which forces the TDI signal for the first TIM site to be derived from this JTAG IN connector rather than the on board TBC. Similarly,if the JTAG OUT connectoris connected to another motherboard’s JTAG IN connector, then the TDO signal returned to both the on board TBC and the JTAG IN connector, will be derived from the JTAG OUT connector.

This diagram shows the routing of the TDO and TDI signals. The top selector is controlled by the presence of the JTAG OUT connector, and the lower selector is controlled by the JTAG IN connector. If another JTAG controller is plugged into the JTAG IN socket, TDI1 into the local TBC is pulled low so that software can determine if the TBC isthe local JTAG controlleror not.

The JTAG IN connector (J34) has the following signals: TDI, TDO,

JTOUT_DET. The JTOUT_DET signal is pulled up on the motherboard, and if a JTAG OUT from one motherboard is connected to the JTAG IN then a corresponding GND pin on the JTAG OUT connectorwill pull JTOUT_DET low, to signaltheTBC as describedabove.Thisconnectoralsocontainsa and the config signal (both of which may be disabledby removing a jumper).

These details can all be found in the table in the section describing the JTAGfront panelconnections.

The JTAG OUT connector (J35) has the followingsignals: TDI, TDO, The SENSE line is pulled down on the motherboard, and thus if the JTAG OUT is

connected to another motherboard’s JTAG IN then the SENSE line is pulled high by the connection to PD(+5v). This configures the other selector as described above. This connector also contains a outputs and inputs from and to the JTAG IN and OUT connectors are passed through buffers, exceptCONFIG which is a global open collector signal. Both the JTAG in and out connectors are 3M 20-way SCSI 2 type, part number 10220-52 12 J L .

These details can be found in the table in the section describ in g the JTAG front panelconnec ti on s.

TRST, TMS, TCK, TCK_RET, EMU0, EMU1, GND, PD(+5v),

reset_in signal

TRST,TMS, TCK, TCK_RET, EMU0, EMU1, GND, SENSE.

reset_out signal and the config signal. All

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9 Comm-port Interface

This interface provides a route by whicha VXI host can talk to a ‘C4x comm-port. Both D16 and D32 accesses are allowed. The following address / register map is used:

Address Register Data Bits Read/Write

base + 80h base + 84h base + 90h comm-port data register 15-O R

There is only one comm-port interface, and its data register is accessible at both addresses indicated in the table above.

The comm-port data register is accessible as a D16 resource by first writing the upper data bits (31 to 16) to address base + 84h and then the lower data bits to address base + 86h. This register, when read, contains the last word to be received from the ‘C4x comm-port. Writing to this register causes a word to be sent to the ‘C4x comm-port. The receive and transmit sections of this register are separate.

The status register is accessible by the VXI host as D16 at address base + 92h or in D32 at address base + 90h. The bit definition is as follows:

comm-port data register comm-port data register

31-O R/W 31-O R/W

Bit Function

9 10 11

receive data available transmit register empty receive data available transmit register empty

The receive data available bit becomes set when a receive word is in the link data register. When the link data registeris read, this bit is reset.

When the transmitregister empty bit is set, it indicates that the VXI host can write a new word to the comm-port data register for later transmission to the ‘C4x comm-port.

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10 Reset Board Register

This special control register is accessedin A32 space as either D16 or D32. When accessed as D16 it uses addressbase+ C2h, and when using D32 at address base + C0h. Only bit-4 is defined, and if this bit is set by the VXI host, it causes all TIM sites, comm-port buffers, and other motherboard logic to become reset. The board remainsin such a stateuntilthis bit is clearedby theVXI host.Thisresetisthesame bit as defined in VXI control registerbit-0.

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11 ‘C4x Memory Map

The C4x (TIM sites 1 or 5) haveaccessto the Dual Port RAM, FIFO data register, general control register, general status register and VXI space. The addresses used are given in the table below:

Address Resource Read/Write

C0000000 C0000001 C0000002 general control register 3 write C0000003 C0000004

C3800000-C3FFFFFF

C1000000-C1FFFFFF C3000000-C37FFFFF

DFFC0000-DFFFFFFF

E0000000-FFFFFFFF

general control register 1 write general control register 2 write

general control register 4 write general status register read high speed interface device control and

status (see high speed interface control) VXI address space read/write FIFO data register read/write 256K word dual port RAM read/write 512M word DPR expansion read/write

read/write

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12 Communications Ports

The TMS320C4x processor has up to 6 byte-wide communications ports. In the case of the ‘C40, upon a reset 3 of these comm-ports are in output mode and the other3areininputmode. Similarlythe8 front-panelcomm-portbuffersaredivided so that 4 reset to input and 4 reset to output.

From the architectural diagram, the TIM sites (1 to 8) have six numbered comm-ports.Ports0 to 2 are reset to output,andports3to 5 are resettoinput.Some of the comm-ports from each site are used to form a double pipe, and the spare comm-ports are routed to the link patch headers.

12.1 Link Patch Headers

The link patch headers are 14-way surface-mount FMS connectors, located on the rear of theboard as close as possible to the respectiveTIM site. There are a total of 26 FMS connectors, 8 connect to the front panel link buffers, and 18 for thespare portsfromtheTIMsites.They are arrangedaroundarectanglewiththecentreclear ofcomponents,to allowclearanceforflatcables.Allsignalsto theseconnectorsare pulled up to +5 volts with 10K resistors, this gives connected signals an effective pull up of 5K ohms. Series damping resistors of 27 ohms are also used on every signalline to reduce ringing effects.Testshave shown that 200mmlong flat cables provide a reliable connection, and allow most connections between the FMS connectors to be made. For further details see Section 15: Patch Area Connector Layout. The FMS connectorpinoutis:

FMS Pin Signal

1 GND 2D0 3D1 4D2 5D3 6D4 7D5 8D6

9D7 10 REQ 11 ACK 12 STRB 13 RDY 14 GND

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12.2 Front Panel Comm-Ports

From the link patch headers, 8 comm-ports are taken to front panel mounted connectors via buffers, constructed from FCT245AT type devices with 64mA pull-downability,and undershootclamp diodesonallsignals.Allsignalsarepulled up to +3 volts with 100 ohm resistors. The active devices are mounted as close as possible to the connectorthey serve,and always within 50 mm of the connector.

The front panel comms ports use 26 pin 3M connectors, (part number 10226-52 12 J L ).The connecto rpin-outis given in the followingtable.

Pin Twisted pair Signal

1 1 STRB 2 1 GND 3 2 RDY 4 2 GND 5 3 REQ 6 3 GND 7 4 ACK 8 4 GND

9 5 DIR_OUT 10 5 GND 11 6 DIR_IN 12 6 GND 13 7 D0 14 7 D1 15 8 D2 16 8 D3 17 9 D4 18 9 D5 19 10 D6 20 10 D7 21 11 VCC 22 11 GND 23 12 /RESET_OUT 24 12 GND 25 13 SPARE 26 13 GND

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Pin Twisted pair Signal

SHELL - SHIELD

The overall shield is clamped to the metal shell of the plug. RESET_OUT is an activelow open collectoroutputcopiedfrom the main boardresetsignal.

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13 TIM Sites

There are 8 TIM sites numbered 1 to 8. Sites 1 and 5 have the optional global connector to allow TIM access to the DPR and FIFO.

13.1 TIM Connector Pin-Out

The global connectorcontains the full ‘C4x global bus signals. For accesses by the ‘C4x to the global bus, the most significant address bit, A31 is a ‘1’. This bit is not an outputpin but used internally to the ‘C4x. The global connector doesnot contain any power or groundsignals.

The bottom, or secondary, connector is used only for comm-ports, power and user definable connections (UDP 7 to 12). The user-definable pins are not implemented on this motherboard.Comm-ports 1, 2, 4 and 5 are on thisconnector.

The top, or primary,connector is used for the remainingtwo comm-ports(0 and3), power,interrupts, ‘C4xcontroland JTAG.Bothplusandminus 12v are supplied by the motherboard to these top connectors. The JTAG signals are derived from the JTAG control logic on the motherboard, or from an external source (see JTAG section). An external clock is supplied to all TIM sites. This clock is currently 50MHz, and MUST be used by TIMs in sites 1 and 5 if they are to perform any external accesses via their Global TIM connector. Similarly, TIMs in sites 1 and 5 must provide both H1 and H3 clock outputs to the SMT301 if they are to perform any global accesses.

Refer to the TIM-40 Module Specification from Texas Instruments for exact connector placement. Adjacent TIM sites must be separated by exactly 2.6".

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14 FIFO and High Speed Interface

14.1 High Speed Interface Control and Status

A 32-bit port is provided that allows either global TIM site access to the Hewlett Packard Local Bus Interface:

A high speed Hewlett Packard ECL ‘Local Bus’ interface is carried on the outer rowsof P2, and isconnected to a custom ECL interfacedevice suppliedby Hewlett Packard. This deviceis known as ‘Ballistic’. The P2 connector is shielded, and the boardlayoutand terminators of the ECL device, are as closeas possibleto Hewlett Packard recommendations.

Connected between the ‘Ballistic’ and the TIM global buses is a 2048 by 32-bit bi-directional FIFO. The maximum data rate on the ‘Local Bus’, using this high-speedchip,is100MBytes/s(unidirectional),whichequatesto 25M words/s(4 bytes are packed into a single 32-bit word within this device). The maximum data rate at the ‘C4x side is also 25MWords/s if 50MHz ‘C4xs are used. This data rate applies for ‘C4x read cycles, a lower data rate of 12.5MWords/s must be used for writesdue to the extra cycle a ‘C4x needs to perform a write.

The flags from the FIFOs are available for the TIM sites 1 and 5 to read from a general status register. Additionally these flags can be programmed to cause an interrupt by the TIMs writing to a general control register.

Data

Bit

0 TRG0 1 TRG1 2 TRG2 3 TRG3 TTLTRG3 active low TTLTRG3 active high reset 4 TRG4 5 TRG5 6 TRG6 7 TRG7 8 EOBID0

9 EOBID1 10 EOBID2 11 EOBID3 12 FRAMEIO0 FRAMEIO0 Drives FRAMEIO0 when data is output 13 FRAMEIO1 14 FRAMEIO2 15 FRAMEIO3 16 WIDTHIO0

Signal Read Description Write Description

TTLTRG0 active low TTLTRG0 active high reset TTLTRG1 active low TTLTRG1 active high reset TTLTRG2 active low TTLTRG2 active high reset

TTLTRG4 active low TTLTRG4 active high reset TTLTRG5 active low TTLTRG5 active high reset TTLTRG6 active low TTLTRG6 active high reset TTLTRG7 active low TTLTRG7 active high reset EOBID0 Drives EOBID0 when data is output EOBID1 Drives EOBID1 when data is output EOBID2 Drives EOBID2 when data is output EOBID3 Drives EOBID3 when data is output

FRAMEIO1 Drives FRAMEIO1 when data is output FRAMEIO2 Drives FRAMEIO2 when data is output FRAMEIO3 Drives FRAMEIO3 when data is output WIDTHIO0 Drives WIDTHIO0 when data is output

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17 WIDTHIO1 18 CONT 19 FLUSH 20 INVEPACK 21 MODE0 - MODE0,reset 22 MODE1 23 MODE2 24 MODE3 25 PACK 26 PACKIN1 - PACKIN1, reset 27 PACKIN0 28 STRIP 29 FLPBK 30 VXSP1 31 VXSP2

WIDTHIO1 Drives WIDTHIO1when data is output

- CONT, reset

- FLUSH, reset

- INVEPACK, reset

- MODE1, reset

- MODE2, reset

- MODE3, reset

- PACK, reset

- PACKIN0, reset

- STRIP, reset

- FLPBK, reset, FIFO loopback when set

- VXSP1, reset, spare 1

- VXSP2, reset, spare 2

General Control Register Table

Note: ‘reset’ means the holding latch is cleared to 0 by a board reset. ‘FLPBK’ is used for testing only.

VXSPI1and2Operation

VXSP2 VXSP1

00 01 10 11

Normal: Auto Restart on pause Software reset of Ballistic device Hold on Pause Force 1 Restart

This means a boardresetwill result in ‘pipemode’functioning normally.

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15 Circuit / Schematic Description

15.1 Schematic Sheet Titles

Sheet Title Description

Hewlett Packard Interface J2(VXIP2), ICI-5/10-17, R1-11/171-172 LED1-2

1 2 VXI Interface J1(VXIP1)/37(DIN30W0, IC18-31/218-219,

Static RAM J3-4, IC4x-47, R15-17/173-174

‘C4x Link Interface C48-61,R18-27

Global TIM Site 1 J5, IC62-76, R28-44

5 6 Comms TIM Site 1 J6-7, IC77-92, R45-55

Comms TIM Site 2 J8-9, IC93-103, R56-62

Comms TIM Site 3 J36/10, IC104-114, R63-69

Comms TIM Site 4 J11-12, IC115-125, R70-76

Global TIM Site 5 J13,IC126-140, R77-93

10 11 Comms TIM Site 5 J14-15, IC141-156, R94-104

Comms TIM Site 6 J16-17, IC157-167, R105-111

Comms TIM Site 7 J18-19, IC168-178, R112-118

Comms TIM Site 8 J20-21, IC179-189, R119-125

FP Comms Buff 1&2 J28-29/51-52, R66-69/231/360-383,F1, C123-126,

JTAG J34-35, IC190-198, R132-146/218-227

VXI Control IC199-204/220-221, C4-112

VXI Slaves J38,IC205-217,

19 FP Comms Buff 3&4 J30-31/53-54, R70-73/540-563,IC115-125

FP Comms Buff 5&6 J32-33/55-56, R115-118/564-587, IC168-178

FP Comms Buff 7&8 J57-60, R122-125, IC179-189

R12-14/160

IC104-114

R147-159/161-170/175-183,C1-2/113,LK1

Schematic SheetTitles

15.2 VXI Slave Registers in Short VXI Address Space.

VXI A6-13 are decoded by IC215 on sheet 18 (QS74FCT2521CTQ) which compares them to the value setin the DIL switch LK1 as follows:

LK1 01 02 03 04 05 06 07 08

VXIA 13 12 11 10 09 08 07 06

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Thecorrespondingswitch must be on fortheaddress line to be decodedas 0. IC215 generates !VXIR1 which is fed to IC208(ISPLSI1016-90LT).

VXI AM0-4 are decoded in IC207 (GAL20V8C-5LJ), which generates !VXIR2 when the address modifiers are $29 (short non-privileged access) or $2D (short supervisory access).

15.3 Control Bus Arbitration

The control bus arbitor sets !CONTIM true when it grantsthe control bus to a TIM via the DPR bus. It sets!CONVME true when the VXI bus isgranted controlof the Controlbus, this is the default state when no requests are pending. The TIMs have a higher priority than the VXI bus and are granted access as soon as any outstanding VXI slave cycles have completed,signaled by !SLVSELgoingfalse.

15.4 Programmable Logic Devices

J38 is the ISP programming port, which allows in circuit programming of all the following FPGAs:

ISP I/O NetI/O IC Type Sheet Function

SDI(IN) SD1/2 10 1016 1 VXI local bus controller

SD2/3 60 1016 4 SD3/4 202 1016 17 SD4/5 203 1016 17 SD5/6 204 1016 17 SD6/7 208 1016 18 VXI primary slave decodes SD7/8 210 1016 18 SD8/9 212 1016 18

SD9/10 209 1016 18

SD10/11 211 1016 18

‘C4x Link interface controller interrupt controller VXI buffer control VXI bus request, DPR arbitor

DPR controller VXI secondary slave decodes VXI D0-D7 registers VXI D8-D15 registers

out SD11

15.5 Communication Ports Naming Convention

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Site Cho Ch1 Ch2 Ch3 Ch4 Ch5

1 A X0 X1 R X2 B 2 C X3 B A X4 D 3 E X5 D C X6 F 4 G X7 F E X8 H 5 N X17 X16 P X15 M 6 L X14 M N X13 K 7 J X12 K L X11 I 8 H X10 I J X9 G

Channels P and R are connected to the ‘C4x-VXI link interface. Channels X0-17 arebuffered and fed to corresponding P0-17 link patchheaderchannels.P18-23 are unbuffered front panel connected channels, which are also fed to the link patch header.

15.6 Patch Header to TIM Map

TIM Link Header Reset to

1 1 J22 OUT 1 2 J23 OUT 1 4 J43 IN 2 1 J24 OUT 2 4 J44 IN 3 1 J25 OUT 3 4 J45 IN 4 1 J26 OUT 4 4 J46 IN 5 1 J42 OUT 5 2 J41 OUT 5 4 J50 IN 6 1 J40 OUT 6 4 J49 IN 7 1 J39 OUT 7 4 J48 IN 8 1 J27 OUT 8 4 J47 IN

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15.7 Control Register Bit Descriptions

The writeonlyboard controlregisterisacessibletoboththe VXI bus and the TIMs. It is split into 4 separate registers:

15.7.1

Control 1

Enables interrupt requests forTIM1 on IIOF1,located in IC202:

Bit Function

FIFO IN empty

FIFO IN almost empty

FIFO IN almost full

FIFO IN full

FIFO OUT empty

FIFO OUT almost empty

5 6 FIFO OUT almost full

FIFO OUT full

VXI BERR

Not defined

Note:A reset clears all these bits to 0.

15.7.2

Control 2

Enables interrupt requests forTIM5 on IIOF1,located in IC202:

Bit Function

FIFO IN empty

FIFO IN almost empty

1 2 FIFO IN almost full

FIFO IN full

FIFO OUT empty

FIFO OUT almost empty

FIFO OUT almost full

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FIFO OUT full

VXI BERR

Not defined

15.7.3

Control 3

Enables interrupt requests forVXI bus, located in IC202:

Bit Function

FIFO IN empty

FIFO IN almost empty

FIFO IN almost full

FIFO IN full

3 4 FIFO OUT empty

FIFO OUT almost empty

FIFO OUT almost full

FIFO OUT full

JTAG

8 9 TIM1 IIOF0

TIM5 IIOF0

15.7.4

Control 4

This write only register holds the VXI bus interrupt vector, the interrupt level, the bus request level and the other VXI address bits used when a ‘C4x drives the VXI bus. Located in IC199-201/220:

Bit Function

0-7

10 11 VXI bus interrupt request level bit 1 = DVIRS1 12

VXI bus interrupt acknowledge vector. VXI DS0 during ‘C4x master cycle = ‘C4xDS0

VXI DS1 during ‘C4x master cycle = ‘C4xDS1

VXI bus interrupt request level bit 0 = DVIRS0

VXI bus interrupt request level bit 2 = DVIRS2

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13 14 15 16 17 VXI LWORD during ‘C4x master cycle 18 19 20 21 22 VXI AM4 during ‘C4x master cycle

236

24 25 26 27 28 29 30 31 VXI A31 during ‘C4x master cycle

VXI Bus request level bit 0 = DVBRS0 VXI Bus request level bit 1 = DVBRS1 Link Select VXI A1 during ‘C4x master cycle

VXI AM0 during ‘C4x master cycle VXI AM1 during ‘C4x master cycle VXI AM2 during ‘C4x master cycle VXI AM3 during ‘C4x master cycle

VXI AM5 during ‘C4x master cycle VXI A24 during ‘C4x master cycle VXI A25 during ‘C4x master cycle VXI A26 during ‘C4x master cycle VXI A27 during ‘C4x master cycle VXI A28 during ‘C4x master cycle VXI A29 during ‘C4x master cycle VXI A30 during ‘C4h:master cycle

15.8 General Status Register.

This read only register containsthe interruptflags, located in IC202:

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Bit Function

FIFO IN empty

FIFO IN almost empty

FIFO IN almost full

FIFO IN full

3 4 FIFO OUT empty

FIFO OUT almost empty

FIFO OUT almost full

FIFO OUT full

JTAG

8 9 TIM1 IIOF0

TIM5 IIOF0

15.9 Link Status Register

This read only register containsthe ‘C4x link status bits:

Bit Function

Receive data available

Transmit register empty

9 10 Receivedata available 11

Transmit register empty

15.10 Peripheral Addressing

The VXI address of theseregisters is an offset from the valueset in theVXI Offset register:

VXI offset ‘C4x Address Peripheral

00-7F None JTAG

80 84 90 C2 E0 C0000000 Control 1 Read/Write

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None Link data register Read/Write None Link data register Read/Write None Link status register Read/Write None Reset board register Read

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VXI offset ‘C4x Address Peripheral

E4 E8

C0000001 Control 2 Read/Write C0000002 Control 3 Read/Write C0000003 Control 4 Write C0000004 Status 1 Read

Setting bit-4 of the Reset board register generates a continuous reset.

15.11 ‘C4x I/O Address Map

‘C4x I/O ‘C4x Address I/O Description

GCR C0000000..C0FFFFFF

VXI C1000000..C1FFFFFF

FIF C3000000..C37FFFFF FIFO data register

VXI C3800000..C3FFFFFF

J4 DF000000..DFFFFFFF J3 E0000000..EFFFFFFF

General control registers VXI address space

VXI ECL interface 256K word dual port RAM 512M word DPR expansion

15.12 Summary of VXI Address Map

There are 3 seperate VXI block decodes:

Decode VME 32-bit Address VME Address

VXI1

VXI2

VXI3

$nnnnnnnn nnnnnnnn 11aaaaaa aaxxxxxx

$bbbbbbbb bbbbyyyy yyyyyyyy yyyyyyyy

$11111111 cccccccc cccccccc zzzzzzzz

Space

A16 64B VXI interface regs

A32 1MB Dual Port RAM

A32 256B All other regs

Where:

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address modifiers AM=$29 or $2D for VXI short address.

A16

address modifiers AM=$09 or $0D for VXI extended address.

A32

Selects a VXI interface reg, for D16 only transfers.

Selects a Dual Port Ram location for D16/D32 transfers.

z Selects a board I/O register for D16/D32 transfers.

Is manually set at LK1 to be 1 when off, 0 when on

Note that LK1 sw 1 corresponds to VXI A13. Programmable in VXI register ‘OFFSET’ at x = $06.

Programmable in VXI register ‘SUB-CLASS OFFSET’ at x = $08.

n Is a do not care bit.

15.13 VXI Interface Registers in Block VXI1.

These are the standard 16 bit wide VXI registers occupying 64 bytes. Only 6

J22

J43

J23

J24

J44

J25 J45 J26 J46

PATCH AREA

J49

J40

J50

J42

J41

J39

J48

Figure3: Patch Area Layout

addresses are decoded, as follows:

ID DEVTYPE VSTATUS

VCONTR

x = $00 is $5123 ro = Extended, A16/A32, Manuf $123 x = $02 is $B301 ro = 1MB, Model $301 x = $04 is $dddd ro = see below. x = $04 is $dddd wo = A32 enable b15, RESET BOARD b0.

J27

J47

J51

J52

J53

J54

J55

J56

J57

J58

F R O N T

P A N E L

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OFFSET SUBOFFS SUBCLAS

dddd = b15:

b14:

b3: b2: ro Passed self test, always 1

rw A32 enable, cleared by board reset ro TIM ID ro TIM CONFIG

rw RESET BOARD, not cleared by board reset

x = $06 is $bbbb rw = Dual port ram offset (see above) x = $08 is $cccc rw = Other regs offset (see above) x = $1E is $1123 ro = Manuf sub class $1, Manuf $123

All other locations read as zero, writes have no effect. A32 enable must be set for VXI2 and VXI3 to be decoded. OFFSET and SUBOFFS are NOT cleared by a board reset. OFFSET and SUBOFFS MUST be initialised before A32 enable is set. ro = read only, wo = write only,rw = read/write.

15.14 Other Board Registers in Block VXI3.

The other registers are:

JTAG z = $00-$7F RW LINK z = $80-87 RW

LINKST z = $90-93 RO

RESET z =$C0-C3 RW RESET BOARD b4 (same bit as VCONTR b0)

JTAG I/O Link I/O Link status b8-11

OUT

J35 J28 J30

J34 J29 J31

J32

J33

J59

J60

PCB

Figure4: Front Panel Connectors

CON1 z = $E0-E3 WO TIM1 interrupt enables b0-8 CON2 z =$E4-E7 WO

TIM5 interrupt enables b0-8

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CON3 z=$E8-EB WO CON4 z=EC-EF WO

CONST z=$F0-F3 RO

VXI interrupt enables b0-10 VXI bus master control b0-31 Interrupt flags b0-10

Note:con4.15= linksel, 1 = TIM5, 0 = TIM1.

15.15 Link Control State Machines in IC60

The ‘Port Arbitration Unit’ (PAU) state machine is exactly as described in the TMS320C4x User’s Guide of 1993. PAU state machine locationswithinIC60 are:

GLB StateMachine

B0 PAU for TIM1 on bus R B6 PAU for TIM5 on bus P

Thereare 4 flagsassociated with occupancy:

Name Description

TXFULL The user accessible TX reg is full RDAVAIL TXMFULL

RXMFULL

The user accessible RX reg is full The internal TX multiplexor is not empty The internal RX multiplexor is full

15.16 Patch Area Connectors Layout

There are 26 patch area connectors, which are arranged as follows when viewed from the back of the board, with the front panel on the right:

J51-58 (right hand column) are the buffered front panel comm-ports (see table for mapping).

The rest connect via 27 ohm series damping resistors, directly to the TIM comm-ports,as follows:

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TIM Site TIM Port TIM

Connector

1 1 J7 J22 OUT CX0 1 2 J7 J23 OUT CX1 1 4 J7 J43 IN CX2 2 1 J9 J24 OUT CX3 2 4 J9 J44 IN CX4 3 1 J10 J25 OUT CX5 3 4 J10 J45 IN CX6 4 1 J12 J26 OUT CX7 4 4 J12 J46 IN CX8 5 1 J15 J42 OUT CX17 5 2 J15 J41 OUT CX16 5 4 J15 J50 IN CX15 6 1 J17 J40 OUT CX14 6 4 J17 J49 IN CX13 7 1 J19 J39 OUT CX12 7 4 J19 J48 IN CX1 8 1 J21 J27 OUT CX10 8 4 J21 J47 IN CX9

Patch

Connector

ResetTo Net Names

15.17 Front Panel Connectors Layout

There are 10 front panel connectors, which are arranged as follows when viewed from the front of the board:

J35 and J34 are 20-way JTAG connectors. J35 is the input to the board from a remoteJTAG controller. J34 is an output fromthe board.

The rest are 26-way buffered comm-port connectors. The buffers for the top row, J28,30, 32, 59 reset to output, while the buffers for thebottomrow, J29, 31, 33, 60 resetto input.

15.18 Front Panel ‘C4x Comm-ports.

15.18.1

The 8 front panel (FP) comm-port connectors, offer a buffered connection to corresponding Patch Area connectors:

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Connection to Patch Area.

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Port Reset To Front Panel Patch Area

1 In J29 J52 2 In J31 J54 3 In J33 J56 4 In J60 J58 5 Out J28 J51 6 Out J30 J53 7 Out J32 J55 8 Out J59 J57

15.18.2

Front Panel Comm-port Cabling

Connecting between ‘Resetto In’ and ‘Reset to Out’ portsrequires a 1 to 1 cable: Cable plugs are: 3M Scotchflex 10126-6000EL FES part 038740A

Plug shellsare : 3M Scotchflex 10326-A200-00 FES part 038760D Cabletype is: 3M Scotchflex KUCKMPVVSB28-13PAIR FES part 038781E

This cable has 13 individual pairs, with an overall shield, and an outer diameter of 7mm.Cablelengthshouldbe as short aspossible.Themaximumtestedcablelength is 600mm, which allows connection between any boards in 1 rack, or between adjacent racks.

If connecting to an adjacent rack, it is essential that both racks share a common ground. This must include a seperatechassisearthing strap connected between the racks. Do not connect ‘Reset to In’ ports together. Do not connect ‘Reset to Out’ port together. However if this should occur, no damage will result, because port direction signals disableportsconnected together like this.

The following table shows connector pinout and cable pair connections. This is important as the critical signals must be paired with a ground as shown. The allocationtotwisted pairsisbased on groupingthe data signalsbecausetheychange at the same time, so that crosstalk is not an issue. Each control signal has its own ground:

Pair Pin Row A Signal Pin Row B Signal

1 1 IN 2 GND 2 3 OUT 4 GND 3 5 -CSTRB 6 GND

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4 7 -CRDY 8 GND 5 9 -CREQ 10 GND 6 11 -CACK 12 GND 7 13 CD0 14 CD1 8 15 CD2 16 CD3

9 17 CD4 18 CD5 10 19 CD6 20 CD7 11 21 VCC1AMP 22 GND 12 23 -RESET 24 GND 13 25 SPARE 26 GND

The overallshieldis attached to thebody of the metal plug shell. ThesignalVCC1AMP is fusedontheboardat1 amp.Thefuseautomaticallyresets

when the load is removed. On ports which resetto input, pin 1 is alwaysdriven and pin 3 alwaysreceived.

On ports which reset to output, pin 3 is always driven and pin 1 always received.

15.19 JTAG Front Panel Connectors

Thereare two 20-way front panel JTAG connectors.J35is furthestfrom the board, andis an output to controlanotherJTAGslave. J34 is nearesttotheboard,andisan input from a JTAG controller For example an XDS510 or another SMT301 acting as a JTAG master.

When a TIM is not fitted in a site, the SMT301 automatically through routes the JTAG serial data signal. This is done with a high speed buffer (74FCT2244CTQ) which has a maximum delay of 4.1ns. Because of this cumulative delay, a JTAG clock speed of 5MHz should be used, not thedefault10MHz.Ifmultiple boardsare connected, this clock rate willneed to be reducedfurther for reliable operation.

15.19.1

JTAG front panel cabling

The 20-way JTAG connectorsrequire the following cabling components: Cableplugs are: 3M Scotchflex 10120-6000EL, FES part 038739R

Plug shellsare: 3MScotchflex 10320-A200-00, FES part 038759A. Cabletype is: 3M Scotchflex KUCKMPVVSB28-10PAIR, FES part 038780G

Pinoutfor J34 (nearest the board), this acts as a JTAGtarget:

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Pin J34Signal Direction Description

1 TDI IN

2 GND -

3 TDO OUT

4 GND -

5 TMS IN JTAG Test Mode Select

6 GND -

7 TCK IN

8 GND -

9 TCK_RET OUT 10 GND 11 -TRST IN 12 GND 13 -RESET IN 14 PD OUT 15 -DETECT IN 16 CONFIG OPEN COLL 17 EMU0 OUT 18 EMU1 OUT 19 SPARE1 20 SPARE2 -

JTAG Data In to SMT301

JTAG Data Out to SMT301

JTAG Clock, 5MHz maximum

JTAG Clock Return

JTAG Reset

SMT301 Board Reset Presence Detect, VCC (+5V) at 1 AMP fused Detect external JTAG controller when GND Global open collector ‘C4x CONFIG Buffered EMU0 output Buffered EMU1 output

Pinoutfor J35 (furthestfrom the board), this acts as a JTAG controller:

Pin J35Signal Direction Description

1 TDI OUT JTAG Data In to SMT301

2 GND -

3 TDO IN

4 GND -

5 TMS OUT

6 GND -

7 TCK OUT

8 GND -

9 TCK_RET IN 10 GND -

JTAG Data Out to SMT301

JTAG Test Mode Select

JTAG Clock, 5MHz maximum

JTAG Clock Return

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11 -TRST OUT 12 GND 13 -RESET OUT 14 PD IN 15 -DETECT OUT Signal external JTAG controller 16 CONFIG OPEN COLL 17 EMU0 IN 18 EMU1 IN 19 SPARE1 20 SPARE2 -

JTAG Reset

SMT301 Board Reset Presence Detect WHEN PULLED HIGH

Global open collector C4x CONFIG EMU0 in EMU1 in

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16 Physical Characteristics

16.1 Power Consumption

The static power consumption was measured under the following conditions: NoTIMsfitted, no Front panelcablesattached,theSMT301 is the only board fitted

into a standard VXI rack. The emptyrackbackplane supplycurrents have been subtracted from the measured

figures to obtain those given:

SupplyVoltage Current Consumption Power Consumption

+5.00 Volts 2.11 Amps 10.55 Watts

-2.00 Volts 0.00 Amps 0.00 Watts

-5.20 Volts 0.56 Amps 2.91 Watts

16.2 Board Dimensions

The board conformsto the VXI standardfor a ‘Size C’ board. This is:

340.0 (+0,-0.3)mm by 233.35 (+0, -0.3) mm.

16.3 Recommended Operating Conditions

The DC VoltageSpecification is the standardVXIbusspecification:

Specification Minimum Nominal Maximum Units

Vcc 4.875 5.00 5.25 Volts Vet -1.90 -2.00 -2.10 Volts Vee -5.044 -5.2 -5.46 Volts

Temperature 0 70

Celsius

16.4 Absolute Maximum Ratings

Theseare non operating limits:

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Specification Maximum Units

Vcc 7.0 Volts Vet GND to Vee Volts Vee -8.0 Volts

Storage Temperature -65 to + 150

Celsius

16.5 Airflow Requirements

The actual power consumption, airflow requirements and airflow resistance, are dependent on the TIMs fitted and on the activity on the board.

The minimum total airflow provided should be the greater of the following (A or B):

A. 3.70 Litres per second (same as HewlettPackard E1485A/B) B. The SUM of the airflow requirements of the fitted TIMs.

Thisairflow must be distributedevenly alongthelengthoftheboard,to prevent hot spots. This is especially important for the Hewlett Packard ECL interface IC1, whichcan dissipate5.7 watts, and is locatedadjacent to P2 on the VXI bus.

16.6 Electromagnetic Shielding

Board drilling locations are available for customers who want to attach an EMI shield. Any such shield must not reduce the airflow to eithersideof the board.It is the customers responsibility to perform operational airflow resistance and temperaturetests, with the shield fitted,to ensureprematurefailure is not caused by overheating,due to restrictedairflow.

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