Sundance SMT950 User Manual
SMT950
User Manual
Version 2.0 Page 2 of 52 SMT950 User Manual
Revision History
Changes Made Issue Initials
02/09/08
21/11/09
Original Document based on SMT350 User Manual 1.0 PhSR
Update ADC DC coupling 2.0 PhSR
Version 2.0 Page 3 of 52 SMT950 User Manual
Table of Contents
Physical Properties ....................................................................................................... 7
Ordering Information..................................................................................................... 7
Precautions................................................................................................................... 8
Introduction ................................................................................................................... 9
Overview ................................................................................................................... 9
Module features ........................................................................................................ 9
Possible applications .............................................................................................. 10
Related Documents ................................................................................................ 10
Functional Description ................................................................................................ 11
Block Diagram......................................................................................................... 11
Module Description ................................................................................................. 11
ADC Channels. ....................................................................................................... 13
ADC Main Characteristics. .................................................................................. 13
ADC Input Stage. ................................................................................................ 13
Clock Structure........................................................................................................ 15
Dual-Channel DAC. ................................................................................................ 16
DAC Main characteristics. ................................................................................... 16
DAC output stage. ............................................................................................... 17
Clock Structure........................................................................................................ 17
Power Supply and Reset Structure......................................................................... 20
JumperJ1 ................................................................................................................ 20
Green LEDs. ........................................................................................................... 20
Mezzanine module Interface................................................................................... 20
Control Register Settings............................................................................................ 28
Control Packet Structure......................................................................................... 28
Reading and Writing Registers ............................................................................... 28
Memory Map ........................................................................................................... 29
Register Descriptions.............................................................................................. 30
Reset Register – 0x0........................................................................................... 30
Test Register – 0x1. ............................................................................................ 31
ADCA Register 0 – 0x2. ...................................................................................... 31
ADCA Register 1 – 0x3. ...................................................................................... 32
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ADCA Register 2 – 0x4. ...................................................................................... 32
ADCB Register 0 – 0x5. ...................................................................................... 32
ADCB Register 1 – 0x6. ...................................................................................... 33
ADCB Register 2 – 0x7. ...................................................................................... 33
DAC Register 0 – 0x8.......................................................................................... 34
DAC Register 1 – 0x9.......................................................................................... 34
DAC Register 2 – 0xA. ........................................................................................ 34
DAC Register 3 – 0xB. ........................................................................................ 34
DAC Register 4 – 0xC. ........................................................................................ 35
DAC Register 5 – 0xD. ........................................................................................ 35
DAC Register 6 – 0xE. ........................................................................................ 35
DAC Register 7 – 0xF. ........................................................................................ 35
CDCM7005 Register 0 – 0x10. ........................................................................... 36
CDCM7005 Register 1 – 0x11. ........................................................................... 36
CDCM7005 Register 2 – 0x12. ........................................................................... 36
CDCM7005 Register 3 – 0x13. ........................................................................... 36
CDCM7005 Register 4 – 0x14. ........................................................................... 37
CDCM7005 Register 5 – 0x15. ........................................................................... 37
CDCM7005 Register 6 – 0x16. ........................................................................... 37
CDCM7005 Register 7 – 0x17. ........................................................................... 37
Main Module Temperature (not implemented) – 0x18........................................ 38
Main Module FPGA Temperature (not implemented) – 0x19 ............................. 38
Mezzanine Module Temperature (not implemented) – 0x1A.............................. 38
Mezzanine Module Converters Temperature (not implemented) – 0x1B ........... 38
Miscellaneous Register – 0x1C........................................................................... 38
Updates, Read-back and Firmware Version Registers – 0x1D .......................... 40
DDS Register 0 – Start Phase Increment LSB - 0x20 ........................................ 40
DDS Register 1 – Start Phase Increment MSB - 0x21 ....................................... 41
DDS Register 2 – Stop Phase Increment LSB - 0x22 ........................................ 41
DDS Register 3 – Stop Increment MSB - 0x23................................................... 41
DDS Register 0 – Step Phase Increment LSB - 0x24 ........................................ 42
DDS Register 5 – Step Increment MSB - 0x25................................................... 42
DAC (DAC5687) Register 0x0 – 0x30................................................................. 43
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DAC (DAC5687) Register 0x1 – 0x31................................................................. 43
DAC (DAC5687) Register 0x2 – 0x32................................................................. 43
DAC (DAC5687) Register 0x3 – 0x33................................................................. 43
DAC (DAC5687) Register 0x4 – 0x34................................................................. 44
DAC (DAC5687) Register 0x5 – 0x35................................................................. 44
DAC (DAC5687) Register 0x6 – 0x36................................................................. 44
DAC (DAC5687) Register 0x7 – 0x37................................................................. 44
DAC (DAC5687) Register 0x8 – 0x38................................................................. 45
DAC (DAC5687) Register 0x9 – 0x39................................................................. 45
DAC (DAC5687) Register 0xA – 0x3A................................................................ 45
DAC (DAC5687) Register 0xB – 0x3B................................................................ 45
DAC (DAC5687) Register 0xC – 0x3C ............................................................... 46
DAC (DAC5687) Register 0xD – 0x3D ............................................................... 46
DAC (DAC5687) Register 0xE – 0x3E................................................................ 46
DAC (DAC5687) Register 0xF – 0x3F ................................................................ 46
FPGA Design.............................................................................................................. 47
Serial Interfaces ...................................................................................................... 47
Block of registers .................................................................................................... 48
Space available in FPGA ........................................................................................ 48
PCB Layout................................................................................................................. 49
Connectors ................................................................................................................. 51
Description .............................................................................................................. 51
Location on the board ............................................................................................. 52
Table of Figures
Figure 1 – Fan across PCI. ......................................................................................................8
Figure 2 - Block Diagram........................................................................................................11
Figure 3 - Main features. ........................................................................................................13
Figure 4 - ADC Input Stage. ...................................................................................................14
Figure 5 - ADC Input Stage (DC Coupling) ............................................................................14
Figure 6 - Clock Structure. .....................................................................................................15
Figure 7 - DAC Output Stage. ................................................................................................17
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Figure 8 - Clock Structure. .....................................................................................................18
Figure 9 - External Clock........................................................................................................19
Figure 10 - Clock Architecture Main Characteristics. .............................................................20
Figure 11 – Mezzanine module Connector Interface (SLB data and power connectors).......21
Figure 12 – Mezzanine Module Interface Power Connector and Pinout. ...............................23
Figure 13 – Daughter Module Interface: Data Signals Connector and Pinout (Bank A). ......24
Figure 14 – Daughter Module Interface: Data Signals Connector and Pinout (Bank B). .......26
Figure 15 – Daughter Module Interface: Data Signals Connector and Pinout (Bank C). .......27
Figure 16 – Setup Packet Structure. ......................................................................................28
Figure 17 – Control Register Read Sequence. ......................................................................28
Figure 18 - Firmware Block Diagram......................................................................................47
Figure 19 - Space available in FPGA .....................................................................................48
Figure 20 – Main Module Component Side............................................................................49
Figure 21 - Main Module (SMT368) Solder Side....................................................................49
Figure 22 - Daughter Module Component Side......................................................................50
Figure 23 - Daughter Module Solder Side..............................................................................50
Figure 24 - Connectors Location. ...........................................................................................52
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Physical Properties
Dimensions 63.5mm x 106.7mm x 18mm
Weight 35 grams
Supply Voltages
Supply Current +12V N/A
+5V 1.2 Amps (reset
/ converters
active)
1.4 Amps max
+3.3V 0.14 Amp (reset
/ converters
active)
0.4 Amps max
-5V N/A
-12V N/A
MTBF
Ordering Information
SMT950 (Standard Product): ADC inputs and DAC outputs are AC-coupled.
SMT950-DC: ADCs inputs are DC-coupled and DAC outputs are AC-coupled.
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Precautions
In order to guarantee that Sundance’s boards function correctly and to protect the
module from damage, the following precautions should be taken:
- They are static sensitive products and should be handled accordingly.
Always place the modules in a static protective bag during storage and transition.
- When operated in a closed environment make sure that the heat generated
by the system is extracted e.g. a fan extracting heat or blowing cool air. Sundance
recommends and uses PAPST 12-Volt fans (Series 8300) producing an air flow of 54
cubic meters per hour (equivalent to 31.8 CFM). Fans are placed so they blow across
the PCI bus as show on the following picture:
Figure 1 – Fan across PCI.
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Introduction
Overview
The SMT950 is a single width expansion TIM that plugs onto the SLB
SMT368
Converters (ADS5500
Converter (DAC5687
based on a CDCM7005
(Virtex-4 FPGA) and incorporates 2 Texas Instrument Analog-to-Digital
) and a Texas Instrument dual-channel Digital-to-Analog
). The SMT950 implements a comprehensive clock circuitry
chip that allows synchronisation among the converters and
base module
cascading modules for multiple receiver or transmitter systems as well as the use of
an external reference clock. It provides a complete conversion solution and stands as
a platform that can be part of a transmit/receive base station.
ADCs are 14-bit and can sample at up to 125 MHz. The DAC has a resolution of 16
bits and is able to update outputs at up to 500MHz. All converters are 3.3-Volt.
The Xilinx FPGA
(Virtex-4) on the base module is responsible for handling data
going/coming to/from one of the following destination/source: TI converters, Comport
(TIM-40 standard
), Sundance High-speed Bus (SHB). These interfaces are
compatible with a wide range of Sundance’s modules.
The memory on base module can be divided into two 16-bit wide independent blocks
for storing incoming and/or outgoing samples.
Converter configuration, sampling and transferring modes are set via internal control
registers stored inside the FPGA and accessible via Comport.
Module features
The main features of the SMT950 are listed below:
● Dual 14-bit 125MSPS ADC (ADS5500
),
● Dual channel 16-bit 500MSPS DAC (DAC5687
● On-board low-jitter clock generation (CDCM7005
● One external clocks, two external triggers and one reference clock via
MMCX
connector,
● One SLB
connector to link SMT950 and SMT368 or SMT351T as an
example,
● Synchronisation signals,
● All Analogue inputs to be connected to 50-Ohm sources.
● All Analogue outputs to be connected to 50-Ohm loads.
● Temperature sensors.
),
),
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Possible applications
The SMT950 can be used for the following application (this non-exhaustive list
should be taken as an example):
● High Intermediate-Frequency (IF) sampling architecture,
● Cellular base station such as CDMA and TDMA,
● Baseband I&Q systems,
● Wireless communication systems,
● Communication instrumentation,
● ...
Related Documents
ADS5500 Datasheet – Texas Instrument:
http://focus.ti.com/docs/prod/folders/print/ads5500.html
DAC5687 Datasheet – Texas Instrument:
http://focus.ti.com/docs/prod/folders/print/dac5687.html
CDCM7005 Datasheet – Texas Instrument:
http://focus.ti.com/docs/prod/folders/print/cdcm7005.html
Sundance High-speed Bus (SHB) specifications – Sundance.
ftp://ftp2.sundance.com/Pub/documentation/pdffiles/SHB_Technical_Specification.pdf
Sundance LVDS Bus (SLB) specifications – Sundance.
http://www.sundance.com/docs/SLB%20-%20Technical%20Specifications.pdf
TIM specifications.
ftp://ftp2.sundance.com/Pub/documentation/pdf-files/tim_spec_v1.01.pdf
Xilinx Virtex-4 FPGA.
http://direct.xilinx.com/bvdocs/publications/ds031.pdf
MMCX Connectors – Hubert Suhner.
MMCX Connectors
Surface Mount MMCX connector
Sundance Multiprocessor Technology Ltd.
SMT368
, SMT351T
Version 2.0 Page 11 of 52 SMT950 User Manual
Functional Description
In this part, we will see the general block diagram and some comments on some the
SMT950 entities.
Block Diag ram
The following diagram describes the architecture of the SMT950, coupled – as an
example – with an SMT368 to show how mezzanine and base modules are
connected together:
Power
Supplies: 1.8
and 3.3 Volts
ADC Input
Ch A MMCX
50-Ohm
ADC Input
Ch B MMCX
50-Ohm
ADCs and DAC External
Clock In - MMCX
ADCs and DAC External
Clock Out - MMCX
External Reference
Clock Out - MMCX
External Reference
Clock In - MMCX
DAC Output
Ch A MMCX
50-Ohm
DAC Output
Ch B MMCX
50-Ohm
Temperature
Sensors
Channel A
Signal
Conditioning
Channel B
Signal
Conditioning
Channel A
Signal
Conditioning
Channel B
Signal
Conditioning
ADS5500
ADC ChA
14-bit 125MSPS
ADS5500
ADC ChB
14-bit 125MSPS
PECL Clock
Generation and
Distribution
based on
CDCM7005 and
SN65LVPC23
DAC5687
Dual Channel DAC
16-bit 500MSPS
Interpolation
External ADC
Trigger
ChA Data(14),
Clock and Control
ChB Data(14),
Clock and Control
ChA Data (16)
and Control
ChB Data (16)
and Control
External ADC
Trigger
DAC Clock
Daughter Card
Daughter Card
SMT950
interface
connector
SLB
Power
connector
SLB
Bank A
Bank B
Bank C
Virtex-4
XCV4SX35
FF668 Package
448 IOs
ChA&ChB Data, Clock
and Control (60)
2xComports and
Control (24)
ChA&ChB Data, Clock
and Control (60)
Power
Supplies: 1.25,
1.5, 2.5 and 3.3
Volts
SHBB
ADC Channel A and
Channel B
Spare SHB connector
(SHBA)
Top and Bottom TIM
Connectors
Spare SHB connector
(SHBC)
SHBD
DAC Channel A and
Channel B
SMT368
Figure 2 - Block Diagram.
Module Description
The module is built around two TI ADS5500
converters and one TI DAC5687
ADCs
: Analog data enters the module via two MMCX connectors, one for each
dual 16-bit digital-to-analog converter.
14-bit sampling analog-to-digital
channel. Both signals are then conditioned (AC coupling; DC optional) before being
digitized. Both ADCs gets their own sampling clock, which can be either on-board
generated or from an external reference or an external clock, common to ADCs and
DAC (MMCX connector). Digital samples travel to the FPGA on the base module via
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the inter-module connector (SLB – Sundance LVDS Bus, used in this case as
‘single-ended’).
DAC
: Digital samples are routed from the FPGA to the DAC via the inter-module
connector. Internal interpolation scheme allows reaching 500 Mega Samples per
Second. The DAC shows other modes such as Dual DAC, Single side-band,
Quadrature or up conversion. Both outputs are AC-coupled. By default they are
single-ended but can optionally be differential. The DAC mode is selected via Jumper
J1, that enables or disables the DAC Internal PLL (see DAC5687 datasheet for more
details).
Clock generator and distribution
: All samplings clocks are generated by the same
chip. It allows having them all synchronized to a single reference clock.
Multi-module Synchronization
: There are two types of synchronization available on
the SMT950. The first one is frequency synchronization, by passing the external
reference clock to an other module. It first goes through a 0-delay buffer and is then
output. Note that the synchronization is in frequency and not in phase. The second
type is register synchronization between DACs. It is achieved by the way of an extra
link between several modules to synchronize DAC internal registers (DAC signal
PHSTR passed from one module to the other and driven by the master FPGA – it
resets the internal VCO).
Inter-module Connector
pins). It is called Sundance LVDS Bus. Please refer to the SLB specifications
: it is made of a power (33 pins) and data connectors (120
for
more details. In the case of the SMT950, the SLB is used as ‘single-ended’.
A global reset signal is mapped to the FPGA from the bottom TIM connector.
External Clock signals
, used to generate Sampling clocks. There is one external
clock, common to ADCs and DAC When used, the CDCM7005 is used as a clock
multiplexer. Also available, an external reference clock that can be passed to an
other SMT950 module with ‘0-delay’.
External Trigger
: passed directly to base module. There are two, one for the ADCs
and one for the DAC.
Temperature Sensor
provided.
: available for constant monitoring. Not part of default firmware
Version 2.0 Page 13 of 52 SMT950 User Manual
ADC Channels.
ADC Main Characteristics.
The main characteristics of the SMT950 ADCs are gathered into the following table.
Analogue Inputs
AC coupled option. 2.4 Vp-p (11.5 dbm –
50 Ohm) Full scale - AC coupled.
DC coupled option. 1.15 Vp-p (Gain
Input voltage range
Impedance
Bandwidth
Output Data Width
Data Format
SFDR
amplifier 6dB) centered around 0. DC
coupled via amplifier. Gain can be adjusted
to a required input amplitude centered
around 0. Minimm gain 6dBs, which should
allow input swing +/-0.575V as full scale.
ADC single-ended inputs are to be
connected to a 50Ω source. Source
impedance matching implemented between
RF transformers and ADC.
ADC bandwidth: 750 MHz.
ADCs Output
14-Bits
2’s Compliment or offset binary
(Changeable via control register)
82dBs maximum (manufacturer)
SNR
Minimum Sampling Clock
Maximum Sampling Frequency
Figure 3 - Main features.
70dBs maximum (manufacturer)
10 MHz (ADC DLL off)
125 MHz (ADC DLL on)
ADC Input Stage.
Each ADC Analogue input is AC-coupled via and RF transformer (AC-coupled
version of the SMT950). The 50-Ohm resistor between the connector and the first RF
transformer is not fitted because the source impedance match is implemented
between the second RF transformer and the ADC by the way of two 25-Ohm
resistors.
Version 2.0 Page 14 of 52 SMT950 User Manual
Figure 4 - ADC Input Stage.
The SMT950 can also receive an DC-coupling input stage on request as shown
below :
It is based around a Texas Instrument amplifier (THS4509
dBs and is to match a 50-Ohm signal source.
), which gain is set to 6
Figure 5 - ADC Input Stage (DC Coupling)
Version 2.0 Page 15 of 52 SMT950 User Manual
Clock Structure
There is one integrated clock generator on the module (AD9510 – Analog Devices).
The user can either use this clock (on-board) or provide the module with an external
clock (input via MMCX connector).
Figure 6 - Clock Structure.
ADCs can all receive the same clock or the integer multiple of it (x2, x3, …x32), the
maximum being 125MHz for each ADC. This clock can be coming from the on-board
VCXO or from an external source.
An extra connector outputs the reference clock for multiple-module systems.
Below is shown how the external clock is fed to the system. By default it is singleended and AC-coupled before being converted into LVPECL format. The option of
having a differential external clock is still possible on the hardware by the way of
fitting or not some of the components.
Version 2.0 Page 16 of 52 SMT950 User Manual
Dual-Channel DAC.
DAC Main characteristics.
The main characteristics of the SMT950 DAC are gathered into the following table.
Analogue Outputs
Input voltage range
Impedance
SFDR
SNR
Bandwidth
Output Data Width per channel
Data Format
SFDR
SNR
1 Vp-p – Full scale - AC coupled
DAC single-ended outputs are to be
connected to a 50Ω load, which impedance
matching implemented between DAC and
RF transformers.
89dBs maximum (manufacturer)
80dBs maximum (manufacturer)
TBD
DAC Input
16-Bits
2’s Compliment or offset binary
(Changeable via control register)
85dBs maximum (manufacturer)
73dBs maximum (manufacturer)
Maximum input data rate
Maximum Sampling rate
250 MSPS (Clk1 – DAC5687)
500 MSPS (Clk2 – DAC5687)
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