Sundance SMT943 User Manual
Sundance Multiprocessor Technology Limited
User Manual
Form : QCF42
Date : 11 February 2009
Unit / Module Description:
Dual ADC/DAC SLB Module
Unit / Module Number:
SMT943
Document Issue Number:
3
Issue Date:
23/06/2010
Original Author:
PhSR
Sundance Multiprocessor Technology Ltd, Chiltern House,
Waterside, Chesham, Bucks. HP5 1PS.
This document is the property of Sundance and may not be copied
nor communicated to a third party without prior written
permission.
© Sundance Multiprocessor Technology Limited 2009
User Manual
for
SMT943
User Manual SMT943 Last Edited: 23/08/2011 17:24:00
Revision History
Issue
Changes Made
Date
Initials
1
Original document.
11/01/2010
PhSR
2
Update after testing v2.
19/06/2010
PhSR
3
Captures added.
23/06/2010
PhSR
User Manual SMT943 Page 2 of 54 Last Edited: 23/08/2011 17:24:00
Table of Contents
Precautions ................................................................................................................................ 5
1 Introduction ..................................................................................................................... 6
2 Related Documents ........................................................................................................ 7
2.1 Referenced Documents .............................................................................................. 7
2.2 Applicable Documents ............................................................................................... 7
3 Functional Description .................................................................................................. 8
3.1 Block Diagram.............................................................................................................. 8
3.2 Module Description .................................................................................................... 8
3.2.1 A/D converters ....................................................................................................... 9
3.2.2 D/A converters ..................................................................................................... 12
3.2.3 Clock structure ..................................................................................................... 15
3.3 FPGA Design ............................................................................................................... 18
3.3.1 Control Register Settings .................................................................................... 18
Register Descriptions ......................................................................................................... 20
3.3.2 Control Register – 0x1. ........................................................................................ 20
CLOCK Register 0 – 0x10. .............................................................................................. 21
CLOCK Register 1 – 0x11. .............................................................................................. 22
CLOCK Register 2 – 0x12. .............................................................................................. 22
CLOCK Register 3 – 0x13. .............................................................................................. 23
CLOCK Register 4 – 0x14. .............................................................................................. 23
CLOCK Register 5 – 0x15. .............................................................................................. 24
CLOCK Register 6 – 0x16. .............................................................................................. 25
CLOCK Register 7 – 0x17. .............................................................................................. 25
CLOCK Register 8 – 0x18. .............................................................................................. 26
CLOCK Register 9 – 0x19. .............................................................................................. 26
CLOCK Register A – 0x1A. ............................................................................................. 27
CLOCK Register B – 0x1B. .............................................................................................. 27
CLOCK Register C – 0x1C. ............................................................................................. 28
CLOCK Register D – 0x1D. ............................................................................................. 28
CLOCK Register E – 0x1E. .............................................................................................. 29
CLOCK Register F – 0x1F. .............................................................................................. 29
CLOCK Register 10 – 0x20. ............................................................................................ 29
CLOCK Register 11 – 0x21. ............................................................................................ 30
CLOCK Register 12 – 0x22. ............................................................................................ 30
CLOCK Register 13 – 0x23. ............................................................................................ 31
CLOCK Register 14 – 0x24. ............................................................................................ 31
CLOCK Register 15 – 0x25. ............................................................................................ 32
CLOCK Register 16 – 0x26. ............................................................................................ 32
CLOCK Register 17 – 0x27. ............................................................................................ 33
CLOCK Register 18 – 0x28. ............................................................................................ 34
CLOCK Register 19 – 0x29. ............................................................................................ 34
ADC Chab Register 0 – 0x30. ........................................................................................ 35
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ADC Chab Register 1 – 0x31. ........................................................................................ 35
ADC Chab Register 2 – 0x32. ........................................................................................ 36
ADC Chab Register 3 – 0x33. ........................................................................................ 36
ADC Chab Register 4 – 0x34. ........................................................................................ 37
ADC Chab Register 5 – 0x35. ........................................................................................ 37
ADC Chab Register 6 – 0x36. ........................................................................................ 38
ADC Chab Register 7 – 0x37. ........................................................................................ 39
ADC Chab Register 8 – 0x38. ........................................................................................ 40
ADC Chab Register 9 – 0x39. ........................................................................................ 40
DAC chcd Register 0 – 0x40. ......................................................................................... 41
DAC chcd Register 1 – 0x41. ......................................................................................... 42
DAC chcd Register 2 – 0x42. ......................................................................................... 43
DAC chcd Register 3 – 0x43. ......................................................................................... 44
DAC chcd Register 4 – 0x44. ......................................................................................... 44
DAC chcd Register 5 – 0x45. ......................................................................................... 45
DAC chcd Register 6 – 0x46. ......................................................................................... 45
DAC chcd Register 7 – 0x47. ......................................................................................... 46
DAC chcd Register 8 – 0x48. ......................................................................................... 46
DAC chcd Register 9 – 0x49. ......................................................................................... 46
DAC chcd Register A – 0x4A. ........................................................................................ 47
DAC chcd Register B – 0x4B. ......................................................................................... 48
DAC chcd Register C – 0x4C. ........................................................................................ 48
DAC chcd Register D – 0x4D. ........................................................................................ 49
DAC chcd Register D – 0x4D. ........................................................................................ 49
DAC chcd Register E – 0x4E. ......................................................................................... 49
DAC Chcd – Phase shift DCM – 0x50. .......................................................................... 50
4 Pictures of the board ................................................................................................... 51
4.1 Top View ..................................................................................................................... 51
4.2 Bottom View ............................................................................................................... 52
5 Connectors ..................................................................................................................... 52
5.1 Description ................................................................................................................. 52
5.2 Location on the board .............................................................................................. 53
6 Physical Properties ....................................................................................................... 54
7 Safety ............................................................................................................................... 54
8 Ordering Information .................................................................................................. 54
9 EMC .................................................................................................................................. 54
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Table of Figures
Figure 1 - SMT943 Block diagram. .......................................................................................... 8
Figure 2 - ADC input terminated (50 Ohms). ..................................................................... 10
Figure 3 - ADC input terminated (50 Ohms) - Raw data. ................................................. 10
Figure 4 - ADCA input terminated (50 Ohm) - ADCB receiving a 20.04Mhz tone. ..... 11
Figure 5 – ADCA 20.6MHz tone - 200MSPS. ....................................................................... 11
Figure 6 - ADCA 60.55MHz tone - 200MSPS. ...................................................................... 12
Figure 7 - DAC Output 20.04-MHz sinewave - Narrow band. ......................................... 13
Figure 8 - DAC Output 20.04-MHz sinawave - Wide bandwidth. ................................... 14
Figure 9 - DAC output 20.04-MHz sinewave - Full bandwidth. ...................................... 14
Figure 10 - Clock Structure - Block Diagram ...................................................................... 15
Figure 11 - Clock Architecture Main Characteristics. ....................................................... 16
Figure 12 - External clock output (98.304MHz – Divided by 5 output) ........................ 16
Figure 13 - External Clock output (245.76MHz – Divided by 2 output). ....................... 17
Figure 14 - External Clock Output (491.52MHz – Divided by 1 output). ...................... 17
Figure 15 – Setup Packet Structure. ..................................................................................... 18
Figure 16 – Control Register Read Sequence. .................................................................... 18
Figure 17 – Register Memory Map. ....................................................................................... 19
Figure 18 - Connectors ........................................................................................................... 53
Figure 19 - SMT593 Loopback pcb. ...................................................................................... 54
Precautions
In order to guarantee that Sundance’s boards function correctly and to protect the
module from damage, the following precautions should be taken:
- They are static sensitive products and should be handled accordingly.
Always place the modules in a static protective bag during storage and transition.
User Manual SMT943 Page 5 of 54 Last Edited: 23/08/2011 17:24:00
1 Introduction
The SMT943 is a single width expansion TIM that plugs onto an SLB base module,
the SMT351T (Virtex-5 LXT, SXT or even FXT FPGA) as an example and incorporates
1 Texas Instrument dual-channel Analog-to-Digital Converter (ADS62P49) and 1
Texas Instrument dual-channel Digital-to-Analog Converter (DAC5688). The SMT943
implements a comprehensive clock circuitry based on a chip (CDCE72010) from
Texas instrument that allows synchronisation among the converters and the use of
an external reference clock or sampling clock. It provides a complete conversion
solution and stands as a platform that can be part of a transmit/receive base
station. The SMT943 has an on-board VCXO of frequency 491.52MHz.
The DAC has a resolution of 16 bits and can update its outputs at up to
800MSamples per second. The converter is 1.8/3.3-Volt. Among the features of the
DAC5688 are integrated interpolation filters, a fine frequency mixer with a complex
NCO, a clock multiplier and IQ compensation. No DC-coupled version is currently
available on the DAC.
The ADC has a resolution of 14 bits and can update its outputs at up to 250MHz. All
converters are 1.8/3.3-Volt. ADCs internal gain and offset can be adjusted as well as
the data format. ADCs are AC-coupled on the board using a double-transformer
structure. No DC-coupled version is currently available on the ADC.
The Xilinx FPGA (Virtex-5 LXT or SXT series in the case of the SMT351T) on the base
module is responsible for handling data coming from one of the following sources:
Comports or Rocket Serial Link (RSL). These interfaces are compatible with a wide
range of Sundance’s modules.
The memory (DDR2) on the base module (still based on the case where using an
SMT351T SLB base module) can store samples.
Converter configuration, sampling and transferring modes are set via internal
control registers stored inside the FPGA and accessible via Comport.
The SMT943 module is well-suited for multi-carrier, wide bandwidth communication
applications.
The main features of the SMT943 are listed below:
● One Dual 14-bit 250MSPS ADC (ADS62P49),
● One Dual 16-bit 800MSPS DAC (DAC5688),
● On-board low-jitter clock distribution chip (CDCE72010),
● On-board 491.52MHz VCXO,
● On-board 10MHz reference crystal,
● One external clock, one external trigger and one reference clock inputs via
MMCX connector,
● One external clock output via MMCX connector,
● One SLB connector to link SMT943 and SMT351T (set to 2.5-V FPGA IOs) as
an example,
● All Analogue inputs to be connected to 50-Ohm sources.
● All Analogue outputs to be connected to 50-Ohm loads.
● A fan.
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2 Related Documents
2.1 Referenced Documents
ADC datasheet: Texas Instrument ADS62P49.
DAC datasheet: Texas Instrument DAC5688.
Clock datasheet: Texas Instrument CDCE72010.
2.2 Applicable Documents
User Manual SMT943 Last Edited: 23/08/2011 17:24:00
SLB Interface connector
ADS62P49
Dual ADC Ch A
& Ch B
14-bit
250MSPS
(2x 675mW)
DAC5688
Dual channel
DAC
16-Bit
800MSPS
Interpolation
(1.3W)
Clock Synchronizer and
Jitter cleaner
Based on
CDCE72010
(1.8W)
Channel B
Signal
Conditioning
(AC coupling)
Channel A
Signal
Conditioning
(AC coupling)
Channel B
Signal
Conditioning
(AC coupling)
Channel A
Signal
Conditioning
(AC coupling)
DAC
Output
Ch A
MMCX
50 Ohm
DAC
Output
Ch B
MMCX
50 Ohm
ADC Input
Ch A
MMCX
50 Ohm
ADC Input
Ch B
MMCX
50 Ohm
ADCs
External
Clock in
MMCX
External
Refference
Clock in
MMCX
ADCs
External
Clock out
MMCX
Ch A – 1.8V DDR LVDS
Clock and Control
Ch B – 1.8V DDR LVDS
Clock and Control
Ch A – Data (16)
and Control
Ch B – Data (16)
and control
SLB Power connector
External Trigger
FPGA Clock
SMT943
ADC / DAC
Module, 2 ADC
Channels; 250MHz
@ 14 bits; 2 DACs
@ 800MHz/16 bits
Power Supplies:
1.8 and 3.3V
Linear
Regulators
3 Functional Description
3.1 Block Diagram
Figure 1 - SMT943 Block diagram.
3.2 Module Description
The SMT943 has got 1 dual channel Analog-to-Digital converters (ADS62P49 – Texas
Instrument) that has been designed for multi-carrier, wide bandwidth
communication applications. Both analog inputs are available on MMCX connectors.
They are 50-Ohm AC-coupled inputs (RF transformers - ration 1). DDR LVDS lines
are used to carry samples through the SLB connector to the FPGA (SLB base module FPGA IOs must be set to 2.5-Volt). The module has also got a dual channel DAC
(DAC5688 – Texas Instrument) that has integrated 2x-8x interpolation filters, a fine
frequency mixer with a 32-bit complex numerically controlled oscillator, an onboard clock multiplier, an IQ compensation and an internal voltage reference.
A clock distribution chip ensures that all converters sample synchronously to a
single clock source. The clock source can be external or internal (on-board 491.52MHz VCXO). The distribution chip also allows synchronising the on-board VCXO to a
reference signal that can be external or internal (on-board 10-MHz crystal). External
reference, external sampling clock input and output are accessible on MMCX
connectors. An external trigger input is also available on the board.
All control, data and clock lines are mapped onto an SLB connector so the card can
be fully controlled by an SLB FPGA base module (SMT351T for example).
User Manual SMT943 Last Edited: 23/08/2011 17:24:00
Some green LEDs are available on the board. A group of four LEDs is driven directly
Analogue Inputs
Input voltage range
0dB gain setting : 2.3Vpp - Full scale - AC
coupled
6dB gain setting : 1.15Vpp – Full Scale –
AC-coupled
Programmable input gain via register
(0…6dBs) by steps of 0.5dB (coarse gain)
and steps of 0.134dB (fine gain).
Impedance
Single-ended inputs – to be connected to a
50 source.
Bandwidth
Tbd – depends on ADC internal input gain.
ADC characteristics
Output Data Width per channel
14 Bits
Data Format
2’s Compliment or offset binary
(Changeable via control register)
SFDR
75 (0-db gain) / 82dBs (6-db gain)
maximum (manufacturer)
SNR
69 (0-db gain) / 66dBs (6-db gain)
maximum (manufacturer)
ENOB
11.3 bits maximum (manufacturer)
Maximum Sampling rate
250 MSPS
(1…100MSPS low speed mode)
(100…250MSPS high speed mode)
Minimum Sampling rate
1 MSPS
from the SLB base FPGA module and can be used to return status bits. Other
indivudual LEDs should be lit and show that local power supplies are on.
3.2.1 A/D converters
The main characteristics of the SMT943 are gathered into the following table.
ADC Analog inputs on the board are single-ended. A double RF transformer
structure is used to provide single-ended to differential conversion. Both
transformers are identical and have a ratio of 1. In order to match the 50-Ohm at
the connector, the output of the second transformer has two 25-Ohm resistors
terminated to the ADC common mode voltage.
Below are some captures. All of them are 2048 points. ADCs are sampling at
245.76MHz and have an input gain of 6dBs:
User Manual SMT943 Page 9 of 54 Last Edited: 23/08/2011 17:24:00
Figure 2 - ADC input terminated (50 Ohms).
Figure 3 - ADC input terminated (50 Ohms) - Raw data.
User Manual SMT943 Page 10 of 54 Last Edited: 23/08/2011 17:24:00
Figure 4 - ADCA input terminated (50 Ohm) - ADCB receiving a 20.04Mhz tone.
Below are some captures. All are 2048 points. ADCs are sampling at 200MHz and
have an input gain of 6dBs:
Figure 5 – ADCA 20.6MHz tone - 200MSPS.
User Manual SMT943 Page 11 of 54 Last Edited: 23/08/2011 17:24:00
Figure 6 - ADCA 60.55MHz tone - 200MSPS.
Analogue Outputs
Output voltage range
1 Vp-p – Full scale - AC coupled
Impedance
DAC single-ended outputs are to be
connected to a 50 load, which impedance
matching implemented between DAC and
RF transformers.
SFDR
89dBs maximum (manufacturer)
SNR
80dBs maximum (manufacturer)
Bandwidth
TBD
DAC Input
Output Data Width per channel
16-Bits
Data Format
2’s Compliment or offset binary
(Changeable via control register)
SFDR
85dBs maximum (manufacturer)
SNR
73dBs maximum (manufacturer)
Maximum input data rate
250 MSPS (Clk1 – DAC5688)
Maximum Sampling rate
800 MSPS (Clk2 – DAC5688)
3.2.2 D/A converters
The main characteristics of the SMT943 are gathered into the following table.
User Manual SMT943 Page 12 of 54 Last Edited: 23/08/2011 17:24:00
Below are some captures of the DAC output. The DAC was set to output a 20.04MHz tone under a sampling clock of 245.76MHz and an interpolation factor of 2
(DAC internally clocked at 491.52MHz):
Figure 7 - DAC Output 20.04-MHz sinewave - Narrow band.
User Manual SMT943 Page 13 of 54 Last Edited: 23/08/2011 17:24:00
Figure 8 - DAC Output 20.04-MHz sinawave - Wide bandwidth.
Figure 9 - DAC output 20.04-MHz sinewave - Full bandwidth.
User Manual SMT943 Page 14 of 54 Last Edited: 23/08/2011 17:24:00
3.2.3 Clock structure
Clock Synthesizer and Jitter Cleaner - Texas Instrument CDCE72010
U2 - DAC Clk2 Channel c&d
U7 - Clk Out and FPGA Clk Output (ExtClkOut)
FPGA (SLB)
Clk In
Clk Input (ExtClkIn)
On-board VCXO
491.52 MHz
On-board 10-MHz reference
External Reference (ExtRefIn)
DAC Chc&d – DAC5688
16-bit 800MSPS
U4 - ADC Channel a&b
ADC Cha&b – ADS62P49
14-bit 250MSPS
U1 - DAC Clk1 Channel c&d
The following diagram shows the clock structure of the SMT943:
Figure 10 - Clock Structure - Block Diagram
The clock distribution chip used on the SMT943 offers 2 reference inputs, a VCXO
differential input and a charge pump to drive the VCXO, as well as a second
differential clock input. ADCs, DACs and external clock are mapped to separate
internal output dividers in order to give more flexibility.
The CDCE72010 chip is designed to provide clean, phase related clocks to the
converters. The reference clock (on-board or external) is used to lock the on-board
VCXO using the clock chip PLL/charge pump. It is also possible to feed an external
sampling clock to the chip that can then be distributed the analog converters.
Note that when the board is mounted onto a PXI SLB carrier such as the SMT700
(with 2.5-Volt FPGA IOs), it is possible to feed the 10-MHz reference clock (PXI bus)
to the SMT943 order to lock the VCXO, then creating a local source synchronised to
the rest of the system.
Also to be noted is that a VCXO of a different frequency can be fitted to replace the
standard 800-MHz one. It is to be discussed prior to ordering as it is an operation
carried out in the factory.
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The table below gathers the characteristics of all clock inputs/outputs:
External Reference Input
Input Voltage Level
1 – 3.3 Volts peak-to-peak (AC-coupled)
Frequency Range
0 – 100 MHz.
External Sampling Clock Input
Input Voltage Level
1.5 – 3.3 Volts peak-to-peak (AC-coupled)
Input Format
Single-ended.
Frequency range
10-500 MHz
External Sampling Clock Output
Output Voltage Level
0-2.4 Volts fixed amplitude
Output Format
LVTTL
External Trigger Inputs
Input Voltage Level
1.2-2.5 Volts peak-to-peak.
Format
DC-coupled and Single-ended. Protected by 2
clamping diodes.
Format
LVCMOS
Figure 11 - Clock Architecture Main Characteristics.
Below are shown some captures of the external clock output:
Figure 12 - External clock output (98.304MHz – Divided by 5 output)
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Figure 13 - External Clock output (245.76MHz – Divided by 2 output).
Figure 14 - External Clock Output (491.52MHz – Divided by 1 output).
User Manual SMT943 Page 17 of 54 Last Edited: 23/08/2011 17:24:00
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