Sundance SMT942 User Manual

Sundance Multiprocessor Technology Limited

User Manual

Form : QCF42
Date : 11 February 2009

Unit / Module Description:

Quad DAC SLB Module

Unit / Module Number:

SMT942

Document Issue Number:

1

Issue Date:

Original Author:

PhSR

Sundance Multiprocessor Technology Ltd, Chiltern House,

Waterside, Chesham, Bucks. HP5 1PS.

This document is the property of Sundance and may not be copied

nor communicated to a third party without prior written

permission.

© Sundance Multiprocessor Technology Limited 2009

User Manual

for

SMT942

User Manual SMT942 Last Edited: 23/08/2011 17:25:00

Issue

Changes Made

Date

Initials

1

Original document

13/11/2009

PhSR

Revision History

User Manual SMT942 Page 2 of 55 Last Edited: 23/08/2011 17:25:00

Table of Contents

1 Introduction ..................................................................................................................... 7

2 Related Documents ........................................................................................................ 8

2.1 Referenced Documents .............................................................................................. 8

2.2 Applicable Documents ............................................................................................... 8

3 Acronyms, Abbreviations and Definitions .............................................................. 9

3.1 Acronyms and Abbreviations ................................................................................... 9

3.2 Definitions .................................................................................................................... 9

4 Functional Description ................................................................................................ 10

4.1 Block Diagram............................................................................................................ 10

4.2 Module Description .................................................................................................. 10

4.3 Interface Description ................................................................................................ 12

4.3.1 Mechanical Interface ............................................................................................ 12

4.3.2 Electrical Interface ............................................................................................... 12

4.4 FPGA Design ............................................................................................................... 12

4.4.1 Control Register Settings .................................................................................... 12

Register Descriptions ......................................................................................................... 14

4.4.2 Control Register – 0x1. ........................................................................................ 14

CLOCK Register 0 – 0x10. .............................................................................................. 15

CLOCK Register 1 – 0x11. .............................................................................................. 15

CLOCK Register 2 – 0x12. .............................................................................................. 16

CLOCK Register 3 – 0x13. .............................................................................................. 16

CLOCK Register 4 – 0x14. .............................................................................................. 17

CLOCK Register 5 – 0x15. .............................................................................................. 17

CLOCK Register 6 – 0x16. .............................................................................................. 18

CLOCK Register 7 – 0x17. .............................................................................................. 19

CLOCK Register 8 – 0x18. .............................................................................................. 19

CLOCK Register 9 – 0x19. .............................................................................................. 20

CLOCK Register A – 0x1A. ............................................................................................. 20

CLOCK Register B – 0x1B. .............................................................................................. 21

CLOCK Register C – 0x1C. ............................................................................................. 21

CLOCK Register D – 0x1D. ............................................................................................. 22

CLOCK Register E – 0x1E. .............................................................................................. 22

CLOCK Register F – 0x1F. .............................................................................................. 22

CLOCK Register 10 – 0x20. ............................................................................................ 23

CLOCK Register 11 – 0x21. ............................................................................................ 23

User Manual SMT942 Page 3 of 55 Last Edited: 23/08/2011 17:25:00

CLOCK Register 12 – 0x22. ............................................................................................ 23

CLOCK Register 13 – 0x23. ............................................................................................ 24

CLOCK Register 14 – 0x24. ............................................................................................ 25

CLOCK Register 15 – 0x25. ............................................................................................ 25

CLOCK Register 16 – 0x26. ............................................................................................ 25

CLOCK Register 17 – 0x27. ............................................................................................ 26

CLOCK Register 18 – 0x28. ............................................................................................ 27

CLOCK Register 19 – 0x29. ............................................................................................ 27

DAC Chab Register 0 – 0x30. ........................................................................................ 28

DAC Chab Register 1 – 0x31. ........................................................................................ 29

DAC Chab Register 2 – 0x32. ........................................................................................ 30

DAC Chab Register 3 – 0x33. ........................................................................................ 31

DAC Chab Register 4 – 0x34. ........................................................................................ 31

DAC Chab Register 5 – 0x35. ........................................................................................ 32

DAC Chab Register 6 – 0x36. ........................................................................................ 32

DAC Chab Register 7 – 0x37. ........................................................................................ 32

DAC Chab Register 8 – 0x38. ........................................................................................ 33

DAC Chab Register 9 – 0x39. ........................................................................................ 33

DAC Chab Register A – 0x3A. ....................................................................................... 34

DAC Chab Register B – 0x3B. ........................................................................................ 35

DAC Chab Register C – 0x3C......................................................................................... 35

DAC Chab Register D – 0x3D. ....................................................................................... 36

DAC Chab Register D – 0x3D. ....................................................................................... 36

DAC Chab Register E – 0x3E. ........................................................................................ 37

ADC Chab Register 0 – 0x40. ...................................... Error! Bookmark not defined.

ADC Chab Register 1 – 0x41. ...................................... Error! Bookmark not defined.

ADC Chab Register 2 – 0x42. ...................................... Error! Bookmark not defined.

ADC Chab Register 3 – 0x43. ...................................... Error! Bookmark not defined.

ADC Chab Register 4 – 0x44. ...................................... Error! Bookmark not defined.

ADC Chab Register 5 – 0x45. ...................................... Error! Bookmark not defined.

ADC Chab Register 6 – 0x46. ...................................... Error! Bookmark not defined.

ADC Chab Register 7 – 0x47. ...................................... Error! Bookmark not defined.

ADC Chab Register 8 – 0x48. ...................................... Error! Bookmark not defined.

ADC Chab Register 9 – 0x49. ...................................... Error! Bookmark not defined.

5 Footprint ......................................................................................................................... 50

5.1 Top View ..................................................................................................................... 50

5.2 Bottom View ............................................................................................................... 50

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6 Pinout ............................................................................................................................... 51

7 Support Packages ......................................................................................................... 52

8 Physical Properties ....................................................................................................... 53

9 Safety ............................................................................................................................... 54

10 EMC .................................................................................................................................. 55

User Manual SMT942 Page 5 of 55 Last Edited: 23/08/2011 17:25:00

Table of Figures

SLB Base Module (In this case SMT351T)

SMT942 (SLB Mezzanine Module)

Virtex-5

XC5VLX50T, SX50T, SX95T, LX110T

FF1136 Package

Channel A

Signal

Conditioning

(AC-coupling)

Channel B

Signal

Conditioning

(AC-coupling)

DAC Output
Ch A MMCX

50-Ohm

DAC Output
Ch B MMCX

50-Ohm

Daughter Card

interface

connector

SLB

RSLA

ADC ChannelA and

ChannelB

RSLB

DAC ChannelA and

ChannelB

Top and Bottom TIM

Connectors

ChA Data (16)
and Control

Data and Clocks

4xComports (0,1,3 and 4)

DAC5688

Dual Channel DAC

16-bit 800MSPS

Interpolation

(1.3W)

Channel C

Signal

Conditioning

(AC-coupling)

Channel D

Signal

Conditioning

(AC-coupling)

DAC Output
Ch C MMCX

50-Ohm

DAC Output
Ch D MMCX

50-Ohm

DAC5688

Dual Channel DAC

16-bit 800MSPS

Interpolation

(1.3W)

Power

Daughter Card

connector

SLB

ChD Data (16)
and Control

ChC Data (16)
and Control

Bank A

2.5V

Bank B

2.5V

Bank C

2.5V

Power
Supplies: 1.8
and 3.3 Volts

(Linear

Regulators)

Power

Supplies: 1.0,

1.2, 1.8, 2.5

and 3.3 Volts

External Trigger

Clock Synchronizer

and Jitter Cleaner

based on

CDCE72010

(1.8W)

DACs External Clock In

- MMCX

External Reference

Clock In - MMCX

FPGA Clock

ChB Data (16) and
Control

DACs External Clock

Out - MMCX

Data and Clocks

Figure 1 - SMT942 Block diagram. ............................................................................... 10

Figure 2 – Setup Packet Structure. ....................................................................................... 12

Figure 3 – Control Register Read Sequence. ....................................................................... 13

Figure 4 – Register Memory Map. ......................................................................................... 14

Precautions

In order to guarantee that Sundance’s boards function correctly and to protect the
module from damage, the following precautions should be taken:

- They are static sensitive products and should be handled accordingly.

Always place the modules in a static protective bag during storage and transition.

User Manual SMT942 Page 6 of 55 Last Edited: 23/08/2011 17:25:00

Introduction

The SMT942 is a single width expansion TIM that plugs onto an SLB base module,

the SMT351T (Virtex-5 LXT, SXT or even FXT FPGA) as an example and incorporates
2 Texas Instrument dual-channel Digital-to-Analog Converters (DAC5688). The

SMT942 implements a comprehensive clock circuitry based on a chip (CDCE72010)

from Texas instrument that allows synchronisation among the converters and the
use of an external reference clock or sampling clock. It provides a complete
conversion solution and stands as a platform that can be part of a transmit/receive
base station. The SMT942 has an on-board VCXO of frequency 245.76MHz.

DACs have a resolution of 16 bits and are able to update outputs at up to
800MSamples per second. All converters are 1.8/3.3-Volt. Among the features of the
DAC5688 are integrated interpolation filters, a fine frequency mixer with a complex
NCO, a clock multiplier and IQ compensation. No DC-coupled version is currently
available.

The Xilinx FPGA (Virtex-5 LXT or SXT series in the case of the SMT351T) on the base
module is responsible for handling data coming from one of the following sources:

Comports or Rocket Serial Link (RSL). These interfaces are compatible with a wide

range of Sundance’s modules.

The memory (DDR2) on the base module (still based on the case where using an
SMT351T SLB base module) can store outgoing samples.

Converter configuration, sampling and transferring modes are set via internal
control registers stored inside the FPGA and accessible via Comport.

The SMT942 module is well-suited for multi-carrier, wide bandwidth communication
applications.

The main features of the SMT942 are listed below:

● Two Dual 16-bit 800MSPS DAC (DAC5688),

● On-board low-jitter clock distribution chip (CDCE72010),

● On-board 491.52MHz VCXO,

● On-board 10MHz reference crystal,

● One external clock, one external trigger and one reference clock inputs via

MMCX connector,

● One external clock output via MMCX connector,

● One SLB connector to link SMT942 and SMT351T as an example,

● All Analogue inputs to be connected to 50-Ohm sources.

● All Analogue outputs to be connected to 50-Ohm loads.

● Optional fan.

User Manual SMT942 Page 7 of 55 Last Edited: 23/08/2011 17:25:00

1 Related Documents

1.1 Referenced Documents

DAC datasheet: Texas Instrument DAC5688.

Clock datasheet: Texas Instrument CDCE72010.

1.2 Applicable Documents

User Manual SMT942 Last Edited: 23/08/2011 17:25:00

2 Acronyms, Abbreviations and Definitions

2.1 Acronyms and Abbreviations

2.2 Definitions

User Manual SMT942 Last Edited: 23/08/2011 17:25:00

SLB Base Module (In this case SMT351T)

SMT942 (SLB Mezzanine Module)

Virtex-5

XC5VLX50T, SX50T, SX95T, LX110T

FF1136 Package

Channel A

Signal

Conditioning

(AC-coupling)

Channel B

Signal

Conditioning

(AC-coupling)

DAC Output
Ch A MMCX

50-Ohm

DAC Output
Ch B MMCX

50-Ohm

Daughter Card

interface

connector

SLB

RSLA

ADC ChannelA and

ChannelB

RSLB

DAC ChannelA and

ChannelB

Top and Bottom TIM

Connectors

ChA Data (16)
and Control

Data and Clocks

4xComports (0,1,3 and 4)

DAC5688

Dual Channel DAC

16-bit 800MSPS

Interpolation

(1.3W)

Channel C

Signal

Conditioning

(AC-coupling)

Channel D

Signal

Conditioning

(AC-coupling)

DAC Output
Ch C MMCX

50-Ohm

DAC Output
Ch D MMCX

50-Ohm

DAC5688

Dual Channel DAC

16-bit 800MSPS

Interpolation

(1.3W)

Power

Daughter Card

connector

SLB

ChD Data (16)
and Control

ChC Data (16)
and Control

Bank A

2.5V

Bank B

2.5V

Bank C

2.5V

Power
Supplies: 1.8
and 3.3 Volts

(Linear

Regulators)

Power

Supplies: 1.0,

1.2, 1.8, 2.5

and 3.3 Volts

External Trigger

Clock Synchronizer

and Jitter Cleaner

based on

CDCE72010

(1.8W)

DACs External Clock In

- MMCX

External Reference

Clock In - MMCX

FPGA Clock

ChB Data (16) and
Control

DACs External Clock

Out - MMCX

Data and Clocks

3 Functional Description

3.1 Block Diagram

Figure 1 - SMT942 Block diagram.

3.2 Module Description

The SMT943 has got 2 dual channel DACs (DAC5688 – Texas Instrument) that have
integrated 2x-8x interpolation filters, a fine frequency mixer with a 32-bit complex
numerically controlled oscillator, an on-board clock multiplier, an IQ compensation
and an internal voltage reference.

A clock distribution chip ensures that all converters sample synchronously to a
single clock source. The clock source can be external or internal (on-board 245.76­MHz VCXO). The distribution chip also allows synchronising the on-board VCXO to a
reference signal that can be external or internal (on-board 10-MHz crystal). External
reference, external sampling clock input and output are accessible on MMCX
connectors. An external trigger input is also available on the board.

All control, data and clock lines are mapped onto an SLB connector so the card can
be fully controlled by an SLB FPGA base module (SMT351T for example).

Some green LEDs are available on the board. A group of four LEDs is driven directly
from the SLB base FPGA module and can be used to return status bits. Other
indivudual LEDs should be lit and show that local power supplies are on.

User Manual SMT942 Last Edited: 23/08/2011 17:25:00

3.2.1 D/A converters

Analogue Outputs

Output voltage range

1 Vp-p – Full scale - AC coupled

Impedance

DAC single-ended outputs are to be
connected to a 50 load, which impedance
matching implemented between DAC and
RF transformers.

SFDR

89dBs maximum (manufacturer)

SNR

80dBs maximum (manufacturer)

Bandwidth

TBD

DAC Input

Output Data Width per channel

16-Bits

Data Format

2’s Compliment or offset binary
(Changeable via control register)

SFDR

85dBs maximum (manufacturer)

SNR

73dBs maximum (manufacturer)

Maximum input data rate

250 MSPS (Clk1 – DAC5687)

Maximum Sampling rate

500 MSPS (Clk2 – DAC5687)

External Reference Input

Input Voltage Level

1 – 3.3 Volts peak-to-peak (AC-coupled)

Frequency Range

0 – 100 MHz.

External Reference Output

Output Voltage Level

1.6 Volts peak-to-peak (AC-coupled)

Output Impedance

50-Ohm (Termination implemented at the

connector)

External Sampling Clock Input

Input Voltage Level

1.5 – 3.3 Volts peak-to-peak (AC-coupled)

Input Format

Single-ended.

Frequency range

10-500 MHz

External Sampling Clock Output

Output Voltage Level

0-2.4 Volts fixed amplitude

Output Format

LVTTL

External Trigger Inputs

The main characteristics of the SMT942 are gathered into the following table.

Jumper J1 disables (position 1-2; also called External Clock Mode) or enables
(position2-3; also called Internal Clock Mode) the DAC internal PLL.

3.2.2 Clock structure

User Manual SMT942 Page 11 of 55 Last Edited: 23/08/2011 17:25:00

Input Voltage Level

1.5-3.3 Volts peak-to-peak.

Format

DC-coupled and Single-ended (Termination

implemented at the connector). Differential

on option (3.3 V PECL).

Impedance

50-Ohm.

Frequency range

62.5 MHz maximum

Delay

External Ref. Input to Ext Ref. Out

External Clk Input to Ext Clk Out

9ns (between J29 and J4)

Figure 2 - Clock Architecture Main Characteristics.

Byte Content

Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

3

Command

3

Command

2

Command

1

Command

0

Address

11

Address

10

Address 9

Address 8

2

Address 7

Address 6

Address 5

Address 4

Address 3

Address 2

Address 1

Address 0

1

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

3.3 Interface Description

3.3.1 Mechanical Interface

3.3.2 Electrical Interface

3.4 FPGA Design

3.4.1 Control Register Settings

The Control Registers control the complete functionality of the SMT942. They are

setup via the Comport3 (standard firmware provided). The settings of the DACs,
triggers, clocks and the configuration of the interfaces and the internal FPGA data
path settings can be configured via the Control Registers.

3.4.1.1 Control Packet Structure

The data passed on to the SMT942 over the Comport must conform to a certain

packet structure. Only valid packets will be accepted and only after acceptance of a
packet will the appropriate settings be implemented. Each packet will start with a
command (4 bits – 0x1 for a write operation – 0x2 for a read operation) information,
followed by a register address (12 bits – see table Memory Map), followed by a 16-bit
data. This structure is illustrated in the following figure:

Figure 3 – Setup Packet Structure.

User Manual SMT942 Page 12 of 55 Last Edited: 23/08/2011 17:25:00

3.4.1.2 Reading and Writing Registers

Host

Fixed Sequence

SMT942

ComPort 3

Byte 0

Read/Write AddressByte 1
Read/Write DataByte 3
Read/Write DataByte 4

1) Write Packet

Address

Writable Registers

Readable Registers

0x00

Reserved.

Reserved.

0x01

Board Control Register.

Firmware Version.

0x02

Reserved.

Clock Readback Register.

0x03

Reserved.

Board Status Register

Clock Section

0x10

Clock Register 0x0.

Read-back (FPGA Register) Clock Register 0x0.

0x11

Clock Register 0x1.

Read-back (FPGA Register) Clock Register 0x1.

…

…

0x28

Clock Register 0x18.

Read-back (FPGA Register) Clock Register 0x18.

0x29

Clock Register 0x19.

Read-back (FPGA Register) Clock Register 0x19.

0x2A

Clock Readback Address Register (LSB)

0x2B

Clock Readback Address Register (MSB)

DACab Section

0x30

DACab Register 0x0.

Read-back (FPGA Register) DACab Register 0x0.

0x31

DACab Register 0x1.

Read-back (FPGA Register) DACab Register 0x1.

…

...

0x3D

DACab Register 0xD.

Read-back (FPGA Register) DACab Register 0xD.

Control packets are sent to the SMT942 over Comport3. This is a bi-directional

interface. The format of a ‘Read Packet’ is the same as that of a write packet.

Figure 4 – Control Register Read Sequence.

3.4.1.3 Memory Map

The write packets must contain the address where the data must be written to and
the read packets must contain the address where the required data must be read.
The following figure shows the memory map for the writable and readable Control

Registers on the SMT942:

User Manual SMT942 Page 13 of 55 Last Edited: 23/08/2011 17:25:00

0x3E

DACab Register 0xE.

Read-back (FPGA Register) DACab Register 0xE.

DACcd Section

0x40

DACcd Register 0x0.

Read-back (FPGA Register) DACcd Register 0x0.

0x41

DACcd Register 0x1.

Read-back (FPGA Register) DACcd Register 0x1.

…

...

0x4D

DACcd Register 0xD.

Read-back (FPGA Register) DACcd Register 0xD.

0x4E

DACcd Register 0xE.

Read-back (FPGA Register) DACcd Register 0xE.

Figure 5 – Register Memory Map.

Control Register 0x01

Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1

Sync (chcd)

TxEnable

(chcd)

Sync

(chab)

TxEnabl

e (chab)

Chcd_Read

nWrite

Chab_Rea

dnWrite

Clk_Readb
ack

Default

0

Chcd

trigger

selection

Chdc

internal

trigger

Chab

trigger

selectio

n

Chab

internal

trigger

Chcd

update

Chab

update

clk update

Default

‘0’

‘0’

‘0’

‘0’ ‘0’

‘0’

‘0’

Clock Register 0 0x10

Setting

Bit 0

Description clk update clock chip register update

0

0

No action.

1

1

All clock registers are sent to the clock chip via its serial interface.

Setting

Bit 1

Description chab update channel a and b register update

0

0

No action.

1

1

All registers (chab) are sent to the converter via its serial interface.

Setting

Bit 2

Description chcd update channel c and d register update

0

1

No action.

1

1

All registers (chcd) are sent to the converter via its serial interface.

Setting

Bit 4

Description chab Internal trigger

0

0

No action.

1

1

Starts the data flow (converter chab).

Setting

Bit 5

Description chab trigger selection

0

0

Trigger from control register selected.

1

1

Trigger from external source selected.

Setting

Bit 6

Description chcd Internal trigger

0

0

No action.

1

1

Starts the data flow (converter chcd).

Register Descriptions

3.4.2 Control Register 0x1.

User Manual SMT942 Page 14 of 55 Last Edited: 23/08/2011 17:25:00

Setting

Bit 7

Description chcd trigger selection

0

0

Trigger from control register selected.

1

1

Trigger from external source selected.

Clock Register 0 0x10

Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1

Reserved

Reserved

CP_DIR

CP_MODE

DELAY_PFD

REFSELCNTRL

VCXO_AUX_SEL

Default

‘0’

‘0’

‘0’

‘0’

‘00’

‘0’

‘0’

0

SECSEL_PRISEL

Reserved

Reserved

Default

‘00’

‘00’

‘0000’

Clock Register 0 0x10

Setting

Bit 7:6

Description SECSEL_PRISEL Reference Input Selection

0

00

Nothing Selected

1

01

On-board Reference selected

2

10

External Reference selected

3

11

Auto Selection (Not recommended)

Setting

Bit 8

Description VCXO_AUX_SEL VCXO/AUX Selection

0

0

On-board or External Reference. Selected (SECSEL_PRI_SEL)

1

1

On-board VCXO or External Clock selected.

Setting

Bit 9

Description REFSELCNTRL Reference selection mode

0

0

Reference selection made externally.

1

1

Reference selection made internally (using SECSEL_PRISEL.).

Setting

Bit 11:10

Description DELAY_PFD PFD pulse width

0

00

1 01

2 10

3 11

Setting

Bit 12

Description CP_MODE

0

0

3V. 1 1

5V

Setting

Bit 13

Description CP_DIR

0

0

Positive CP current output

1

1

Negative CP current output

Clock Register 1 0x11

CLOCK Register 0 0x10.

CLOCK Register 1 0x11.

User Manual SMT942 Page 15 of 55 Last Edited: 23/08/2011 17:25:00

Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1

Output0 (DAC chc&d clk1) Mode

PECLOHISWING

Reserved

Default

‘100000’

‘0’

‘0’ 0 Reserved

ICP

CP_PRE

Reserved

Default

‘00’

‘0000’

‘0’

‘0’

Reset Register 1 0x11

Setting

Bit 1

Description CP_PRE - Preset charge pump output voltage to vcc/2

0

0

OFF. 1 1

ON.

Setting

Bit 5:2

Description ICP Charge pump current setting

0

0

1 1

Setting

Bit 9

Description PECL0HISWING PECL output voltage swing (DAC chc&d clk1)

0

0

Normal Operation.

1

1

High PECL output voltage.

Setting

Bit 15:10

Description Output0 (DAC chc&d clk1) mode

0

0

LVPECL only: ‘100000’.

Clock Register 2 0x12

Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1

Coarse Phase Adjustment[5:0] (Output DAC chc&d clk1 and clk2)

Reserved

Default

‘000000’

‘00’

0

Reserved

Reserved

Default

‘0011’

‘0001’

Reset Register 2 0x12

Setting

Bit 15:10

Description Coarse Phase Adjustment[5:0] DAC chc&d clk1 and clk2

0

0

1 1

Clock Register 3 0x13

Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1

Output0 (DAC chc&d clk2) Mode

PECL1HISWING

Output

Divider

Enable

CLOCK Register 2 0x12.

CLOCK Register 3 0x13.

User Manual SMT942 Page 16 of 55 Last Edited: 23/08/2011 17:25:00

Default

‘100000’

‘0’

‘0’

0

Output Divider Ratio DAC chc&d clk1 and clk2

Coarse Phase

Adjustment[6]

Default

‘0000000’

‘0’

Reset Register 3 0x13

Setting

Bit 0

Description - Coarse Phase Adjustment[6] DAC chc&d clk1 and clk2

0

0

1 1

Setting

Bit 7:1

Description Output Divider Ratio DAC chc&d clk1 and clk2

0

0

1 1

Setting

Bit 8

Description Output Divider Enable DAC chc&d clk1 and clk2

0

0

Divider disabled.

1

1

Divider enabled.

Setting

Bit 9

Description PECL1HISWING PECL output voltage swing (DAC chc&d clk2)

0

0

Normal Operation.

1

1

High PECL output voltage.

Setting

Bit 15:10

Description Output1 (DAC chc&d clk2) mode

0

0

LVPECL only: ‘100000’.

Clock Register 4 0x14

Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1

Coarse Phase Adjustment[5:0] (Output DAC cha&b clk1)

Delay N[2:1]

Default

‘000000’

‘00’

0

Delay N[0]

Delay M

Reserved

Default

‘0’

‘0’

‘0010’

Reset Register 4 0x14

Setting

Bit 6:4

Description Delay M

0

0

1 1

Setting

Bit 9:7

Description Delay N

0

0

1 1

Setting

Bit 15:10

Description Coarse Phase Adjustment[5:0] DAC cha&b clk1

0

0

1

1

CLOCK Register 4 0x14.

CLOCK Register 5 0x15.

User Manual SMT942 Page 17 of 55 Last Edited: 23/08/2011 17:25:00