Sundance SMT941 User Manual
Sundance Multiprocessor Technology Limited
User Manual
Form : QCF42
Date : 11 February 2009
Unit / Module Description:
Quad ADC SLB Module
Unit / Module Number:
SMT941
Document Issue Number:
2
Issue Date:
Original Author:
PhSR
Sundance Multiprocessor Technology Ltd, Chiltern House,
Waterside, Chesham, Bucks. HP5 1PS.
This document is the property of Sundance and may not be copied
nor communicated to a third party without prior written
permission.
© Sundance Multiprocessor Technology Limited 2009
User Manual
for
SMT941
User Manual SMT941 Last Edited: 23/08/2011 17:24:00
Revision History
Issue
Changes Made
Date
Initials
1
Original document ‘pre-released’.
06/11/2009
PhSR
2
Updates to match v2 PCB
23/03/2010
PhSR
User Manual SMT941 Page 2 of 43 Last Edited: 23/08/2011 17:24:00
Table of Contents
Precautions ................................................................................................................................ 5
Introduction ............................................................................................................................... 6
1 Related Documents ........................................................................................................ 7
1.1 Referenced Documents .............................................................................................. 7
1.2 Applicable Documents ............................................................................................... 7
2 Functional Description .................................................................................................. 8
2.1 Block Diagram.............................................................................................................. 8
2.2 Module Description .................................................................................................... 8
2.2.1 A/D converters ....................................................................................................... 9
2.2.2 Clock structure ..................................................................................................... 10
2.3 FPGA Design ............................................................................................................... 11
2.3.1 Control Register Settings .................................................................................... 11
2.3.2 Register Descriptions .......................................................................................... 13
Control Register – 0x1. ................................................................................................... 13
CLOCK Register 0 – 0x10. .............................................................................................. 14
CLOCK Register 1 – 0x11. .............................................................................................. 15
CLOCK Register 2 – 0x12. .............................................................................................. 15
CLOCK Register 3 – 0x13. .............................................................................................. 15
CLOCK Register 4 – 0x14. .............................................................................................. 16
CLOCK Register 5 – 0x15. .............................................................................................. 17
CLOCK Register 6 – 0x16. .............................................................................................. 17
CLOCK Register 7 – 0x17. .............................................................................................. 18
CLOCK Register 8 – 0x18. .............................................................................................. 18
CLOCK Register 9 – 0x19. .............................................................................................. 19
CLOCK Register A – 0x1A. ............................................................................................. 19
CLOCK Register B – 0x1B. .............................................................................................. 20
CLOCK Register C – 0x1C. ............................................................................................. 20
CLOCK Register D – 0x1D. ............................................................................................. 21
CLOCK Register E – 0x1E. .............................................................................................. 21
CLOCK Register F – 0x1F. .............................................................................................. 21
CLOCK Register 10 – 0x20. ............................................................................................ 22
CLOCK Register 11 – 0x21. ............................................................................................ 22
CLOCK Register 12 – 0x22. ............................................................................................ 22
CLOCK Register 13 – 0x23. ............................................................................................ 23
CLOCK Register 14 – 0x24. ............................................................................................ 23
CLOCK Register 15 – 0x25. ............................................................................................ 24
CLOCK Register 16 – 0x26. ............................................................................................ 24
CLOCK Register 17 – 0x27. ............................................................................................ 25
CLOCK Register 18 – 0x28. ............................................................................................ 26
CLOCK Register 19 – 0x29. ............................................................................................ 26
ADC Chab Register 0 – 0x30. ........................................................................................ 27
ADC Chab Register 1 – 0x31. ........................................................................................ 27
User Manual SMT941 Page 3 of 43 Last Edited: 23/08/2011 17:24:00
ADC Chab Register 2 – 0x32. ........................................................................................ 28
ADC Chab Register 3 – 0x33. ........................................................................................ 28
ADC Chab Register 4 – 0x34. ........................................................................................ 29
ADC Chab Register 5 – 0x35. ........................................................................................ 29
ADC Chab Register 6 – 0x36. ........................................................................................ 30
ADC Chab Register 7 – 0x37. ........................................................................................ 31
ADC Chab Register 8 – 0x38. ........................................................................................ 32
ADC Chab Register 9 – 0x39. ........................................................................................ 32
ADC Chcd Register 0 – 0x40. ........................................................................................ 33
ADC Chcd Register 1 – 0x41. ........................................................................................ 33
ADC Chcd Register 2 – 0x42. ........................................................................................ 34
ADC Chcd Register 3 – 0x43. ........................................................................................ 35
ADC Chcd Register 4 – 0x44. ........................................................................................ 35
ADC Chcd Register 5 – 0x45. ........................................................................................ 36
ADC Chcd Register 6 – 0x46. ........................................................................................ 37
ADC Chcd Register 7 – 0x47. ........................................................................................ 37
ADC Chcd Register 8 – 0x48. ........................................................................................ 38
ADC Chcd Register 9 – 0x49. ........................................................................................ 39
3 PCB Layout ..................................................................................................................... 40
3.1 Top View ..................................................................................................................... 40
3.2 Bottom View ............................................................................................................... 40
4 Connectors ..................................................................................................................... 41
4.1 Description ................................................................................................................. 41
4.2 Location on the board .............................................................................................. 42
5 Physical Properties ....................................................................................................... 43
6 Safety ............................................................................................................................... 43
7 Ordering Information .................................................................................................. 43
8 EMC .................................................................................................................................. 43
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Table of Figures
Figure 1 - SMT942 Block diagram. .......................................................................................... 8
Figure 2 - Clock Structure - Block Diagram ........................................................................ 10
Figure 3 - Clock Architecture Main Characteristics. ......................................................... 11
Figure 4 – Setup Packet Structure. ....................................................................................... 12
Figure 5 – Control Register Read Sequence. ....................................................................... 12
Figure 6 – Register Memory Map. ......................................................................................... 13
Figure 7 - Connectors ............................................................................................................. 42
Precautions
In order to guarantee that Sundance’s boards function correctly and to protect the
module from damage, the following precautions should be taken:
- They are static sensitive products and should be handled accordingly.
Always place the modules in a static protective bag during storage and transition.
User Manual SMT941 Page 5 of 43 Last Edited: 23/08/2011 17:24:00
Introduction
The SMT941 is a single width expansion TIM that plugs onto an SLB base module,
the SMT351T (Virtex-5 LXT, SXT or even FXT FPGA) as an example and incorporates
2 Texas Instrument dual-channel Analog-to-Digital Converters (ADS62P49). The
SMT941 implements a comprehensive clock circuitry based on a distribution chip
(CDCE72010) from Texas Instrument that allows synchronisation among the
converters and the use of an internal/external reference clock or internal/external
sampling clock. It provides a complete conversion solution and stands as a platform
that can be part of a transmit/receive communication platform. The SMT941 has an
on-board VCXO of frequency 245.76MHz.
ADCs have a resolution of 14 bits and are able to update outputs at up to 250MHz.
All converters are 1.8/3.3-Volt. ADCs internal gain and offset can be adjusted as
well as the data format. ADCs are AC-coupled on the board using a doubletransformer structure. No DC-coupled version is currently available.
The Xilinx FPGA (Virtex-5 LXT or SXT series in the case of the SMT351T) on the base
module is responsible for handling data coming from one of the following sources:
Comports or Rocket Serial Link (RSL). These interfaces are compatible with a wide
range of Sundance’s modules.
The memory (DDR2 on SMT351T) on the base module can be used to store incoming
samples.
Converter configuration, sampling and transferring modes are set via internal
control registers stored inside the FPGA and accessible via Comport.
The SMT941 module is well-suited for multi-carrier, wide bandwidth communication
applications.
Note that the SMT941 requires to be coupled with an SLB base module set to work
with 2.5V FPGA IOs.
The main features of the SMT941 are listed below:
● Two Dual 14-bit 250MSPS ADC (ADS62P49),
● On-board low-jitter clock distribution chip (CDCE72010),
● On-board 245.76MHz VCXO,
● On-board 10MHz reference crystal,
● One external clock, and one reference clock inputs via MMCX connector,
● One external clock output via MMCX connector,
● One external trigger input via MMCX connector (can also be used as an
output),
● One SLB connector to link SMT941 and SMT351T as an example,
● All Analogue inputs to be connected to 50-Ohm sources.
● All Analogue outputs to be connected to 50-Ohm loads.
● A fan.
User Manual SMT941 Page 6 of 43 Last Edited: 23/08/2011 17:24:00
1 Related Documents
1.1 Referenced Documents
ADC datasheet: Texas Instrument ADS62P49.
Clock datasheet: Texas Instrument CDCE72010.
1.2 Applicable Documents
User Manual SMT941 Last Edited: 23/08/2011 17:24:00
SLB Base Module (In this case SMT351T)
SMT941 (SLB Mezzanine Module)
Virtex-5
XC5VLX50T, SX50T, SX95T, LX110T
FF1136 Package
Channel A
Signal
Conditioning
(AC-coupling)
Channel B
Signal
Conditioning
(AC-coupling)
ADC Input
Ch A MMCX
50-Ohm
ADC Input
Ch B MMCX
50-Ohm
Daughter Card
interface
connector
SLB
ChA – 1.8V DDR LVDS,
Clock and Control
Data and Clocks
4xComports (0,1,3 and 4)
ADS62P49
Dual ADC ChA&B
14-bit 250MSPS
(2x675mW)
Channel C
Signal
Conditioning
(AC-coupling)
Channel D
Signal
Conditioning
(AC-coupling)
ADC Output
Ch C MMCX
50-Ohm
ADC Output
Ch D MMCX
50-Ohm
ADS62P49
Dual ADC ChA&B
14-bit 250MSPS
(2x675mW)
Power
Daughter Card
connector
SLB
ChD – 1.8V DDR LVDS,
Clock and Control
ChC – 1.8V DDR LVDS,
Clock and Control
Bank A
2.5V
Bank B
2.5V
Bank C
2.5V
Power
Supplies: 1.8
and 3.3 Volts
(Linear
Regulators)
External Trigger
Clock Synchronizer
and Jitter Cleaner
based on
CDCE72010 (1.8W)
ADCs External Clock In
- MMCX
External Reference
Clock In - MMCX
FPGA Clock
ChB – 1.8V DDR LVDS,
Clock and Control
ADCs External Clock
Out - MMCX
Data and Clocks
2 Functional Description
2.1 Block Diagram
2.2 Module Description
The SMT941 has got 2 dual channel Analog-to-Digital converters (ADS62P49 – Texas
Instrument) that have been designed for multi-carrier, wide bandwidth
communication applications. All 4 analog inputs are available on MMCX connectors.
They are 50-Ohm AC-coupled inputs (RF transformers - ration 1). DDR LVDS lines
are used to carry samples through the SLB connector to the FPGA (SLB base module
– FPGA IOs must be 2.5-Volt).
A clock distribution chip ensures that all converters sample synchronously to a
single clock source. The clock source can be external or internal (on-board 245.76-
Figure 1 - SMT942 Block diagram.
User Manual SMT941 Last Edited: 23/08/2011 17:24:00
MHz VCXO). The distribution chip also allows synchronising the on-board VCXO to a
Analogue Inputs
Input voltage range
0dB gain setting : 2.3Vpp - Full scale - AC
coupled
6dB gain setting : 1.15Vpp – Full Scale –
AC-coupled
Programmable input gain via register
(0…6dBs) by steps of 0.5dB (coarse gain)
and steps of 0.134dB (fine gain).
Impedance
Single-ended inputs – to be connected to a
50 (AC) source.
Bandwidth
Tbd – depends on ADC internal input gain.
ADC characteristics
Output Data Width per channel
14 Bits
Data Format
2’s Compliment or offset binary
(Changeable via control register)
SFDR
75 (0-db gain) / 82dBs (6-db gain)
maximum (manufacturer)
SNR
69 (0-db gain) / 66dBs (6-db gain)
maximum (manufacturer)
ENOB
11.3 bits maximum (manufacturer)
Maximum Sampling rate
250 MSPS
(1…100MSPS low speed mode)
(100…250MSPS high speed mode)
Minimum Sampling rate
1 MSPS
reference signal that can be external or internal (on-board 10-MHz crystal). External
reference, external sampling clock input and output are accessible on MMCX
connectors. An external trigger input is also available on the board (it is
implemented as an input in the default firmware provided but can also be
implemented as an output).
All control, data and clock lines are mapped onto an SLB connector so the card can
be fully controlled by an SLB FPGA base module (SMT351T for example, with 2.5Volt FPGA IOs).
Some green LEDs are available on the board. A group of four LEDs is driven directly
from the SLB base FPGA module and can be used to return status bits. Other
indivudual LEDs should be lit and show that local power supplies are on.
2.2.1 A/D converters
The main characteristics of the SMT941 are gathered into the following table.
ADC Analog inputs on the board are single-ended. A double RF transformer
structure is used to provide single-ended to differential conversion. Both
transformers are identical and have a ratio of 1. In order to match the 50-Ohm at
the connector, the output of the second transformer has two 25-Ohm resistors
terminated to the ADC common mode voltage.
User Manual SMT941 Page 9 of 43 Last Edited: 23/08/2011 17:24:00
Clock Synthesizer and Jitter Cleaner - Texas Instrument CDCE72010
U2 - ADC Channel a&b
U7 - Clk Out and FPGA Clk Output (ExtClkOut)
FPGA (SLB)
Clk In
Clk Input (ExtClkIn)
On-board VCXO
254.76 MHz
On-board 10-MHz reference
External Reference (ExtRefIn)
ADC Chc&d – ADS62P49
14-bit 250MSPS
U4 - ADC Channel a&b
ADC Cha&b – ADS62P49
14-bit 250MSPS
External Reference Input
2.2.2 Clock structure
The following diagram shows the clock structure of the SMT941:
The clock distribution chip used on the SMT941 offers 2 reference inputs, a VCXO
differential input and a charge pump to drive the VCXO, as well as a second
differential clock input. ADCs and external clock are mapped to separate internal
output dividers in order to give more flexibility.
The CDCE72010 chip is designed to provide clean, phase related clocks to the
converters. The reference clock (on-board or external) is used to lock the on-board
VCXO using the clock chip PLL/charge pump. It is also possible to feed an external
sampling clock to the chip that can then be distributed the analog converters.
Note that when the board is mounted onto a PXI SLB carrier such as the SMT700
(with 2.5-Volt FPGA IOs), it is possible to feed the 10-MHz reference clock (PXI bus)
to the SMT941 order to lock the VCXO, then creating a local source synchronised to
the rest of the system.
Also to be noted is that a VCXO of a different frequency can be fitted to replace the
standard 245.76-MHz one. It is to be discussed prior to ordering as it is an
operation carried out in the factory.
The table below gathers the characteristics of all clock inputs/outputs:
Figure 2 - Clock Structure - Block Diagram
User Manual SMT941 Page 10 of 43 Last Edited: 23/08/2011 17:24:00
Input Voltage Level
1 – 3.3 Volts peak-to-peak (AC-coupled)
Frequency Range
0 – 100 MHz.
External Reference Output
Output Voltage Level
1.6 Volts peak-to-peak (AC-coupled)
Output Impedance
50-Ohm (Termination implemented at the
connector)
External Sampling Clock Input
Input Voltage Level
1.5 – 3.3 Volts peak-to-peak (AC-coupled)
Input Format
Single-ended.
Frequency range
10-500 MHz
External Sampling Clock Output
Output Voltage Level
0-2.4 Volts fixed amplitude
Output Format
LVTTL
External Trigger Inputs
Input Voltage Level
1.5-3.3 Volts peak-to-peak.
Format
DC-coupled and Single-ended (Termination
implemented at the connector). Differential
on option (3.3 V PECL).
Impedance
50-Ohm.
Frequency range
62.5 MHz maximum
Delay
External Ref. Input to Ext Ref. Out
External Clk Input to Ext Clk Out
9ns (between J29 and J4)
Figure 3 - Clock Architecture Main Characteristics.
Byte Content
2.3 FPGA Design
2.3.1 Control Register Settings
The Control Registers control the complete functionality of the SMT941. They are
setup via the Comport3 (standard firmware provided). The settings of the ADCs,
triggers, clocks and the configuration of the interfaces and the internal FPGA data
path settings can be configured via the Control Registers.
2.3.1.1 Control Packet Structure
The data passed on to the SMT941 over the Comport must conform to a certain
packet structure. Only valid packets will be accepted and only after acceptance of a
packet will the appropriate settings be implemented. Each packet will start with a
command (4 bits – 0x1 for a write operation – 0x2 for a read operation) information,
followed by a register address (12 bits – see table Memory Map), followed by a 16-bit
data. This structure is illustrated in the following figure:
User Manual SMT941 Page 11 of 43 Last Edited: 23/08/2011 17:24:00
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
3
Command
3
Command
2
Command
1
Command
0
Address
11
Address
10
Address 9
Address 8
2
Address 7
Address 6
Address 5
Address 4
Address 3
Address 2
Address 1
Address 0
1
Data 15
Data 14
Data 13
Data 12
Data 11
Data 10
Data 9
Data 8
0
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
Figure 4 – Setup Packet Structure.
Host
Fixed Sequence
SMT941
ComPort 3
Byte 0
Read/Write AddressByte 1
Read/Write DataByte 3
Read/Write DataByte 4
1) Write Packet
Address
Writable Registers
Readable Registers
0x00
Reserved.
Reserved.
0x01
Board Control Register.
Firmware Version.
0x02
Reserved.
Clock Readback Register.
0x03
Reserved.
Board Status Register
Clock Section
0x10
Clock Register 0x0.
Read-back (FPGA Register) Clock Register 0x0.
0x11
Clock Register 0x1.
Read-back (FPGA Register) Clock Register 0x1.
…
…
0x28
Clock Register 0x18.
Read-back (FPGA Register) Clock Register 0x18.
2.3.1.2 Reading and Writing Registers
Control packets are sent to the SMT941 over Comport3. This is a bi-directional
interface. The format of a ‘Read Packet’ is the same as that of a write packet.
Figure 5 – Control Register Read Sequence.
2.3.1.3 Memory Map
The write packets must contain the address where the data must be written to and
the read packets must contain the address where the required data must be read.
The following figure shows the memory map for the writable and readable Control
Registers on the SMT941:
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0x29
Clock Register 0x19.
Read-back (FPGA Register) Clock Register 0x19.
0x2A
Clock Readback Address Register (LSB)
0x2B
Clock Readback Address Register (MSB)
ADCab Section
0x30
ADCab Register 0x0.
Read-back (FPGA Register) ADCab Register 0x0.
0x31
ADCab Register 0x1.
Read-back (FPGA Register) ADCab Register 0x1.
…
...
0x38
ADCab Register 0x8.
Read-back (FPGA Register) ADCab Register 0x8.
0x39
ADCab Register 0x9.
Read-back (FPGA Register) ADCab Register 0x9.
ADCcd Section
0x40
ADCcd Register 0x0.
Read-back (FPGA Register) ADCcd Register 0x0.
0x41
ADCcd Register 0x1.
Read-back (FPGA Register) ADCcd Register 0x1.
…
...
0x48
ADCcd Register 0x8.
Read-back (FPGA Register) ADCcd Register 0x8.
0x49
ADCcd Register 0x9.
Read-back (FPGA Register) ADCcd Register 0x9.
Figure 6 – Register Memory Map.
Control Register 0x01
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
Clk_Readb
ack
Default
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
0
Chcd
trigger
selection
Chdc
internal
trigger
Chab
trigger
selectio
n
Chab
internal
trigger
Chab reset
Chcd
update
(dac)
Chab
update
(adc)
clk update
Default
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
Clock Register 0 0x10
Setting
Bit 0
Description clk update clock chip register update
0
0
No action.
1
1
All clock registers are sent to the clock chip via its serial interface.
Setting
Bit 1
Description chab update channel a and b register update
0
0
No action.
1
1
All registers (chab) are sent to the converter via its serial interface.
Setting
Bit 2
Description chcd update channel c and d register update
0
1
No action.
1
1
All registers (chcd) are sent to the converter via its serial interface.
Setting
Bit 4
Description chab Internal trigger
0
0
No action.
1
1
Starts the data flow (converter chab).
2.3.2 Register Descriptions
Control Register 0x1.
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