Sundance SMT916 User Manual
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User Manual
Twelve 16-bit ADC module (10 MSPS)
SMT916
1.1
08/07/2011
Philippe Robert
for
SMT916
Sundance Multiprocessor Technology Ltd, Chiltern House,
Waterside, Chesham, Bucks. HP5 1PS.
This document is the property of Sundance and may not be copied
nor communicated to a third party without prior written
permission.
© Sundance Multiprocessor Technology Limited 2009
Revision History
Issue Changes Made Date Initials
1 Original document released 06/07/2011 PhSR
1.1 Ordering information added 08/07/2011 PhSR
Table of Contents
1 Introduction ................................................................................................................... 6
2 Related Documents ....................................................................................................... 7
2.1 Referenced Documents .............................................................................................. 7
2.2 Applicable Documents ............................................................................................... 7
3 Functional Description ................................................................................................ 7
3.1 Block Diagram.............................................................................................................. 7
3.2 Module Description .................................................................................................... 8
3.3 Interface Description .................................................................................................. 8
3.3.1 Mechanical Interface .............................................................................................. 8
3.3.2 Electrical Interface ................................................................................................. 8
3.3.2.1 Analogue inputs ............................................................................................ 8
3.3.2.2 Digital Inputs ................................................................................................. 8
3.3.2.3 Digital output ................................................................................................ 9
3.3.2.4 VCC/Ground planes ..................................................................................... 9
3.3.2.5 ADC common mode voltage ....................................................................... 9
3.3.2.6 Input dual opamp structure ..................................................................... 10
3.4 Firmware ..................................................................................................................... 10
3.4.1 FPGA Block Diagram. ........................................................................................... 10
3.4.2 Global Control Register – 0x4 ............................................................................ 11
3.4.3 Global Status Register – 0x4 .............................................................................. 13
3.4.4 Conversion rate register channels 0 to 5 – 0x10. .......................................... 14
3.4.5 Conversion rate register channels 6 to 11 – 0x11. ........................................ 15
Storage Control Register – 0x12 ........................................................................ 15
3.4.6
3.4.7 ADCs Output Format GroupA – 0x13 .............................................................. 17
3.4.8 ADCs Output Format GroupB – 0x14 ............................................................... 17
3.4.9 Led Register – 0x15 .............................................................................................. 17
3.4.10Channel Selection for read back operation – 0x20. ....................................... 18
3.4.11Channel 0 – IODelay – 0x30. .............................................................................. 18
3.4.12Channel 1 – IODelay – 0x31. .............................................................................. 18
3.4.13Channel 2 – IODelay – 0x32. .............................................................................. 19
3.4.14Channel 3 – IODelay – 0x33. .............................................................................. 19
3.4.15Channel 4 – IODelay – 0x34. .............................................................................. 19
3.4.16Channel 5 – IODelay – 0x35. .............................................................................. 20
3.4.17Channel 6 – IODelay – 0x36. .............................................................................. 20
3.4.18Channel 7 – IODelay – 0x37. .............................................................................. 20
3.4.19Channel 8 – IODelay – 0x38. .............................................................................. 20
3.4.20Channel 9 – IODelay – 0x39. .............................................................................. 21
3.4.21Channel 10 – IODelay – 0x3A. ............................................................................ 21
3.4.22Channel 11 – IODelay – 0x3B. ............................................................................ 21
4 Verification Procedures ............................................................................................. 22
Power Consumption – Heat dissipation. ................................................................ 22
5
5.1 AD7626 ADC Chip. ................................................................................................... 22
5.2 Linear regulators. ...................................................................................................... 22
5.3 Clock distribution chips. ......................................................................................... 23
5.4 Power consumption .................................................................................................. 23
6 PCB Layout ................................................................................................................... 23
6.1 ADC Channel .............................................................................................................. 23
6.2 Top Layer .................................................................................................................... 25
6.3 Bottom Layer .............................................................................................................. 25
7 Performance ................................................................................................................. 26
7.1 DC Input – 10MSPS. .................................................................................................. 26
8 Pinout ............................................................................................................................ 27
9 Physical Properties ..................................................................................................... 27
10 Safety ............................................................................................................................. 28
11 Cooling .......................................................................................................................... 28
12 EMC ................................................................................................................................ 28
13 Ordering Information ................................................................................................. 28
Table of Figures
Figure 1 – SMT916 Block Diagram. ........................................................................................ 7
Figure 2 - ADCs common mode voltage. .............................................................................. 9
Figure 3 - ADCs input front-end. .......................................................................................... 10
Figure 4 - Firmware Block Diagram. ..................................................................................... 11
Figure 5 - ADC Channel Layout. ........................................................................................... 24
Figure 6 - Top Layout. ............................................................................................................. 25
Figure 7 - Bottom Layout........................................................................................................ 25
Figure 8 – DC Input distribution - 4k samples - 10MSPS. ................................................ 26
Figure 9 – DC Input - Time domain - 10MSPS. ................................................................... 26
Figure 10 – DC Input - Frequency domain - 10MSPS. ....................................................... 27
Figure 11 - DC Input - Distribution of all 12 channels. .................................................... 27
1 Introduction
The SMT916 is an SLB mezzanine board that incorporates twelve AD7626 ADC chips
from Analog Devices (Two groups of six ADCs, Group A for the first six channels
and Group B for the next six channels). Converters are 16-bit SAR (Successive
Approximation Register), with a maximum throughput of 10MSPS. Analog input
connectors on the board all MMCX.
This module can be mated with one Sundance’s SLB base modules such as the
SMT351T (Virtex5 FPGA, DDR2 memory), SMT372T (Virtex5 FPGA coupled with two
6-core TI DSPs, Ethernet) or SMT700 (Virtex5 FPGA, PXIe bus, USB, Ethernet, SATA).
Note that the Base module is required to be set to 2.5V IOs in order not to damage
the SMT916.
ADCs will be working as two groups of 6 converters, all in ‘self-clocked’ mode. Each
group will be working simultaneously. The FPGA on the SLB base module is
responsible for triggering ADC conversions. The distribution of the conversion
signal will be ensured by two CDCLVD2106 chips from Texas Instrument. It features
low pin to pin skew (below 50ps) and low additive jitter (below 100ps).
Samples are collected by the FPGA using a serial LVDS link. Bits are clocked out of
the ADCs at a speed of 250MHz. Individual state machines synchronised to the
conversion signal ensure this process. The FPGA generates a serial clock that is be
distributed among the converters (2 groups of 6) using an LVDS clock distribution
chip (CDCLVD2106).
The front-end is implemented around 2 amplifiers (Analog Devices) allowing DC
levels. The input impedance will be 50 Ohms (or more depending on option
purchased). An anti-aliasing filter follows the amplifiers before signal reach the
ADCs. Cut-off frequency is half of the maximum ADC sampling rate (5MHz). ADCs
are driven differentially.
When it comes to synchronisation among several modules, an external clock input
(slave mode) and an external clock output (master mode) connectors are present as
well as a SYNC input connector to synchronise state machines between boards. An
external trigger is also present on the board. All four lines are connected to an FPGA
IO and protected by clamping diodes (3.3V). MMCX connectors are used.
2 Related Documents
2.1 Referenced Documents
2.2 Applicable Documents
Analog Devices: AD7626 datasheet
Texas Instrument: CDCLVC2106 datasheet
Sundance: SLB specifications
Sundance: SMT351T
Sundance: SMT372T
Sundance: SMT700
.
.
.
.
.
3 Functional Description
3.1 Block Diagram
AD7626
16 bits - 10 MSPS
Channel 0
AD7626
16 bits - 10 MSPS
Channel 1
PSU ADCs:
12x 2.5-Volts Supplies.
12x 5-Volts Supplies.
MMCX
50-Ohm
MMCX
50-Ohm
Signal
Conditioning
Signal
Conditioning
.
1x LVDS data line
1x LVDS data line
Power
Daughter Card
connector
SLB
Clock Input
(used in Slave mode)
Trigger Input
Sync Input
Clock Output
(used in Master mode)
MMCX
50-Ohm
MMCX
50-Ohm
MMCX
50-Ohm
MMCX
50-Ohm
Group A
Group B
MMCX
50-Ohm
MMCX
50-Ohm
MMCX
50-Ohm
MMCX
50-Ohm
MMCX
50-Ohm
MMCX
50-Ohm
MMCX
50-Ohm
MMCX
50-Ohm
MMCX
50-Ohm
Signal
Conditioning
Signal
Conditioning
Signal
Conditioning
Signal
Conditioning
LVDS Clock Distribution Chip
6 outputs – CDCLVP2106 (1/2)
LVDS Clock Distribution Chip
6 outputs – CDCLVP2106 (2/2)
Signal
Conditioning
Signal
Conditioning
Signal
Conditioning
Signal
Conditioning
Signal
Conditioning
AD7626
16 bits - 10 MSPS
Channel 2
AD7626
16 bits - 10 MSPS
Channel 3
AD7626
16 bits - 10 MSPS
Channel 4
AD7626
16 bits - 10 MSPS
Channel 5
LVDS Clock Distribution Chip
6 outputs – CDCLVP2106 (1/2)
Synchronisation and Clocks – 4 lines
LVDS Clock Distribution Chip
6 outputs – CDCLVP2106 (2/2)
AD7626
16 bits - 10 MSPS
Channel 6
AD7626
16 bits - 10 MSPS
Channel 7
AD7626
16 bits - 10 MSPS
Channel 8
AD7626
16 bits - 10 MSPS
Channel 9
AD7626
16 bits - 10 MSPS
Channel 10
1x LVDS data line
1x LVDS data line
1x LVDS data line
1x LVDS data line
Conversion
1x LVDS data line
1x LVDS data line
1x LVDS data line
1x LVDS data line
1x LVDS data line
Daughter Card
interface
connector
SLB
MMCX
50-Ohm
Signal
Conditioning
AD7626
16 bits - 10 MSPS
Channel 11
1x LVDS data line
Figure 1 – SMT916 Block Diagram.
The above block diagram shows how converters are driven and linked to the SLB
connector.
The FPGA implements states machines to generate conversion pulses. They are then
distributed to both groups (Group A and Group B) of 6 ADCs. Further in the state
machine, eighteen 250MHz clock cycles are generated to get the 16-bit sample out
of the converter (serial LVDS line) – 2 extra bits being used to synchronise data and
the fpga internal clock. This process will be repeated in order to collect more
samples.
The 250-MHz clock is distributed among the converter using a TI distribution chip.
LVDS lines are used between the FPGA, the clock distribution chips and the
analogue converters in order to avoid any noise to be picked up.
3.2 Module Description
Clock distribution chips are all from Texas Instrument. Converters are from Analog
Devices.
All MMCX connectors are accessible from the top of the module.
3.3 Interface Description
3.3.1 Mechanical Interface
The SMT916 comes as an SLB mezzanine module. It is coupled with an SLB base
module. The mezzanine plugs into the base module via an SLB data connector and
an SLB power connector. Some Nylon screws ensure that modules don’t move and
guarantee best connection.
The SMT916 does not follow the SLB specifications in terms of dimensions. The
board area will identical to an standard SLB base module.
3.3.2 Electrical Interface
3.3.2.1 Analogue inputs
All twelve analog inputs will be 50-ohm (other values are available on order)
terminated and accept signals within the range 0-4Volts.
Analog inputs have got parallel diodes used as ESD protection, which will prevent
any input voltage higher than 5 volts to reach the front-end.
3.3.2.2 Digital Inputs
There are 3 digital inputs, External Clock Input, External Trigger Input and External
Sync Input. They are part of the group of 4 connectors (bottom left of the board).
Digital inputs, just like analog inputs have got parallel diodes used as ESD
protection, which will prevent any input voltage higher than 5 volts to reach the
front-end.
A Buffer is used on each line to pass the signal to the FPGA.
Minimum Input levels: 1V peak-to-peak.
Maximum Input Level: 3.3V peak to peak.
Maximum frequency: 200MHz.
3.3.2.3 Digital output
There is one Digital Output, External Sync Out. It is part of the group of 4
connectors (bottom left of the board).
A Buffer is used between the FPGA and the connector.
Output Level: 0-3.3Volts
3.3.2.4 VCC/Ground planes
The module is powered from the SLB power module. Each ADC is connected to an
independent power rail in order to be less likely subject to cross-talk and shared
noises.
Each ADC channel will have its own independent ground plane and independent
power supplies. Each ADC ground plane will join (star type layout) the ‘SLB’ ground
plane in one point using 0-Ohm resistors.
3.3.2.5 ADC common mode voltage
The ADC common mode voltage is divided by 2 in the chip. It is then fed into an
opamp in order to ‘align’ analogue input and ADC internal voltages.
Figure 2 - ADCs common mode voltage.
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