Sundance SMT911 User Manual
Form : QCF42
Date : 11 February 2009
Describes the demo and SMT911 operation.
SMT911
1.0
15 Jan. 10
C. H. Gray
Sundance Multiprocessor Technology Ltd, Chiltern House,
Waterside, Chesham, Bucks. HP5 1PS.
This document is the property of Sundance and may not be copied
nor communicated to a third party without prior written
permission.
© Sundance Multiprocessor Technology Limited 2009
SMT911 User Manual SMT911 Last Edited: 01/06/2010 10:09:00
1.0
Initial Release
15 Jan. 10
CHG
SMT911 User Manual SMT911 Page 2 of 38 Last Edited: 01/06/2010 10:09:00
1.1 Referenced Documents .............................................................................................. 7
2.1 Acronyms and Abbreviations ................................................................................... 8
3.1 Interface Description ................................................................................................ 10
3.1.1 Electrical Description .......................................................................................... 10
3.2 Block Diagram............................................................................................................ 10
3.3 Module Description .................................................................................................. 11
3.3.1 Clock Distribution ................................................................................................ 11
3.3.2 JTAG ........................................................................................................................ 11
3.3.3 Antenna Connectors ............................................................................................ 12
4.1 Functional Overview ................................................................................................. 13
4.2 Control Registers ...................................................................................................... 14
4.2.1 Control Packet Structure .................................................................................... 14
4.2.2 Reading and Writing Registers .......................................................................... 14
4.2.3 Register Map .......................................................................................................... 15
4.3 Running Demo ........................................................................................................... 16
4.3.1 Transmitter ........................................................................................................... 17
4.3.2 Receiver .................................................................................................................. 17
5.1 Top View ..................................................................................................................... 19
5.2 Bottom View ............................................................................................................... 20
6.1 SLB Interface .............................................................................................................. 21
10.1 2.4GHz Frequency Plan and Divider Ratio Programming Words .................... 25
10.2 5GHz Frequency Plan and Divider Ratio Programming Words ........................ 25
10.3 Reset Register 0x00 .................................................................................................. 26
SMT911 User Manual SMT911 Page 3 of 38 Last Edited: 01/06/2010 10:09:00
10.4 Test Register 0x01 .................................................................................................... 26
10.5 Function Register 0 – 0x02 ...................................................................................... 26
10.6 Function Register 1 – 0x03 ...................................................................................... 26
10.7 Function Register 2 – 0x04 ...................................................................................... 27
10.8 MAXIM A Register 0 – 0x05 (Standby) ................................................................... 27
10.9 MAXIM A Register 1 – 0x06 (Integer-Divider Ration) ......................................... 28
10.10 MAXIM A Register 2 – 0x07 (Fractional-Divider Ratio) ...................................... 28
10.11 MAXIM A Register 3 – 0x08 (Band Select and PLL) ............................................. 28
10.12 MAXIM A Register 4 – 0x09 (Calibration) ............................................................. 29
10.13 MAXIM A Register 5 – 0x0A (Low-pass Filter) ..................................................... 29
10.14 MAXIM A Register 6 – 0x0B (RX Control/RSSI) .................................................... 30
10.15 MAXIM A Register 7 – 0x0C (TX Linearity/Gain) ................................................. 30
10.16 MAXIM A Register 8 – 0x0D (RX Gain) .................................................................. 30
10.17 MAXIM A Register 9 – 0x0E (TX VGA Gain) .......................................................... 31
10.18 MAXIM B Register 0 – 0x0F (Standby) ................................................................... 31
10.19 MAXIM B Register 1 – 0x10 (Integer-Divider Ratio) ............................................ 31
10.20 MAXIM B Register 2 – 0x11 (Fractional-Divider Ratio) ....................................... 31
10.21 MAXIM B Register 3 – 0x12 (Band Select and PLL) .............................................. 31
10.22 MAXIM B Register 4 – 0x13 (Calibration) .............................................................. 31
10.23 MAXIM B Register 5 – 0x14 (Low-pass Filter) ...................................................... 31
10.24 MAXIM B Register 6 – 0x15 (RX Control/RSSI) .................................................... 31
10.25 MAXIM B Register 7 – 0x16 (TX Linearity/Gain) ................................................. 31
10.26 MAXIM B Register 8 – 0x17 (RX Gain) ................................................................... 31
10.27 MAXIM B Register 9 – 0x18 (TX VGA Gain) .......................................................... 32
10.28 ADDAC A Register 0 – 0x19 .................................................................................... 32
10.29 ADDAC A Register 1 – 0x1A ................................................................................... 32
10.30 ADDAC A Register 2 – 0x1B .................................................................................... 32
10.31 ADDAC A Register 3 – 0x1C ................................................................................... 33
10.32 ADDAC A Register 4 – 0x1D ................................................................................... 33
10.33 ADDAC A Register 5 – 0x1E .................................................................................... 33
10.34 ADDAC A Register 6 – 0x1F .................................................................................... 34
10.35 ADDAC A Register 7 – 0x20 .................................................................................... 34
10.36 ADDAC A Register 8 – 0x21 .................................................................................... 34
10.37 ADDAC A Register 9 – 0x22 .................................................................................... 35
10.38 ADDAC A Register 10 – 0x23 ................................................................................. 35
10.39 ADDAC A Register 11 – 0x24 ................................................................................. 36
10.40 ADDAC B Register 0 – 0x25 .................................................................................... 36
SMT911 User Manual SMT911 Page 4 of 38 Last Edited: 01/06/2010 10:09:00
10.41 ADDAC B Register 1 – 0x26 .................................................................................... 36
10.42 ADDAC B Register 2 – 0x27 .................................................................................... 36
10.43 ADDAC B Register 3 – 0x28 .................................................................................... 36
10.44 ADDAC B Register 4 – 0x29 .................................................................................... 36
10.45 ADDAC B Register 5 – 0x2A .................................................................................... 36
10.46 ADDAC B Register 6 – 0x2B .................................................................................... 36
10.47 ADDAC B Register 7 – 0x2C .................................................................................... 36
10.48 ADDAC B Register 8 – 0x2D .................................................................................... 36
10.49 ADDAC B Register 9 – 0x2E .................................................................................... 37
10.50 ADDAC B Register 10 – 0x2F .................................................................................. 37
10.51 ADDAC B Register 11 – 0x30 .................................................................................. 37
10.52 Update Register 0x31 ............................................................................................... 37
10.53 Update RSSI Register 0x32 ...................................................................................... 37
10.54 RSSI Register A 0x33 ................................................................................................ 37
10.55 RSSI Register B 0x34 ................................................................................................. 38
SMT911 User Manual SMT911 Page 5 of 38 Last Edited: 01/06/2010 10:09:00
The SMT911 is an advanced, high-quality MIMO transceiver card, designed to cover
all features of future high-speed MIMO radio systems. The SMT911 comprises two
complete, fully configurable transceiver chains between two dual 12-bit digital I/Q
interfaces and two dual-band 50 Ohm antenna ports for each channel.
Each transceiver chain is comprised of an integrated RF-frontend (band switch, T/R
switch and power amplifier), up-/down converters with on chip PLLs and high
performance analog-to-digital and digital-to-analog converters for the I/Q signals
and additional analog-to-digital converters for RSSI conversion.
With a single on-board crystal or externally supplied common reference clock for
the transceiver PLL‟s, multiple SMT911 cards are easily combined to build an
arbitrary size 2m x 2n MIMO system with coherent LO phase. All control signals,
data bits and the SPI bus are routed through a 120-pin QSH data connector
providing for flexible, application specific configuration and control during
operation. The SMT911 is designed to fit on and connect directly to an FPGA base
module like the Sundance SMT351T or SMT368. The provided demo SMT911
Firmware Control Module permits simple and unrestricted access to all control
registers from a user friendly C-Language API.
SMT911 User Manual SMT911 Page 6 of 38 Last Edited: 01/06/2010 10:09:00
SiGe Se2545A23: Dual Band 802.11 Wireless LAN Front End
MAX2828/2829: World-Class Transceiver-IC, MAXIM
AD9863: Analog Devices dual ADC/DAC
Sundance Local Bus: (SLB) specification
ftp2.sundance.com : TIM specification
SMT148FX: Carrier with 4 Module sites
SMT6048: Host-side USB software interface to Sundance hardware
SMT6002: Sundance Flash Programming Utility (FPGA)
SMT911 User Manual SMT911 Last Edited: 01/06/2010 10:09:00
A list of acronyms etc:
http://www.sundance.com/web/files/static.asp?pagename=acc
SMT911 User Manual SMT911 Last Edited: 01/06/2010 10:09:00
The SMT911 is an advanced, high-quality MIMO transceiver card, designed to cover
all features of future high-speed MIMO radio systems. It is used in combination with
Sundance base modules such as the SMT351T.
On the SMT911 transceiver card, two single-chip MIMO RF front-ends (SE2545A23)
are applied, containing nearly all circuitry required between the transceiver and the
antenna. Two transceiver chips of type MAXIM MAX2829 are used to up and downconvert signals between the WLAN carrier bands and the base-band. The MAX2829
is specially designed for MIMO/Smart Antenna application and the IEEE 802.11a/g
standard.
In order to fulfill the requirements of more simple and clever MIMO solutions, the
SMT911 transceiver card is equipped with two built-in ADC/DAC chips from Analog
Devices – AD9863. Each of the transceiver (MAXIM) chips is served by one AD9863.
The AD9863 integrates dual 12-bit ADCs and dual 12-bit DACs. The dual DACs
convert the digital base band I/Q signals to analog signals when the SMT911 card
acts as a transmitter. When the SMT911 card acts as receiver, the dual ADCs convert
the analog base-band I/Q signals into a digital format for the FPGA base board. Two
additional ADC‟s (AD7476) are provided to enable conversion of the Receive Signal
Strength Information (RSSI) from the MAXIM transceivers. All control pins of the
mentioned ICs above are routed through to the base module via the QSH connector. The
firmware on the base module offers the user flexibility to specify control signals and
control register settings. More details about the firmware are explained in the Firmware
implementation section.
The SMT911 card has two external reference clock inputs. These external clock inputs
provide the reference for generating the sampling clock in both ADC/DAC chips, and
provide the transceiver PLL‟s a reference for creating the required 2.4GHz or 5GHz
carrier frequency. Both of these circuits can be run for wider synchronization from
these connectors, or from a fixed, on-board oscillator output of 40MHz. The maximum
clocking speed of the internal ADC‟s is 50MHz, and the maximum clocking speed of the
internal DAC‟s is 200MHz (attainable through internal PLL multiplying).
SMT911 User Manual SMT911 Last Edited: 01/06/2010 10:09:00
• 4 SMA connectors (50 Ohm) for dual-band antennas providing TX/RX
• Two MMCX connectors (50 Ohm) external clock input
• Samtec BKT connector for 5 V and 3.3 V power supply
• 120-pin Samtec QSH connector for all digital I/O signals
• JTAG connector for debug/access to FPGA on base-board.
• Plugs directly into a wide range Sundance SLB TIMs
Each pin on the BKT power connector (33 pins in total) can carry 1.5 A. Digital 5V
(D+5V0), digital 3V3 (D+3V3) and digital ground (DGND) are provided over this
connector. D+3V3 and D+5V0 are assigned four pins each. The daughter card can
thus draw a total of 6A of each of these two supplies.
The major elements of the SMT911 are shown in the block diagram below (single
channel shown).
SMT911 User Manual SMT911 Page 10 of 38 Last Edited: 01/06/2010 10:09:00
Jumper
Both use XTAL
Both use External
XTAL CLKA/External CLKB
External CLKA/XTAL CLKB
CLKA
off
on
off
on
CLKB
off
on
on
off
There are two MMCX connector clock inputs for the SMT911. Clock A provides a
40MHz clock input for the MAXIM transceiver IC‟s. Clock B is the input for both
CLKIN1 and CLKIN 2 of ADC/DAC A and ADC/DAC B. Clock distribution is achieved
by two CDCV304 clock buffer drivers. Because the clock inputs to both pins CLKIN1
and CLKIN2 of the ADC/DAC‟s are shared, the clock provided here cannot exceed
50MHz (the maximum speed of the internal ADC‟s) if switching from TX to RX is the
ultimate goal. To achieve higher frequencies with the DAC‟s, the ADC/DAC‟s
internal PLL circuitry must be implemented to multiply and output the clock onto
IFACE2. This is programmable via SPI up to 200MHz.
For ease of use, a high quality 40MHz crystal has been placed on the mezzanine to
provide clocking for either both MAXIM transceivers, both ADC/DAC‟s, or all four
IC‟s. These configurations are selectable via jumpers 1 and 2.
The clock source is driven by two jumper controlled, multi-function gates that drive
two CDCV304 clock buffers. The jumper marked CLKA will select the source clock
for the MAXIM chip. With no jumper, the defaulted clock source is the onboard
40MHz crystal. With the jumper, the external CLK6 jack (J6) is then the chosen input
for the MAXIM clock. The same arrangement exists for CLKB, the clock source for
the ADDAC chips. If the jumper is attached, an external clock source (J3) is
expected; otherwise, the crystal will output a 40MHz clock to pins CLKIN1 and
CLKIN2 of the ADDAC chips.
The external clock jacks are AC coupled and so do not require any DC offset to
drive this logic. The clock provided to the MAXIM chip if external must be 40MHz
from a quality, stable source. The clock provided to the ADC/DAC chips must be a
quality, clean source and not exceed 50MHz if in a switching TX/RX configuration,
as this source clock feeds the internal ADC and DAC.
A standard Xilinx parallel JTAG header is supplied on the mezzanine to provide access
to the base modules JTAG chain.
SMT911 User Manual SMT911 Page 11 of 38 Last Edited: 01/06/2010 10:09:00
Four SMA antenna jacks are connected directly to the output of two SiGe RF frontend
IC‟s. Each channel shares both band A and band G on the same TX connector,
and both bands on the same RX connector. The antennas should be connected as
described below.
SMT911 User Manual SMT911 Page 12 of 38 Last Edited: 01/06/2010 10:09:00
Loading...