Sundance SMT8091-395VP User Manual

SMT8091_395VP

User Manual

Revision History

Date Comments Engineer Version

02/06/05 First release SM 1.0
02/08/05 Update: support Diamond V3 SM 1.1

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999

Version 1.0 Page 2 of 12 SMT80901_395VP20 User Manual

Table of Contents

Revision History.......................................................................................................... 1

Table of Contents....................................................................................................... 2

Contacting Sundance................................................................................................. 3

Notes..........................................................................................................................3

Precautions................................................................................................................. 3

Outline description...................................................................................................... 4

Architecture ................................................................................................................ 5

Hardware involved...................................................................................................... 6

Hardware installation.................................................................................................. 7

Software applications ............................................................................................... 10

3L application........................................................................................................ 10

Description of the functions in the test software menu.......................................... 11

“ '0' to configure the FPGA and acquire data”.............................................. 11

“ '1' to skip the configuration of the FPGA and acquire data” .................... 11

CPLDReset(): Pulse on Config Line - for FPGA reconfiguring .......................... 11

Configuring internal Registers........................................................................... 11

Capturing data................................................................................................... 11

Matlab application................................................................................................. 12

Power consumption.................................................................................................. 12

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Contacting Sundance

You can contact Sundance for additional information by posting a message in our

online support forum.

To access the support forum, please

register first.

Notes

- SHB stands for Sundance High-speed Bus

- SDB stands for Sundance Digital Bus

- RSL stands for Rocket-IO Serial Link

- Comport denotes an 8-bit communication port following the TI C4x standards

Precautions

In order to guarantee that Sundance’s boards function correctly and to protect the
module from damage, the following precautions should be taken:

- They are static sensitive products and should be handled accordingly.
Always place the modules in a static protective bag during storage and
transition.

- When operating, make sure that the heat generated by the system is

extracted e.g. a fan extracting heat or air blower. It is vital for the SMT391
daughter module.

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Outline description

The SMT8091_395VP is a single-C6416T based module (SMT395VP) combined
with a dual high-speed ADC module (SMT391-VP composed of SMT338-VP and

SMT391).

SMT395VP characteristics:

⇒ Single TMS320C6416T processor running @ 1GHz (32 bits)
⇒ Six 20MB/s communication ports (comports)
⇒ Up to 256MBytes of SDRAM @ 133MHz
⇒ 8MByte Flash ROM for boot code and FPGA programming
⇒ Global expansion connector
⇒ General purpose I/O connector
⇒ High bandwidth data I/O via 2 Sundance High-speed Buses (32-bit SDB

interfaces)

⇒ 8 Rocket Serial links @ 2Gbit/s per lane for inter-module communications

SMT391-VP characteristics:

⇒ Dual 8-bit ADC (

AT84AD001) sampling at up to 1Gsps via LVDS bus (SLB)

⇒ Two Sundance High-speed Bus (SHB) connectors
⇒ Two 4-channel Rocket Serial Link (
⇒ Two 20 MBytes/s communication ports (comport)
⇒ Low-jitter on-board system clock
⇒ Xilinx Virtex-II Pro FPGA (VP30-6)
⇒ 50-Ohm terminated analogue inputs and outputs, external triggers and

clocks via MMCX or MMBX (Huber and Suhner) connectors

⇒ User defined pins for external connections
⇒ Compatible with a wide range of Sundance SHB modules

RSL) connector – 2.5Gbit/s per lane

⇒ TIM standard compatible