Sundance SMT784 User Manual
Sundance Multiprocessor Technology Limited
User Manual
Unit / Module Description: Quad-ADC-14-bit-125Msps System
Unit / Module Number: SMT784
Document Issue Number:
Issue Date:
Original Author: C. H. Gray
Form : QCF42
Date : 11 February 2009
User Manual
for
SMT784
Sundance Multiprocessor Technology Ltd, Chiltern House,
Waterside, Chesham, Bucks. HP5 1PS.
This document is the property of Sundance and may not be copied
nor communicated to a third party without prior written
permission.
© Sundance Multiprocessor Technology Limited 2009
User Manual SMT784 Last Edited: 19/03/2009 14:12:00
Revision History
Issue Changes Made Date Initials
1.0 Original Document 19/03/09 CHG
User Manual SMT784 Page 2 of 31 Last Edited: 19/03/2009 14:12:00
Table of Contents
1 Introduction..................................................................................................................... 6
2 Related Documents........................................................................................................ 7
2.1 Referenced Documents.............................................................................................. 7
2.2 Applicable Documents...............................................................................................7
3 Acronyms, Abbreviations and Definitions.............................................................. 8
3.1 Acronyms and Abbreviations................................................................................... 8
3.2 Definitions.................................................................................................................... 8
4 Functional Description.................................................................................................. 9
4.1 Block Diagram.............................................................................................................. 9
5 System Overview..........................................................................................................11
5.1 FPGA............................................................................................................................11
5.2 SLB Connector............................................................................................................12
5.3 DDR2 ...........................................................................................................................12
5.4 Front Panel Fibre Optic Modules............................................................................ 12
5.5 Front Panel RJ45 Connector (Ethernet)................................................................. 12
5.6 Front Panel SATA Connectors................................................................................12
5.7 RSL............................................................................................................................... 12
5.8 Flash ............................................................................................................................13
5.9 CPLD and FPGA Configuration...............................................................................13
5.10 SHB...............................................................................................................................13
5.11 LEDs.............................................................................................................................13
5.12 Clock Distribution.....................................................................................................14
5.13 ADS5500 ADCs..........................................................................................................15
5.14 Switch 1 Flash Settings ............................................................................................ 17
5.15 ADC Data Flow...........................................................................................................18
6 Software Interface........................................................................................................ 19
6.1 Functional Diagram..................................................................................................19
6.2 Xilinx PCI Core...........................................................................................................20
6.3 Software Driver..........................................................................................................20
6.4 Carrier Board Registers............................................................................................ 20
7 Sample Host Control and Data Capture..................................................................21
7.1 Getting Started .......................................................................................................... 21
7.2 Host Control of SMT784.......................................................................................... 23
7.3 Viewing the Samples ................................................................................................ 24
7.4 Uploading Firmware to Flash.................................................................................. 24
8 SMT784 Board Layout................................................................................................. 26
User Manual SMT784 Page 3 of 31 Last Edited: 19/03/2009 14:12:00
8.1 Top Side of SMT700 Carrier.................................................................................... 26
8.2 Bottom Side of SMT700 Carrier..............................................................................27
8.3 Top Side of SMT384 Mezzanine.............................................................................28
8.4 Bottom Side of SMT384 Mezzanine....................................................................... 29
9 Power and Thermal......................................................................................................30
9.1 Power Dissipation..................................................................................................... 30
10 Safety...............................................................................................................................31
11 EMC .................................................................................................................................. 31
12 Physical Properties....................................................................................................... 31
13 Ordering Information ..................................................................................................31
14 EMC .................................................................................................................................. 31
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Table of Figures
Figure 1: SMT700 Block Diagram ........................................................................................... 9
Figure 2 SMT384 Block Diagram .......................................................................................... 10
Figure 3 JTAG pin-out............................................................................................................ 11
Figure 4 Clock Distribution................................................................................................... 14
Figure 5 ADC Data Flow......................................................................................................... 18
Figure 6 Software Interface to Firmware ............................................................................ 19
Figure 7 SMT784.exe............................................................................................................... 22
Figure 8 ANALYSIS.m..............................................................................................................24
Figure 9 Top-sid of SMT700 Carrier ................................................................................... 26
Figure 10 Bottom-side of SMT700 Carrier......................................................................... 27
Figure 11 Top-side of SMT384 Mezzanine........................................................................ 28
Figure 12 Bottom-side of SMT384 Mezzanine.................................................................. 29
Figure 13 3U Heat Dissipation..............................................................................................30
List of Tables
Table 1 Clock Characteristics ...............................................................................................15
Table 2 ADC Characteristics ................................................................................................. 16
Table 3 Common Configurations of Switch 1.................................................................... 17
Table 4 Register 0x1C Data Control....................................................................................23
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1 Introduction
The SMT784 is a Virtex 5 based PXI form-factor system utilizing Sundance’s
SMT700 carrier board and the SMT384 quad 125MSPS ADC mezzanine board. The
SMT700 implements up to eight 2.5-Gigabit PCI Express lanes, allowing a maximum
data transfer of 2 gigabytes per second. It also implements optionally a 32-bit, 33MHz PCI interface. As a standard, the ADCs are all AC-coupled (RF Transformers),
but can also be optionally DC-coupled (TI opamp THS4509
sampling, and transferring modes are set via internal control registers stored inside
the FPGA and accessible via a Comport interface.
The front panel interfaces make inter-system capabilities extremely extensive, while
the ADC’s and configurable clock distribution attached to the mezzanine module
(SMT384) make processing raw data fast and simple to configure.
Together, the SMT784 is a powerful system for capturing and manipulating data at
high speeds.
Main features of system:
• Xilinx Virtex 5 in an FF1136 package. Supports LX50T/LX85T/SX50T or
LX110T/SX95T.
• FPGA configuration from flash (64MB) using a Xilinx Coolrunner CPLD.
). ADC configuration,
• One 64-bit wide data bank of DDR2 memory. The bank uses 4, 16-bit wide
devices. Running this memory at 220MHz provides a maximum access speed
of over 3.5Gbyte/s.
• Sundance LVDS Bus (SLB) connector for interfacing the SMT700 carrier with
the SMT384 mezzanine. (Future expanded functionality can be achieved as
well by utilizing any one of Sundance’s long line of other mezzanine
modules)
• Front panel SATA connectors carrying Virtex 5 serial interfaces.
• Front panel RJ45 for gigabit Ethernet.
• Front panel Fibre Optic modules carrying Virtex 5 Serial interfaces.
• Sundance Rocket Serial Link (RSL) connector with 4 serial interfaces.
• Front panel USB interface to allow re-programming of the flash memory.
• Four 14-bit, 125MSPS analogue to digital converters.
• Flexible, on-board, low-jitter clock generation.
• One external clock, external triggers, and one reference clock via MMCX
connector.
• All analogue inputs to be connected to 50-ohm sources/loads.
• Mezzanine module temperature sensors.
User Manual SMT784 Page 6 of 31 Last Edited: 19/03/2009 14:12:00
2 Related Documents
Sundance RSL specification: RSL
Xilinx Virtex5 datasheets: Xilinx Virtex5
Texas Instruments ADS550 ADC datasheet: ADS5500
Analog Devices AD9510 datasheet: AD9510
Sundance High-speed Bus (SHB) specifications: SHB
Sundance LVDS Bus (SLB) specifications: SLB
TIM specifications: TIM
MMCX specifications: Surface Mount MMCX
2.1 Referenced Documents
SMT384 User Manual:
X-Link Documentation:
2.2 Applicable Documents
User Manual SMT784 Last Edited: 19/03/2009 14:12:00
3 Acronyms, Abbreviations and Definitions
3.1 Acronyms and Abbreviations
Sundance commonly used acronyms.
MGT, GTP, RSL are all used (interchangeably) and refer to the FPGA’s high speed
serial links.
3.2 Definitions
User Manual SMT784 Last Edited: 19/03/2009 14:12:00
4 Functional Description
4.1 Block Diagram
The major elements of the SMT784 can be broken down into the two main modules
it is comprised of: the SMT700 and SMT384. The SMT700 PXIe carrier board block
diagram can be viewed below.
SMT700 Block Diagram
Ethernet
Ext clk
PXIe ref
USB
Custom Front Panel
Ethernet
PHY
SATA Connectors
2 lanes of RSL
SFF Connectors
2 lanes of Fibre
Clock
generation
Config
CPLD
& USB
512Mbit
flash
2 x 2.5Gb/s
serial links
2 x 2.5Gb/s
serial links
1.5GHz SATA
2.5GHz RSL
SLB
120 I/O pins
Virtex5 LXT-50
FF1136 package
serial links
4 x 2.5Gb/s
1GByte 220MHz
FPGA
DDR2
64 bit data
19 address
13 control
PXI Control
(Trigger, Clk, etc)
8 x 2.5Gb/s
serial links
SHB
PXIe Connector
8 lanes of 2.5Gb/s
(option)
32 bit PCI
33/66MHz
(option)
RSL Connector
4 lanes of 2.5Gb/s
LEDs and
Misc. I/O
Front Panel
Connector
Rear Card
Connector
Figure 1: SMT700 Block Diagram
User Manual SMT784 Last Edited: 19/03/2009 14:12:00
The SMT384 block diagram can be found below.
Figure 2 SMT384 Block Diagram
User Manual SMT784 Page 10 of 31 Last Edited: 19/03/2009 14:12:00
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