Sundance SMT712 User Manual

Sundance Multiprocessor Technology Limited

User Manual

Form : QCF42 Date : 6 July 2006

Unit / Module Description:

Unit / Module Number:

Document Issue Number:

Issue Date:

Original Author:

User Manual

Dual 2.3GHz DAC PXI Express Module

SMT712

11/12/2012

PhSR

for

SMT712

Sundance Multiprocessor Technology Ltd, Chiltern House,

Waterside, Chesham, Bucks. HP5 1PS.

This document is the property of Sundance and may not be copied

nor communicated to a third party without prior written

permission.

User Manual SMT712 Last Edited: 11/12/2012 10:36:00

Revision History

Issue Changes Made Date Initials

1 Original Document released. 02/06/09 PhSR

2 DAC synchronisation function added 01/07/09 PhSR

3 FPGA Design supports xlinks 22/05/10 PhSR

4 Soft Reset added 15/07/10 PhSR

5 Updated for FX100T, SHB phase synchronisation 11/12/12 JV

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Table of Contents

Introduction........................................................................................................................ 8

Related Documents...........................................................................................................9

Acronyms, Abbreviations and Definitions..............................................................10

3.1 Acronyms and Abbreviations ...................................................................................10

Functional Description ..................................................................................................10

4.1 General Block Diagram...............................................................................................10

4.2 Block Diagram – Standard SMT712 (PXIe)..............................................................11

4.3 Block Diagram – SMT712-HYBRPXI32 (option 32-bit PXI)..................................12

4.4 Block Diagram – SMT712-CPCI32 (Option 32-bit PCI).........................................13

4.5 Module Description.....................................................................................................13

4.5.1 DACs..........................................................................................................................13

4.5.2 FPGA ..........................................................................................................................14

4.5.2.1 General Description......................................................................................14

4.5.2.2 Resources used – XCV5FX70T....................................................................14

4.5.2.3 Resources used – XCV5FX100T. ................................................................15

4.5.3 Configuration (CPLD+Flash).................................................................................17

4.5.4 DDR2 Memory .........................................................................................................19

4.5.5 Clock circuitry.........................................................................................................19

4.5.6 Data (samples) path / Data storage....................................................................20

4.5.7 PXI Express Bus.......................................................................................................21

4.5.8 SHB connector .........................................................................................................23

4.5.9 External Trigger. .....................................................................................................23

4.5.10Power dissipation ...................................................................................................24

4.5.11JTAG ..........................................................................................................................24

4.5.12PXI Express Hybrid Connectors...........................................................................26

4.6 FPGA Design .................................................................................................................28

4.6.1 Control Registers....................................................................................................29

4.6.1.1 Register Descriptions...................................................................................32

4.6.1.1.1 General Control Register – 0x08 (read-only). ..................................32

4.6.1.1.2 Set Control Register – 0x10 (write)....................................................35

4.6.1.1.3 DACA (MAX19692) Register 0x1 – Configuration Register – 0x44 (write). 37

4.6.1.1.4 DACB (MAX19692) Register 0x1 – Configuration Register – 0x48 (write). 37

4.6.1.1.5 DACA and B data source selection – 0x4C (write). ........................38

4.6.1.1.6 Clock Generator (AD9516-2) Register 0x00 – Serial Port

Configuration – 0xC0 (write)...................................................................................38

4.6.1.1.7 Clock Generator (AD9516-2) Register 0x04 – Read-back Control –

0XC4 (write). ...............................................................................................................39

4.6.1.1.8 Clock Generator (AD9516-2) Register 0x10 – PFD and Charge

Pump – 0xC8 (write)..................................................................................................39

4.6.1.1.9 Clock Generator (AD9516-2) Register 0x11 – R Counter – 0xCC (write). 40

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4.6.1.1.10 Clock Generator (AD9516-2) Register 0x12 – R Counter – 0xD0 (write). 40

4.6.1.1.11 Clock Generator (AD9516-2) Register 0x13 – A Counter – 0xD4 (write). 41

4.6.1.1.12 Clock Generator (AD9516-2) Register 0x14 – B Counter – 0xD8 (write). 41

4.6.1.1.13 Clock Generator (AD9516-2) Register 0x15 – B Counter – 0xDC (write). 41

4.6.1.1.14 Clock Generator (AD9516-2) Register 0x16 – PLL Control 1 –

0xE0 (write). ................................................................................................................42

4.6.1.1.15 Clock Generator (AD9516-2) Register 0x17 – PLL Control 2 –

0xE4 (write). ................................................................................................................43

4.6.1.1.16 Clock Generator (AD9516-2) Register 0x18 – PLL Control 3 –

0xE8 (write). ................................................................................................................44

4.6.1.1.17 Clock Generator (AD9516-2) Register 0x19 – PLL Control 4 –

0xEC (write).................................................................................................................45

4.6.1.1.18 Clock Generator (AD9516-2) Register 0x1A – PLL Control 5 –

0xF0 (write). ................................................................................................................46

4.6.1.1.19 Clock Generator (AD9516-2) Register 0x1B – PLL Control 6 –

0xF4 (write). ................................................................................................................47

4.6.1.1.20 Clock Generator (AD9516-2) Register 0x1C – PLL Control 7 –

0xF8 (write). ................................................................................................................48

4.6.1.1.21 Clock Generator (AD9516-2) Register 0x1D – PLL Control 8 –

0xFC (write).................................................................................................................49

4.6.1.1.22 Clock Generator (AD9516-2) Register 0x1F – PLL Readback –

0x104 (write)...............................................................................................................50

4.6.1.1.23 Clock Generator (AD9516-2) Register 0xA0 – OUT6 Delay

Bypass – 0x108 (write)..............................................................................................50

4.6.1.1.24 Clock Generator (AD9516-2) Register 0xA1 – OUT6 Delay Full-

scale – 0x10C (write).................................................................................................51

4.6.1.1.25 Clock Generator (AD9516-2) Register 0xA2 – OUT6 Delay

Fraction – 0x110 (write). ..........................................................................................51

4.6.1.1.26 Clock Generator (AD9516-2) Register 0xA3 – OUT7 Delay

Bypass – 0x114 (write)..............................................................................................52

4.6.1.1.27 Clock Generator (AD9516-2) Register 0xA4 – OUT7 Delay Full-

scale – 0x118 (write). ................................................................................................52

4.6.1.1.28 Clock Generator (AD9516-2) Register 0xA5 – OUT7 Delay

Fraction – 0x11C (write)...........................................................................................53

4.6.1.1.29 Clock Generator (AD9516-2) Register 0xA6 – OUT8 Delay

Bypass – 0x120 (write)..............................................................................................53

4.6.1.1.30 Clock Generator (AD9516-2) Register 0xA7 – OUT8 Delay Full-

scale – 0x124 (write). ................................................................................................53

4.6.1.1.31 Clock Generator (AD9516-2) Register 0xA8 – OUT8 Delay

Fraction – 0x128 (write). ..........................................................................................54

4.6.1.1.32 Clock Generator (AD9516-2) Register 0xA9 – OUT9 Delay

Bypass – 0x12C (write). ............................................................................................54

4.6.1.1.33 Clock Generator (AD9516-2) Register 0xAA – OUT9 Delay Full-

scale – 0x130 (write). ................................................................................................54

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4.6.1.1.34 Clock Generator (AD9516-2) Register 0xAB – OUT9 Delay

Fraction – 0x134 (write). ..........................................................................................55

4.6.1.1.35 Clock Generator (AD9516-2) Register 0xF0 – OUT0 – 0x138 (write). 56

4.6.1.1.36 Clock Generator (AD9516-2) Register 0xF1 – OUT1 – 0x13C (write). 56

4.6.1.1.37 Clock Generator (AD9516-2) Register 0xF2 – OUT2 – 0x140 (write). 57

4.6.1.1.38 Clock Generator (AD9516-2) Register 0xF3 – OUT3 – 0x144 (write). 57

4.6.1.1.39 Clock Generator (AD9516-2) Register 0xF4 – OUT4 – 0x148 (write). 58

4.6.1.1.40 Clock Generator (AD9516-2) Register 0xF5 – OUT5 – 0x14C (write). 58

4.6.1.1.41 Clock Generator (AD9516-2) Register 0x140 – OUT6 – 0x150 (write). 59

4.6.1.1.42 Clock Generator (AD9516-2) Register 0x141 – OUT7 – 0x154 (write). 60

4.6.1.1.43 Clock Generator (AD9516-2) Register 0x142 – OUT8 – 0x158 (write). 61

4.6.1.1.44 Clock Generator (AD9516-2) Register 0x143 – OUT9 – 0x15C (write). 61

4.6.1.1.45 Clock Generator (AD9516-2) Register 0x190 – Divider0 – 0x160 (write). 62

4.6.1.1.46 Clock Generator (AD9516-2) Register 0x191 – Divider0 – 0x164 (write). 63

4.6.1.1.47 Clock Generator (AD9516-2) Register 0x192 – Divider0 – 0x168 (write). 63

4.6.1.1.48 Clock Generator (AD9516-2) Register 0x193 – Divider1 – 0x16C (write). 64

4.6.1.1.49 Clock Generator (AD9516-2) Register 0x194 – Divider1 – 0x170 (write). 64

4.6.1.1.50 Clock Generator (AD9516-2) Register 0x195 – Divider1 – 0x174 (write). 65

4.6.1.1.51 Clock Generator (AD9516-2) Register 0x196 – Divider2 – 0x178 (write). 65

4.6.1.1.52 Clock Generator (AD9516-2) Register 0x197 – Divider2 – 0x17C (write). 65

4.6.1.1.53 Clock Generator (AD9516-2) Register 0x198 – Divider2 – 0x180 (write). 66

4.6.1.1.54 Clock Generator (AD9516-2) Register 0x199 – Divider3 – 0x184 (write). 66

4.6.1.1.55 Clock Generator (AD9516-2) Register 0x19A – Divider3 – 0x188 (write). 67

4.6.1.1.56 Clock Generator (AD9516-2) Register 0x19B – Divider3 – 0x18C (write). 67

4.6.1.1.57 Clock Generator (AD9516-2) Register 0x19C – Divider 3 – 0x190 (write). 67

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4.6.1.1.58 Clock Generator (AD9516-2) Register 0x19D – Divider3 – 0x194 (write). 68

4.6.1.1.59 Clock Generator (AD9516-2) Register 0x19E – Divider4 – 0x198 (write). 68

4.6.1.1.60 Clock Generator (AD9516-2) Register 0x19F – Divider4 – 0x19C (write). 69

4.6.1.1.61 Clock Generator (AD9516-2) Register 0x1A0 – Divider4 – 0x1A0 (write). 69

4.6.1.1.62 Clock Generator (AD9516-2) Register 0x1A1 – Divider 4 –

0x1A4 (write). .............................................................................................................69

4.6.1.1.63 Clock Generator (AD9516-2) Register 0x1A2 – Divider4 – 0x1A8 (write). 70

4.6.1.1.64 Clock Generator (AD9516-2) Register 0x1E0 – VCO Divider –

0x1AC (write)..............................................................................................................70

4.6.1.1.65 Clock Generator (AD9516-2) Register 0x1E1 – Input CLKs –

0x1B0 (write)...............................................................................................................71

4.6.1.1.66 System Monitor – FPGA Die Temperatures – 0x1C0 (read)........72

4.6.1.1.67 System Monitor – FPGA Die Temperature thresholds – 0x1C0 (write). 72

4.6.1.1.68 System Monitor – FPGA Core Voltages – 0x1C4 (read). ..............73

4.6.1.1.69 System Monitor – FPGA core voltage thresholds – 0x1C4 (write). 73

4.6.1.1.70 System Monitor – FPGA Aux Voltages – 0x1C8 (read). ...............74

4.6.1.1.71 System Monitor – FPGA aux voltage thresholds – 0x1C8 (write). 74

4.6.1.1.72 DDS Frequency Register DACA – 0x1CC (write)...........................75

4.6.1.1.73 DDS Frequency Register DACB – 0x1D0 (write). ..........................75

4.6.1.1.74 DACA DCM Phase Shifts – 0x1D4 (write).......................................75

4.6.1.1.75 DACB DCM Phase Shifts – 0x1D8 (write). ......................................76

4.6.1.1.76 Pattern size DACA – 0x1DC (write).................................................77

4.6.1.1.77 Pattern size DACB – 0x1E0 (write)...................................................77

4.6.2 DAC Synchronisation.............................................................................................77

4.6.3 External Signal characteristics.............................................................................79

Board Layout ....................................................................................................................81

5.1 Top View........................................................................................................................81

5.2 Bottom View. ................................................................................................................83

5.3 Front panel....................................................................................................................84

Software Packages ..........................................................................................................85

Physical Properties .........................................................................................................87

Safety ..................................................................................................................................88

EMC......................................................................................................................................88

10 Ordering Information.....................................................................................................88

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Table of Figures

Figure 1 - SMT712 General Block Diagram...........................................................................10

Figure 2 - SMT712 Block Diagram – Standard SMT712 (PXIe)..........................................11

Figure 3 - SMT712-HYBRPXI32 Block Diagram (32-bit PXI Option) ................................12

Figure 4 - SMT712-CPCI32 Block Diagram (32-bit CPCI Option) .....................................13

Figure 5 - Configuration (Flash)..............................................................................................17

Figure 6 - SMT712 Clock circuitry..........................................................................................20

Figure 7 - Data path...................................................................................................................21

Figure 8 - Standard SMT712 - PXI Express Peripheral Module.........................................22

Figure 9 - SMT712-HYBRPXI32 - Hybrid Peripheral Slot Compatible PXI-1 Module....22

Figure 10 - SMT712-CPCI32 - Compact PCI Module ...........................................................23

Figure 11 - Forced airflow for a 3U module.........................................................................24

Figure 12 - JTAG Connector.....................................................................................................25

Figure 13 - Photo of a Xilinx Parallel IV cable and its ribbon cable for JTAG

connection ...........................................................................................................................26

Figure 14 - Block Diagram - FPGA Design (standard Firmware)......................................28

Figure 15 – Register Memory Map..........................................................................................32

Figure 16 - Block Diagram - DACs synchronisation process............................................78

Figure 17 – Main Characteristics. ...........................................................................................79

Figure 18 - Capture DACA – Sampling Frequency 2.3 GHz and Output Frequency

143.5 MHz............................................................................................................................80

Figure 19 - Board Layout (Top View)......................................................................................81

Figure 20 - Board picture (Top view) – SMT712. .................................................................82

Figure 21 - Board Layout (Bottom View). ..............................................................................83

Figure 22 - Board picture (bottom view) SMT712. ..............................................................84

Figure 23 - SMT712 Front Panel..............................................................................................85

Figure 24 - SMT712 Demo application..................................................................................86

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1 Introduction

The SMT712 is a PXI Express (opt. Hybrid or CompactPCI) Peripheral Module (3U), which integrates two fast 12-bit DACs, 2 banks of DDR2 memory, a clock circuitry and a Virtex5 Xilinx FPGA, under the 3U format.

The PXIe specification integrates PCI Express signalling into the PXI standard for more backplane bandwidth. It also enhances PXI timing and synchronisation features by incorporating a 100MHz differential reference clock and triggers. The SMT712 can also integrate the standard 32-bit PXI (Hybrid) signalling as an option or a standard 32-bit CompactPCI.

Both DAC chips are identical and can update their output at up 2.3 Giga-samples per second each, with a 12-bit resolution. The manufacturer is Maxim and the part number is MAX19692. Digital-to-Analog converters are clocked by circuitry based on a PLL coupled with a VCO in order to generate a low-jitter fixed signal. The MAX19692 is capable to achieve SFDR figures close to 70dBs. Each DAC integrates settings depending on the type of frequency response required.

The on-board PLL+VCO chip ensure a stable fixed sampling frequency (maximum rate), in order for the board to be used as frequency synthesizer without the need of external clock signal. The PLL will be able to lock the VCO either on the 100MHz PXI express reference (or 10MHz PXI reference depending on option) or on an external reference signal. The sampling clock for the converters can either be coming from the PLL+VCO chip or from an external source. The reference clock selected is also output on a connector in order to pass it to an other module.

The Virtex5 FPGA is responsible for controlling all interfaces, including CPCI (32-bit 33MHz), PXI (32-bit) and PXIe (8 lanes allocated – depending on PXIe chassis, 4 or 8 lanes would be used), as well as routing samples. The SMT712 is populated with an XC5VLX110T-3.

Two DDR2 memory banks are accessible by the FPGA in order to access data on the fly. Both banks are individually clocked at 312 MHz.

One or two SHB connector(s) is(are) available in order to collect data/samples from an other Sundance module (depending on the option). The first SHB connector is available on all versions of the board, whereas the second SHB connector is only available on the non-PCI versions.

All analog connectors on the front panel are SMA.

Examples of application where the SMT712 can be involved in are wideband communication, radar, wireless modem, software radio or waveform generator systems.

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2 Related Documents

1 – Maxim MAX19692: http://www.maxim-ic.com/quick_view2.cfm/qv_pk/5172 2 – Analog Devices AD9516-2:

http://www.analog.com/en/prod/0,2877,AD9516-0,00.html

3 - Virtex5 FPGA: http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/index.htm 4 - PXIe specifications:

http://www.pxisa.org/Spec/PXIEXPRESS_HW_SPEC_R1.PDF

5 – Micron 2Gigabit DDR2 chip

http://download.micron.com/pdf/datasheets/dram/ddr2/2gbddr2.pdf

6 – Sundance xlink presentation:

ftp://ftp2.sundance.com/Pub/documentation/pdf-files/X-Link.pdf

7 – Sundance xlink specifications:

ftp://ftp2.sundance.com/Pub/documentation/pdf-files/D000051S-spec.pdf

MT47H128M16:

User Manual SMT712 Last Edited: 11/12/2012 10:36:00

3 Acronyms, Abbreviations and Definitions

3.1 Acronyms and Abbreviations

PXIe : PXI Express. SNR: Signal-to-Noise Ratio. It is expressed in dBs. It is defined as the ratio of a signal

power to the noise power corrupting the signal. SINAD: Signal-to-Noise Ratio plus Distorsion. Same as SNR but includes harmonics

too (no DC component). ENOB: Effective Number Of Bits. This is an alternative way of defining the Signal-to-

Noise Ratio and Distorsion Ratio (or SINAD). This means that the ADC is equivalent to a perfect ADC of ENOB number of bits.

SFDR: Spurious-Free Dynamic Range. It indicates in dB the ratio between the powers of the converted main signal and the greatest undesired spur.

4 Functional Description

4.1 General Block Diagram

Below is the general block diagram showing all resources available on the board. Note that not all options are implement in the standard firmware.

Figure 1 - SMT712 General Block Diagram.

The following block diagram shows all three options. The first option (PXIe) can be plugged into any PXI Express slot, the second (32-bit PXI) into any Hybrid PXI Express slot and the third can go in any CPCI system.

User Manual SMT712 Last Edited: 11/12/2012 10:36:00

4.2 Block Diagram – Standard SMT712 (PXIe)

Figure 2 - SMT712 Block Diagram – Standard SMT712 (PXIe)

This option implements a PCI Express Endpoint core (Xilinx) based on 4 lanes. It can support up to 8 lanes or only one. The FPGA also has accesses to all PXI triggers and synchronisation signals.

In case the user has in mind to recompile/change the firmware, the PCI Express Core is free and provided by Xilinx. A free license locked on a PC MAC key has to be requested.

The SMT712 (PXIe version) can only be plugged into a PXI Express or CompactPCI Express Rack.

Note that not all resources are implemented in the standard FPGA firmware.

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4.3 Block Diagram – SMT712-HYBRPXI32 (option 32-bit PXI)

Figure 3 - SMT712-HYBRPXI32 Block Diagram (32-bit PXI Option)

This option implements a 32-bit PCI core (33 Mhz). The FPGA also has accesses to all PXI triggers and synchronisation signals.

The PCI core source core cannot be supplied by Sundance as the license held does not cover such use for it. In case the user intends to recompile the source code or design his own firmware, he would have to purchase a license for the core.

The SMT712-HYBRPXI32 can only be plugged into a PXI Express or CompactPCI Express rack.

Note that not all ressoures shown on the above diagram are implemented in the standard firmware.

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4.4 Block Diagram – SMT712-CPCI32 (Option 32-bit PCI)

Figure 4 - SMT712-CPCI32 Block Diagram (32-bit CPCI Option)

This option implements a 32-bit PCI core (33 Mhz). Note that PXI trigger signals and reference clock (10Mhz) are not accessible by the PFGA (not available on a standard CPCI rack). An external reference clock would have to be used.

The PCI core source core cannot be supplied by Sundance as the license held does not cover such use for it.

The SMT712-CPCI32 can be plugged in either a PXI (CompactPCI) or PXI Express rack.

Note that not all resources shown on the above diagram are implemented in the standard firmware.

4.5 Module Description

4.5.1 DACs

The DACs are 12-bit parts from Maxim (MAX19692). On the SMT712, each DAC can achieve up to 2.3 GSPS, via a built-in 4:1 multiplexer.

Both DACs have a selectable frequency response mode, that can be NRZ (NonReturn-to-Zero – high dynamic range and output power in the first Nyquist zone), RZ (Return-to-Zero – this mode trades off SNR for improved gain flatness in the first, second and third Nyquist zones) or RF (Radio Frequency – high SNR and dynamic range in the second and third Nyquist Zones). For more information, please refer to the MAX19692 datasheet (Maxim).

The typical output power of the MAX19692 is -2.6 dBm (50-Ohm – Full scale). These are the manufacturer figures.

Both DACs are AC coupled using RF transformers.

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Each DAC has a heat sink to help the heat dissipation.

4.5.2 FPGA

4.5.2.1 General Description

The FPGA fitted as standard on the SMT712 is part of the Virtex5 LXT family: XC5VLX110T. The package used is FFG1136 and the speed grade -3 (fastest part). For more information about the LXT family, you can visit the Xilinx website.

It is fitted with a heatsink coupled with a fan to keep it within an appropriate range of temperature (no more than 85 ºC) when using the default firmware provided. Nevertheless the board requires some forced cooling. It is recommended to use a PXIe-1062Q chassis or equivalent from National instrument as it already integrates a built-in regulated cooling system. Measurements have been made using a PXIe1062Q on the maximum fan speed setting and the standard firmware with both DACs clocked at 2,3GHz:

In an ambient temperature of 25 ºC, the FPGA die temperature stays close to 60 ºC. In an ambient temperature of 30 ºC, the FPGA die temperature stays close to 70 ºC.

In order to improve the heat dissipation is a system, some slot blockers can be used (from National Instrument), which redirect the air flow of non-used slots to where it is needed.

4.5.2.2 Resources used – XCV5FX70T.

Below is a summary (ISE11.4) of the resources used in the FPGA by the default firmware (Standard SMT712-FX70T):

Slice Logic Utilization:

Number of Slice Registers: 19,258 out of 44,800 42% Number used as Flip Flops: 19,251 Number used as Latches: 1 Number used as Latch-thrus: 6 Number of Slice LUTs: 13,781 out of 44,800 30% Number used as logic: 13,160 out of 44,800 29% Number using O6 output only: 12,075 Number using O5 output only: 457 Number using O5 and O6: 628 Number used as Memory: 417 out of 13,120 3% Number used as Dual Port RAM: 308 Number using O6 output only: 204 Number using O5 output only: 20 Number using O5 and O6: 84 Number used as Shift Register: 109 Number using O6 output only: 109 Number used as exclusive route-thru: 204 Number of route-thrus: 924 Number using O6 output only: 656 Number using O5 output only: 264 Number using O5 and O6: 4 Slice Logic Distribution: Number of occupied Slices: 7,245 out of 11,200 64% Number of LUT Flip Flop pairs used: 22,949 Number with an unused Flip Flop: 3,691 out of 22,949 16% Number with an unused LUT: 9,168 out of 22,949 39% Number of fully used LUT-FF pairs: 10,090 out of 22,949 43%

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Number of unique control sets: 1,143 Number of slice register sites lost to control set restrictions: 2,779 out of 44,800 6% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of clock, reset, set, and enable signals for a registered element. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. OVERMAPPING of BRAM resources should be ignored if the design is over-mapped for a non-BRAM resource or if placement fails.

IO Utilization:

Number of bonded IOBs: 534 out of 640 83% Number of LOCed IOBs: 533 out of 534 99% IOB Flip Flops: 724 IOB Master Pads: 97 IOB Slave Pads: 97 Number of bonded IPADs: 10 out of 50 20% Number of bonded OPADs: 8 out of 32 25% Specific Feature Utilization: Number of BlockRAM/FIFO: 46 out of 148 31% Number using BlockRAM only: 30 Number using FIFO only: 16 Total primitives used: Number of 36k BlockRAM used: 15 Number of 18k BlockRAM used: 17 Number of 36k FIFO used: 14 Number of 18k FIFO used: 2 Total Memory used (KB): 1,386 out of 5,328 26% Number of BUFG/BUFGCTRLs: 26 out of 32 81% Number used as BUFGs: 26 Number of IDELAYCTRLs: 6 out of 22 27% Number of BUFDSs: 1 out of 8 12% Number of BUFIOs: 18 out of 80 22% Number of DCM_ADVs: 8 out of 12 66% Number of LOCed DCM_ADVs: 8 out of 8 100% Number of GTX_DUALs: 2 out of 8 25% Number of LOCed GTX_DUALs: 2 out of 2 100% Number of PCIEs: 1 out of 3 33% Number of LOCed PCIEs: 1 out of 1 100% Number of PLL_ADVs: 1 out of 6 16% Number of SYSMONs: 1 out of 1 100% Number of RPM macros: 128 Average Fanout of Non-Clock Nets: 3.15

4.5.2.3 Resources used – XCV5FX100T.

Below is a summary (ISE14.3) of the resources used in the FPGA by the default firmware (Standard SMT712-FX100T):

Slice Logic Utilization:

Number of Slice Registers: 20,303 out of 64,000 31% Number used as Flip Flops: 20,296 Number used as Latches: 1 Number used as Latch-thrus: 6 Number of Slice LUTs: 14,666 out of 64,000 22% Number used as logic: 13,969 out of 64,000 21% Number using O6 output only: 12,848 Number using O5 output only: 493 Number using O5 and O6: 628 Number used as Memory: 490 out of 19,840 2% Number used as Dual Port RAM: 308

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Number using O6 output only: 204 Number using O5 output only: 20 Number using O5 and O6: 84 Number used as Shift Register: 182 Number using O6 output only: 182 Number used as exclusive route-thru: 207 Number of route-thrus: 892 Number using O6 output only: 698 Number using O5 output only: 193 Number using O5 and O6: 1

Slice Logic Distribution: Number of occupied Slices: 8,232 out of 16,000 51% Number of LUT Flip Flop pairs used: 24,867 Number with an unused Flip Flop: 4,564 out of 24,867 18% Number with an unused LUT: 10,201 out of 24,867 41% Number of fully used LUT-FF pairs: 10,102 out of 24,867 40% Number of unique control sets: 1,027 Number of slice register sites lost to control set restrictions: 2,077 out of 64,000 3%

A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of clock, reset, set, and enable signals for a registered element. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. OVERMAPPING of BRAM resources should be ignored if the design is over-mapped for a non-BRAM resource or if placement fails.

IO Utilization:

Number of bonded IOBs: 536 out of 640 83% Number of LOCed IOBs: 535 out of 536 99% IOB Flip Flops: 726 IOB Master Pads: 97 IOB Slave Pads: 97 Number of bonded IPADs: 10 Number of LOCed IPADs: 2 out of 10 20% Number of bonded OPADs: 8

Specific Feature Utilization: Number of BlockRAM/FIFO: 45 out of 228 19% Number using BlockRAM only: 29 Number using FIFO only: 16 Total primitives used: Number of 36k BlockRAM used: 10 Number of 18k BlockRAM used: 22 Number of 36k FIFO used: 14 Number of 18k FIFO used: 2 Total Memory used (KB): 1,296 out of 8,208 15% Number of BUFG/BUFGCTRLs: 24 out of 32 75% Number used as BUFGs: 24 Number of IDELAYCTRLs: 8 out of 22 36% Number of BUFDSs: 1 out of 8 12% Number of BUFIOs: 16 out of 80 20% Number of DCM_ADVs: 8 out of 12 66% Number of LOCed DCM_ADVs: 8 out of 8 100% Number of GTX_DUALs: 2 out of 8 25% Number of LOCed GTX_DUALs: 2 out of 2 100% Number of PCIEs: 1 out of 3 33% Number of LOCed PCIEs: 1 out of 1 100% Number of PLL_ADVs: 1 out of 6 16%

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Number of SYSMONs: 1 out of 1 100%

Number of RPM macros: 128 Average Fanout of Non-Clock Nets: 3.36

The part mentioned above is also footprint compatible with the SXT series: XC5VSX50T and XC5VSX95T. The SXT series implements a DSP48E core, which if used on the SMT712 may result an increase of the power consumption. Please contact Sundance if you require details about the SXT series.

4.5.3 Configuration (CPLD+Flash)

On the SMT712, the FPGA is connected to a CPLD via a serial link. The CPLD is responsible for controlling read and write operations to and from the Flash memory and to route data to the FPGA configuration port.

The following diagram show how connections are made on the board between the CPLD, the Flash memory and the FPGA:

Flash

Data[7:0]

FPGA

Ctrl[9:0]

Switch

(bitstream

selection)

CPLD

JTAG

Connector

(J8)

Serial Link

jtag

Jtag

Figure 5 - Configuration (Flash).

Configuration Task

A reset coming from the bus (PXI/PCI or PXI Express) triggers a configuration cycle and the FPGA is configured with the default firmware (stored in factory at location

0). The on-board Flash memory (256-Mbit part) is big enough to store several versions

(4 in total on the SMT712) of firmware. A switch (SW1) at the back of the board allows the selection among the 4 locations. It selects the bitstream to be loaded at power up (only switches 1 and 2 of SW1 are used. Each can contain up to 8Mbytes of

Reset

PXIe

Bus or 32-bit

PCI Bus

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data, which is big enough to store an XC5LX110T bitstream (about 3.8 Mbytes) and some text (comments or description of the firmware version).

The user can store a ‘user’ bitstream at location 1 (see table below) for instance using the SMT6002 piece of software (host server to load bitstream into Sundance FPGA modules also called Flash Utility). The SMT6002 also allows adding text based comments above the bitstream in flash memory.

This architecture allows the SMT712 to be used as a development platform for signal processing and algorithms implementation. The function reboot can be used from the SMT6002 GUI to boot from any flash location within seconds.

Both FPGA and CPLD can be reprogrammed/reconfigured at anytime via JTAG (J8 connector – Using a Xilinx parallel/USB programming cable) but it can cause problems as it will break the access to the board from the host. JTAG has a higher priority.

At power up or under a reset on the PXI or PXI Express bus, it takes 140ms for the FPGA (XC5VLX110T-3) to be fully configured and ready to answer the requests from the host.

The following table shows the settings that can be used and the start addresses of the bitstream in the Flash memory.

Position

Switch 2

Position

Switch 1

Bitstream start

address in

Description

flash

ON ON 0x1800000

(Location 3)

User Bitstream 2

loaded at power

ON OFF 0x1000000

(Location 2)

User Bitstream 1

loaded at power

OFF ON 0x0800000

(Location 1)

User bitstream 0

loaded at power

Default

selection

OFF OFF 0x0000000

(Location 0)

Standard

bitstream loaded

at power up

Note that the CPLD routes the contents of the flash starting from the location selected (SW1) until the FPGA indicates that it is configured. Addresses are incremented by a counter that rolls over to 0 when the maximum address is reached. For instance, in the case where Location 1 is selected and a corrupted bitstream is loaded at that location (or if there is no bitstream at that location), the default bitstream will end up being loaded.

The default bitstream returns ‘DEF’ as firmware revision (see register ‘Firmware Version and Revision numbers).

It is recommended to keep the Switch SW1 so the User bitstream 0 is selected and store a custom/user bitstream at Location 1 is needed. The card would then boot from this location. Otherwise the card would boot automatically from the default firmware (Location 0)

Storing a new bitstream using the SMT6002 first involves erasing the appropriate sectors before programming them with the bitstream. This is automatically handled

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by the SMT6002. Storing a new bitstream at location 1 (User Bitstream 0) will only require from the user to select the file (.bit for instance) and to press the ‘Comit’ button. The advanced tab offers more options such as a full erase or a partial erase of the flash memory. None of them should be required in normal mode of operation. Note that a full erase will erase the entire contents of the flash including the default firmware and that it can take up to 3-4 minutes. The partial erase will erase the User bitstreams only.

4.5.4 DDR2 Memory

Two banks of DDR2 memory are available on the SMT712, directly connected to the FPGA. Interfaces are part of the FPGA design. Each bank is 64-bit wide and 128-Meg deep, so each bank can store up to 1 Giga bytes of samples. Each memory bank is dedicated to one DAC. Not all bits are used in the memory are 4 12-bit samples are stored in a 64-bit word.

In the standard firmware provided with the board, both DDR2 interfaces are clocked at 312MHz in order to be able to play back a pattern from the memory to match the full DAC sampling rate.

4.5.5 Clock circuitry

An on-board PLL+VCO chip ensure a stable fixed sampling frequency (maximum rate, i.e. 2300MHz), in order for the board to be used as synthesizer without the need of external clock signal. The PLL will be able to lock the VCO either on the onboard 10MHz PXI reference or the 100MHz PXI express reference or on an external reference signal. The sampling clock for the converters can be either coming from the PLL+VCO chip or from an external source. The chip used is a part from Analog Devices, the AD9516-2. The reference used for locking the VCO is output on a connector available on the front panel.

The selection Internal/External clock is made via a bit in the control register. The same applies to the selection of the reference clock.

Below is a block diagram of the clock circuitry:

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Output

Analog Out

External Clock

‘And’ Gate

‘1’

OUT2

OUT0

Clock Distribution

AD9516-2

Flip

Flop

OUT3

Sync

Pulse

DACB

reference

clock

DAC B

/ s F

Clock Mux

DCM

DACB

with

phase

shift

adjust.

DAC A

Fs/8

Clock Mux

Samples

DACA

reference

clock

Virtex 5 LX110T-3

DCM

DACA

with

phase

shift

adjust.

Samples

Figure 6 - SMT712 Clock circuitry.

On the FPGA side, one Xilinx DCM is implemented per channel. They are used to clock the logic, to be able to change their phase shift to align outgoing data and incoming clock. Both DCM are set in High Frequency Mode. This mode has a limitation in terms of input clock (120 Mhz minimum), which implies a minimum sampling frequency of 960 MSPS.

4.5.6 Data (samples) path / Data storage

This section details how samples can be routed to the DACs. By default and after power-up or reset operation, all interfaces are in reset state. The only exception is for the PXI/PXIe bus interface. Relevant interfaces should first be taken out of the initial reset state.

The next step is to program both DACs and the clock generator and make sure it locked to a reference signal. This is not needed in case of using an external sampling clock. A DAC synchronisation cycle can be run to make sure their Fs/8 output clocks are in phase. DACs are then ready to receive samples and output a clock to the FPGA.

Here are the details of the following step. One Xilinx DCM per DAC clock is used inside the FPGA to ensure a good capture of data. The status of these DCMs should be checked to make sure they are ‘locked’. They are available in the Global Control Register. The DDR2 interface uses some Xilinx specific blocks, such as idelays, DCMs and Phy, which have to be ‘locked’ and ‘ready’ as well. These have to be checked the same way, using the bits available from the Global Control Register.

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Each DAC has a dedicated bank of DDR2 Memory, which can be seen as a Fifo. Both Fifos have status bits to check whether they are empty or full (bit available from Global Control Register). Each Fifo is connected to a DMA channel. DMA channel are implemented as Xlinks. Each FIFO is used in the firmware as a pattern generator. Once samples are written into it, the can be played out in a repetitive way, the size of the pattern is loaded into a register.

The following diagram shows the data path implemented:

4 x 8

( 2

M H z

)

4x8 bits (287.5MHz)

DDR LVDS

Figure 7 - Data path.

Note the data coming from the SHB are coming on 8 bits and casted to 12 bits to match the DAC inputs.

4.5.7 PXI Express Bus

As standard, the SMT712 is a 3U PXI Express peripheral module, which means it comes with two PXI Express connectors: XP4 (PXI timing and synchronisation signals) and XP3 (x8 PCI Express and additional synchronisation signals). The SMT712 dedicates 8 lanes to the PXI Express bus, which gives an effective bandwidth per direction of 16Gb/s. It also implies core and user clocks to be 250 MHz. Note that not all PXIe Express chassis can handle 8 lanes on peripheral modules. The default SMT712 firmware (For PXIe version of the board) only implements 4 lanes.

The standard SMT712 can plug in any PXI Express Peripheral Slot or any PXI Express Hybrid Slot.

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Figure 8 - Standard SMT712 - PXI Express Peripheral Module

Optionally, the module can be a 3U Hybrid Peripheral Slot Compatible PXI-1 Module, means it comes with two connectors: XP4 (PXI timing and synchronisation signals) and P1 (32-bit, 33MHz PCI Signals). This version of SMT712 can only plug in any PXI Express Hybrid Slot

Figure 9 - SMT712-HYBRPXI32 - Hybrid Peripheral Slot Compatible PXI-1 Module

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The SMT712 module can also be a 3U Compact PCI module, which can only be plugged into a CPCI system. It only has one connector fitted: P1 (32-bit, 33MHz PCI signals).

Figure 10 - SMT712-CPCI32 - Compact PCI Module

The FPGA requires a reference clock to implement either the PCI or PCI Express core. The selection is made via J11. The Jumper should be fitted in Position1-2 when a PCI core is used (a 250MHz clock is then available to the FPGA) or in Position2-3 when a PCI Express core is used (the 100-MHz express reference is then routed to the FPGA).

4.5.8 SHB connector

An SHB (1) Connector is available from the FPGA. It maps 32 single-ended data lines and a set of control signals including a clock.

It can be used to transfer samples from an other Sundance module, for instance the SMT702.

A second SHB (2) connector is also available on non-PCI versions of the board. As an example, both SHBs can be used to link an SMT702 and an SMT712 to create a

dual-channel, 2GSPS PXIe platform. SHB clock should match the FPGA clock rate used for DAC (clk/8) and SHB data is

automatically phase shifted to be aligned with internal clock.

4.5.9 External Trigger.

The external trigger function is not implemented in current version of the default firmware.

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4.5.10 Power dissipation

The PXI Express chassis receiving the SMT712 module should provide enough forced air flow in order to dissipate the heat generated by the module. The air flow must be going against gravity or upwards, as specified in the PXI Specification.

The FPGA is fitted with a heatsink to keep it within an appropriate range of temperature (no more than 85 ºC) when using the default firmware provided. Nevertheless the board requires some forced cooling. It is recommended to use a PXIe-1062Q chassis or equivalent from National instrument as it already integrates a built-in regulated cooling system. Measurements have been made using a PXIe1062Q on the maximum fan speed setting and the standard firmware with both DACs clocked at 2,3GHz (both DDR2 memory banks used as a pattern generator):

In an ambient temperature of 25 ºC, the FPGA die temperature stays close to 60 ºC. In an ambient temperature of 30 ºC, the FPGA die temperature stays close to 70 ºC.

In order to improve the heat dissipation is a system, some slot blockers can be used (from National Instrument), which redirect the air flow of non-used slots to where it is needed. Keeping the FPGA die temperature below 70-75 ºC ensures constant performance in time.

The temperature of the FPGA die is available within the register to read-back so it can be monitored.

It is also specified that a 3U PXI Express module should not dissipate more than 30 Watts of heat.

The following picture shows the direction of the forced air flow across a 3U PXI Express module:

Figure 11 - Forced airflow for a 3U module.

A PXI Express rack has a capacity of dissipating 30 watts of heat per slot using forced air-cooling system via typically two 110-cfm fans with filter.

4.5.11 JTAG

A connector (J8) is specifically dedicated for FPGA and CPLD detection and programming. Both the CPLD and the FPGA are part of the JTAG chain. A 14-

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position (2x7) connector (2mm) is available and shows TDI, TDO, TCK and TMS lines, as well as a Ground and a reference voltage, as shown below:

Figure 12 - JTAG Connector.

This connector has been chosen because it can connect easily to a Xilinx Parallel IV cable using the ribbon cable provided by Xilinx. The connector is a Molex part:

87831-1428.

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Molex

Figure 13 - Photo of a Xilinx Parallel IV cable and its ribbon cable for JTAG connection

The JTAG connector should only be needed when reprogramming the CPLD. The FPGA is accessible from the host using the SMT6002 software.

4.5.12 PXI Express Hybrid Connectors

As being a PXI Express Hybrid Peripheral Module, the SMT712 is a 3U card with 2 PXI connectors, XP3, XP4 and P1. The following table shows their pinouts.

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The SMT712 can implement up to eight 2.5-Gigabit PCI Express lanes, allowing a maximum data transfer of 2 gigabytes per second. It also implements optionally a 32-bit, 33-MHz PXI/PCI interface.

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