Sundance SMT702 User Manual
Unit / Module Description:
Unit / Module Number:
Document Issue Number:
Issue Date:
Original Author:
User Manual
Dual 3-GHz PXIe ADC Module
SMT702
8
11/12/12
PhSR
for
SMT702
Sundance Multiprocessor Technology Ltd, Chiltern House,
Waterside, Chesham, Bucks. HP5 1PS.
This document is the property of Sundance and may not be copied
nor communicated to a third party without prior written
permission.
© Sundance Multiprocessor Technology Limited 2006
Revision History
Issue Changes Made Date Initials
1 Original Document released 12/09/08 PhSR
2 DMA and system monitor added 30/01/09 PhSR
3 ADCs Output characteristics updated. Ordering
information updated with FX70t part.
4 FPGA Design supports Xlinks. 06/05/10 PhSR
5 Added missing currents; Added weight. 22/05/10 PhSR
6 Soft Reset added in the control register. 14/07/10 PhSR
7 Comment added on board modification (ADC
reset)
8 Added FX100T version 11/12/12 JV
01/12/09 PhSR
27/07/10 PhSR
Table of Contents
1
Introduction........................................................................................................................ 7
2
Related Documents...........................................................................................................8
2.1 Referenced Documents ................................................................................................ 8
3
Acronyms, Abbreviations and Definitions................................................................8
3.1 Acronyms and Abbreviations .....................................................................................8
4
Functional Description ....................................................................................................9
4.1 General Block Diagram.................................................................................................9
4.2 Block Diagram - Standard SMT702 (PXIe) ..............................................................10
4.3 Block Diagram – SMT702-HYBRPXI32 (option 32-bit PXI)..................................11
4.1 Block Diagram – SMT702-CPCI32 (Option 32-bit PCI).........................................12
4.2 Module Description.....................................................................................................13
4.2.1 ADCs..........................................................................................................................13
4.2.2 FPGA ..........................................................................................................................13
4.2.2.1 General Description......................................................................................13
4.2.2.2 Resources used – XC5VLX110T. ................................................................13
4.2.2.3 Resources used – XCV5FX70T....................................................................15
4.2.2.4 Resources used – XCV5FX100T. ................................................................16
4.2.3 Configuration (CPLD+Flash).................................................................................18
4.2.4 DDR2 Memory .........................................................................................................19
4.2.5 Clock circuitry.........................................................................................................20
4.2.6 Data (samples) path / Data capture...................................................................21
4.2.7 PXI Express Bus.......................................................................................................22
4.2.8 SHB Connector ........................................................................................................24
4.2.9 Power dissipation ...................................................................................................24
4.2.10JTAG ..........................................................................................................................25
4.2.11PXI Express Hybrid Connectors...........................................................................27
4.3 FPGA Design .................................................................................................................28
4.3.1 Control Registers....................................................................................................28
4.3.1.1 Memory Map...................................................................................................28
4.3.1.2 Register Descriptions...................................................................................31
4.3.1.2.1 General Control Register – 0x8 (read-only)......................................31
4.3.1.2.2 Set Control Register – 0x10 (write)....................................................34
4.3.1.2.3 Clear Control Register – 0x20 (write)................................................36
4.3.1.2.4 Board Name and Version – 0x24 (read-only)...................................36
4.3.1.2.5 Firmware Version and Revision Numbers – 0x40 (read-only). ....36
4.3.1.2.6 ADCA (ADC083000) Register 0x1 – Configuration Register –
0x44 (write). ................................................................................................................37
4.3.1.2.7 ADCA (ADC083000) Register 0x2 – Offset Adjust – 0x48 (write
and read). 37
4.3.1.2.8 ADCA (ADC083000) Register 0x3 – Full Scale Voltage Adjust –
0x4C (write and read). ..............................................................................................38
4.3.1.2.9 ADCA (ADC083000) Register 0xD – Extended Clock Phase Adjust
Fine – 0x74 (write and read)....................................................................................38
4.3.1.2.10 ADCA (ADC083000) Register 0xE – Extended Clock Phase
Adjust Coarse – 0x78 (write and read).................................................................39
4.3.1.2.11 ADCA (ADC083000) Register 0xF – Test Pattern register – 0x7C
(write and read)..........................................................................................................39
4.3.1.2.12 ADCB (ADC083000) Register 0x1 – Configuration Register –
0x84 (write and read)................................................................................................40
4.3.1.2.13 ADCB (ADC083000) Register 0x2 – Offset Adjust – 0x88 (write
and read). 41
4.3.1.2.14 ADCB (ADC083000) Register 0x3 – Full Scale Voltage Adjust –
0x8C (write and read). ..............................................................................................41
4.3.1.2.15 ADCB (ADC083000) Register 0xD – Extended Clock Phase
Adjust Fine 0xB4 (write and read).........................................................................42
4.3.1.2.16 ADCB (ADC083000) Register 0xE – Extended Clock Phase
Adjust Coarse – 0xB8 (write and read).................................................................42
4.3.1.2.17 ADCB (ADC083000) Register 0xF – Test Pattern register – 0xBC
(write and read)..........................................................................................................43
4.3.1.2.18 Frequency Synthesizer (LMX2531) Register R0 – 0xC0 (write and
read). 43
4.3.1.2.19 Frequency Synthesizer (LMX2531) Register R1 – 0xC4 (write and
read). 44
4.3.1.2.20 Frequency Synthesizer (LMX2531) Register R2 – 0xC8 (write and
read). 44
4.3.1.2.21 Frequency Synthesizer (LMX2531) Register R3 – 0xCC (write
and read). 45
4.3.1.2.22 Frequency Synthesizer (LMX2531) Register R4 – 0xD0 (write
and read). 45
4.3.1.2.23 Frequency Synthesizer (LMX2531) Register R5 – 0xD4 (write
and read). 46
4.3.1.2.24 Frequency Synthesizer (LMX2531) Register R6 – 0xD8 (write
and read). 47
4.3.1.2.25 Frequency Synthesizer (LMX2531) Register R7 – 0xDC (write
and read). 48
4.3.1.2.26 Frequency Synthesizer (LMX2531) Register R8 – 0xE0 (write and
read). 48
4.3.1.2.27 Frequency Synthesizer (LMX2531) Register R9 – 0xE4 (write and
read). 49
4.3.1.2.28 Frequency Synthesizer (LMX2531) Register R12 - 0xE8 (write
and read). 49
4.3.1.2.29 ADCA – DCM Phase Shift – 0x108 (write). .....................................50
4.3.1.2.30 ADCB – DCM Phase Shift – 0x10C (write).......................................50
4.3.1.2.31 System Monitor – FPGA Die Temperatures – 0x180 (read)........51
4.3.1.2.32 System Monitor – FPGA Die Temperature thresholds – 0x180
(write). 51
4.3.1.2.33 System Monitor – FPGA Core Voltages – 0x184 (read)................52
4.3.1.2.34 System Monitor – FPGA core voltage thresholds – 0x184 (write).
52
4.3.1.2.35 System Monitor – FPGA Aux Voltages – 0x188 (read).................53
4.3.1.2.36 System Monitor – FPGA aux voltage thresholds – 0x188 (write).
53
4.3.1.2.37 Amount of samples stored in DDR2 – Bank A – 0x18C (write).54
4.3.1.2.38 Amount of samples stored in DDR2 – Bank B – 0x190 (write). 54
4.3.2 System Monitor. ......................................................................................................54
4.3.3 External Signal characteristics.............................................................................55
5
Board Layout ....................................................................................................................57
5.1 Top View........................................................................................................................57
5.2 Bottom View..................................................................................................................58
6
Photo...................................................................................................................................59
6.1 Overview of the board................................................................................................59
6.2 Front panel....................................................................................................................61
6.3 How is it going to stand on your desk?..................................................................61
7
Software Packages ..........................................................................................................62
8
Physical Properties .........................................................................................................64
9
Hardware Modification..................................................................................................65
10 Safety ..................................................................................................................................66
11 EMC......................................................................................................................................66
12 Ordering Information.....................................................................................................66
Table of Figures
Figure 1 - SMT702 General Block Diagram............................................................................. 9
Figure 2 - SMT702 Block Diagram (Standard SMT702 - PXI Express).............................10
Figure 3 - SMT702 Block Diagram (32-bit PXI Option).......................................................11
Figure 4 - SMT702-CPCI32 Block Diagram (32-bit CPCI Option) .....................................12
Figure 5 - Configuration (Flash)..............................................................................................18
Figure 6 - Clock circuitry Block Diagram..............................................................................21
Figure 7 - Data (samples) path. ...............................................................................................22
Figure 8 - Standard SMT702 - PXI Express Peripheral Module.........................................23
Figure 9 - SMT702-HYBRPXI32 (opt.) - Hybrid Peripheral Slot Compatible PXI-1
Module..................................................................................................................................23
Figure 10 - Forced airflow for a 3U module.........................................................................24
Figure 11 - JTAG Connector.....................................................................................................25
Figure 12 - Photo of a Xilinx Parallel IV cable and its ribbon cable for JTAG
connection ...........................................................................................................................26
Figure 13 - Block Diagram - FPGA Design (standard Firmware)......................................28
Figure 14 – Register Memory Map..........................................................................................30
Figure 15 – Main Characteristics. ...........................................................................................56
Figure 16 - Board Layout (Top View)......................................................................................57
Figure 17 - Board Layout (Bottom View) ...............................................................................58
Figure 18 - Overview of the board..........................................................................................60
Figure 19 - SMT702 Front Panel..............................................................................................61
Figure 20 - SMT702 - PXI Express Chassis............................................................................61
Figure 21 - SMT702 Demo application..................................................................................63
Figure 22 - ADC Reset structure modification. ...................................................................65
1 Introduction
The SMT702 is a PXI Express (opt. Hybrid) Peripheral Module (3U), which integrates
two fast 8-bit ADCs, a clock circuitry, 2 banks of DDR2 Memory (1GByte each), IO
connectors (2 SHBs, SATA and RSL) and a Virtex5 Xilinx FPGA, under the 3U format.
The PXIe specification integrates PCI Express signalling into the PXI standard for
more backplane bandwidth. It also enhances PXI timing and synchronisation
features by incorporating a 100MHz differential reference clock and triggers. The
SMT702 can also integrate the standard 32-bit PXI signalling as an option.
Both ADC chips are identical and can produce 3 Giga-samples per second each, with
an 8-bit resolution. The manufacturer is National Semiconductor and the part
number is ADC083000. Analog-to-Digital converters are clocked by circuitry based
on a PLL coupled with a VCO in order to generate a low-jitter signal. Each ADC
integrates settings such as offset and scale factor, which makes the pair of ADC
suitable to be combined together in order to make a 6GSPS single Analog to Digital
converter. This will be subject to a specific FPGA design.
An on-board PLL+VCO chip ensures a stable fixed sampling frequency (maximum
rate), in order for the board to be used as a digitiser without the need of external
clock signal. The PLL will be able to lock its internal VCO either on the 100MHz PXI
express reference, on the 10MHz PXI reference or on an external reference signal.
The sampling clock for the converters can be either coming from the PLL+VCO chip
(fixed frequency of 1.5ghz) or from an external source. The chip used is a National
Semiconductor part: LMX2531LQ1500. The reference clock selected is also output
on a connector in order to pass it to an other module.
The Virtex5 FPGA is responsible for controlling all interfaces, including PXI (32-bit)
and PXIe (up to 8 lanes – not all PXI Express controller support 8 lane), as well as
routing samples. The FPGA fitted on the SMT702 is part of the Virtex-5 familly from
Xilinx, XC5VLX110T-3 (fastest speed grade available).
Two DDR2 memory banks are accessible by the FPGA in order to store data on the
fly. Each bank can store up to 1GByte.
An SHB connector is available in order to transfer data/samples to an other
Sundance module (SMT712 for instance)
All analog connectors on the front panel are SMA.
2 Related Documents
2.1 Referenced Documents
1 - National Semiconductor ADC083000:
http://www.national.com/pf/DC/ADC083000.html
2 – National Semiconductor LMX2531LQ1500:
http://www.national.com/pf/LM/LMX2531LQ1500E.html
3 - Virtex5 FPGA:
http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/index.htm
4 - PXIe specifications: http://www.pxisa.org/Spec/PXIEXPRESS_HW_SPEC_R1.PDF
5 – Micron 2Gigabit DDR2 chip
http://download.micron.com/pdf/datasheets/dram/ddr2/2gbddr2.pdf
6 – Sundance xlink presentation:
ftp://ftp2.sundance.com/Pub/documentation/pdf-files/X-Link.pdf
7 – Sundance xlink specifications:
ftp://ftp2.sundance.com/Pub/documentation/pdf-files/D000051S-spec.pdf
MT47H128M16:
3 Acronyms, Abbreviations and Definitions
3.1 Acronyms and Abbreviations
PXIe : PXI Express.
SNR: Signal-to-Noise Ratio. It is expressed in dBs. It is defined as the ratio of a signal
power to the noise power corrupting the signal.
SINAD: Signal-to-Noise Ratio plus Distorsion. Same as SNR but includes harmonics
too (no DC component).
ENOB: Effective Number Of Bits. This is an alternative way of defining the Signal-to-
Noise Ratio and Distorsion Ratio (or SINAD). This means that the ADC is equivalent
to a perfect ADC of ENOB number of bits.
SFDR: Spurious-Free Dynamic Range. It indicates in dB the ratio between the powers
of the converted main signal and the greatest undesired spur.
4 Functional Description
4.1 General Block Diagram
Below is the general block diagram showing all resources available on the board.
Note that not all option are implement in the standard firmware.
Figure 1 - SMT702 General Block Diagram.
The following block diagram shows all three options. The first option (PXIe) can be
plugged into any PXI Express slot, the second (32-bit PXI) into any Hybrid PXI
Express slot and the third can go in any CPCI system.
4.2 Block Diagram - Standard SMT702 (PXIe)
Figure 2 - SMT702 Block Diagram (Standard SMT702 - PXI Express)
This option implements a PCI Express Endpoint core (Xilinx) based on 4 lanes. It can
support up to 8 lanes or only one. The FPGA also has accesses to all PXI triggers and
synchronisation signals.
In case the user has in mind to recompile/change the firmware, the PCI Express Core
is free and provided by Xilinx. A free license locked on a PC MAC key has to be
requested.
The SMT702 (PXIe version) can only be plugged into a PXI Express or CompactPCI
Express Rack.
Note that not all resources are implemented in the standard FPGA firmware.
4.3 Block Diagram – SMT702-HYBRPXI32 (option 32-bit PXI)
Figure 3 - SMT702 Block Diagram (32-bit PXI Option)
This option implements a 32-bit PCI core (33 Mhz). The FPGA also has accesses to all
PXI triggers and synchronisation signals.
The PCI core source core cannot be supplied by Sundance as the license held does
not cover such use for it. In case the user intends to recompile the source code or
design his own firmware, he would have to purchase a license for the core.
The SMT702-HYBRPXI32 can only be plugged into a PXI Express or CompactPCI
Express rack.
Note that not all ressoures shown on the above diagram are implemented in the
standard firmware.
4.1 Block Diagram – SMT702-CPCI32 (Option 32-bit PCI)
Figure 4 - SMT702-CPCI32 Block Diagram (32-bit CPCI Option)
This option implements a 32-bit PCI core (33 Mhz). Note that PXI trigger signals and
reference clock (10Mhz) are not accessible by the PFGA (not available on a standard
CPCI rack). An external reference clock would have to be used or an external clock
to feed the converter with.
The PCI core source core cannot be supplied by Sundance as the license held does
not cover such use for it.
The SMT702-CPCI32 can be plugged in either a PXI (CompactPCI) or PXI Express
rack.
Note that not all resources shown on the above diagram are implemented in the
standard firmware.
4.2 Module Description
4.2.1 ADCs
The ADCs are 8-bit parts from National Semiconductor (ADC083000). On the
SMT702, each ADC can achieve up to 3 GSPS, in DDR mode.
Both ADCs are used in the extended mode. For more information, please refer to the
ADC083000 datasheet (National Semiconductor). This implies that they are
configured using a Serial Interface implemented in the FPGA.
The typical Bit Error Rate (BER) of the ADC083000 is 10
Each ADC takes a DDR clock, i.e. to achieve 3GSPS, a clock of 1.5Ghz is required.
The ADCs can only work with a DDR clock within the range 500-1500MHz, which
means they can sample at a rate between 1 and 3 GSPS.
Both ADCs are AC-coupled using an RF Transformer.
They have functionalities such as offset and scale adjustments, as well as test
pattern mode. There is also calibration cycle that can be run once the system is in
temperature.
The FPGA is able to synchronise the ADCs so they samples in phase. The FPGA is
able to return the phase shift between ADCA and ADCB to the host application by
sampling their clock with its local clock and phase shifting it with a DCM.
4.2.2 FPGA
-18
.
4.2.2.1 General Description
The FPGA fitted as standard on the SMT702 is part of the Virtex5 LXT family:
XC5VLX110T. The package used if FFG1136 and the speed grade is -3 (fastest part).
The SMT702 can also receive an FPGA from the Virtex5 FXT family (XC5VFX70T and
XC5VFX100T in the same package).
The FPGA is fitted with a heatsink coupled with a fan to keep it within an
appropriate range of temperature when using the default firmware provided.
Nevertheless the board requires some forced cooling. It is recommended to use a
PXI-1062Q chassis or equivalent from National instrument as it already integrates a
built-in cooling system. Using slot blockers from National Instrument would
improve even more the cooling capacity of the system.
In order to improve the heat dissipation is a system, some slot blockers can be used
(from National Instrument), which redirect the air flow of non-used slots to where it
is needed.
4.2.2.2 Resources used – XC5VLX110T.
Below is a summary (ISE11.4) of the resources used in the FPGA by the default
firmware (Standard SMT702 – XCV5VLX110T FPGA – PXIe option):
Slice Logic Utilization:
Number of Slice Registers: 15,254 out of 69,120 22%
Number used as Flip Flops: 15,244
Number used as Latches: 4
Number used as Latch-thrus: 6
Number of Slice LUTs: 11,699 out of 69,120 16%
Number used as logic: 11,230 out of 69,120 16%
Number using O6 output only: 9,310
Number using O5 output only: 295
Number using O5 and O6: 1,625
Number used as Memory: 439 out of 17,920 2%
Number used as Dual Port RAM: 308
Number using O6 output only: 204
Number using O5 output only: 20
Number using O5 and O6: 84
Number used as Shift Register: 131
Number using O6 output only: 131
Number used as exclusive route-thru: 30
Number of route-thrus: 357
Number using O6 output only: 325
Number using O5 output only: 32
Slice Logic Distribution:
Number of occupied Slices: 6,129 out of 17,280 35%
Number of LUT Flip Flop pairs used: 18,945
Number with an unused Flip Flop: 3,691 out of 18,945 19%
Number with an unused LUT: 7,246 out of 18,945 38%
Number of fully used LUT-FF pairs: 8,008 out of 18,945 42%
Number of unique control sets: 812
Number of slice register sites lost
to control set restrictions: 1,801 out of 69,120 2%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
OVERMAPPING of BRAM resources should be ignored if the design is
over-mapped for a non-BRAM resource or if placement fails.
IO Utilization:
Number of bonded IOBs: 463 out of 640 72%
Number of LOCed IOBs: 461 out of 463 99%
IOB Flip Flops: 693
IOB Master Pads: 1
IOB Slave Pads: 1
Number of bonded IPADs: 10 out of 50 20%
Number of bonded OPADs: 8 out of 32 25%
Specific Feature Utilization:
Number of BlockRAM/FIFO: 38 out of 148 25%
Number using BlockRAM only: 22
Number using FIFO only: 16
Total primitives used:
Number of 36k BlockRAM used: 21
Number of 18k BlockRAM used: 1
Number of 36k FIFO used: 14
Number of 18k FIFO used: 2
Total Memory used (KB): 1,314 out of 5,328 24%
Number of BUFG/BUFGCTRLs: 23 out of 32 71%
Number used as BUFGs: 23
Number of IDELAYCTRLs: 6 out of 22 27%
Number of BUFDSs: 1 out of 8 12%
Number of BUFIOs: 16 out of 80 20%
Number of DCM_ADVs: 8 out of 12 66%
Number of LOCed DCM_ADVs: 8 out of 8 100%
Number of GTP_DUALs: 2 out of 8 25%
Number of LOCed GTP_DUALs: 2 out of 2 100%
Number of PCIEs: 1 out of 1 100%
Number of PLL_ADVs: 1 out of 6 16%
Number of SYSMONs: 1 out of 1 100%
Number of RPM macros: 128
Average Fanout of Non-Clock Nets: 3.00
4.2.2.3 Resources used – XCV5FX70T.
Below is a summary (ISE11.4) of the resources used in the FPGA by the default
firmware (Standard SMT702 – XCV5VFX70T FPGA – PXIe option):
Slice Logic Utilization:
Number of Slice Registers: 15,344 out of 44,800 34%
Number used as Flip Flops: 15,337
Number used as Latches: 1
Number used as Latch-thrus: 6
Number of Slice LUTs: 11,832 out of 44,800 26%
Number used as logic: 11,372 out of 44,800 25%
Number using O6 output only: 9,458
Number using O5 output only: 289
Number using O5 and O6: 1,625
Number used as Memory: 429 out of 13,120 3%
Number used as Dual Port RAM: 308
Number using O6 output only: 204
Number using O5 output only: 20
Number using O5 and O6: 84
Number used as Shift Register: 121
Number using O6 output only: 121
Number used as exclusive route-thru: 31
Number of route-thrus: 393
Number using O6 output only: 318
Number using O5 output only: 75
Slice Logic Distribution:
Number of occupied Slices: 6,261 out of 11,200 55%
Number of LUT Flip Flop pairs used: 19,052
Number with an unused Flip Flop: 3,708 out of 19,052 19%
Number with an unused LUT: 7,220 out of 19,052 37%
Number of fully used LUT-FF pairs: 8,124 out of 19,052 42%
Number of unique control sets: 821
Number of slice register sites lost
to control set restrictions: 1,821 out of 44,800 4%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
OVERMAPPING of BRAM resources should be ignored if the design is
over-mapped for a non-BRAM resource or if placement fails.
IO Utilization:
Number of bonded IOBs: 463 out of 640 72%
Number of LOCed IOBs: 463 out of 463 100%
IOB Flip Flops: 693
IOB Master Pads: 1
IOB Slave Pads: 1
Number of bonded IPADs: 10 out of 50 20%
Number of bonded OPADs: 8 out of 32 25%
Specific Feature Utilization:
Number of BlockRAM/FIFO: 38 out of 148 25%
Number using BlockRAM only: 22
Number using FIFO only: 16
Total primitives used:
Number of 36k BlockRAM used: 21
Number of 18k BlockRAM used: 1
Number of 36k FIFO used: 14
Number of 18k FIFO used: 2
Total Memory used (KB): 1,314 out of 5,328 24%
Number of BUFG/BUFGCTRLs: 25 out of 32 78%
Number used as BUFGs: 25
Number of IDELAYCTRLs: 6 out of 22 27%
Number of BUFDSs: 1 out of 8 12%
Number of BUFIOs: 16 out of 80 20%
Number of DCM_ADVs: 8 out of 12 66%
Number of LOCed DCM_ADVs: 8 out of 8 100%
Number of GTX_DUALs: 2 out of 8 25%
Number of LOCed GTX_DUALs: 2 out of 2 100%
Number of PCIEs: 1 out of 3 33%
Number of LOCed PCIEs: 1 out of 1 100%
Number of PLL_ADVs: 1 out of 6 16%
Number of SYSMONs: 1 out of 1 100%
Number of RPM macros: 128
Average Fanout of Non-Clock Nets: 3.00
4.2.2.4 Resources used – XCV5FX100T.
Below is a summary (ISE14.3) of the resources used in the FPGA by the default
firmware (Standard SMT702 – XCV5VFX100T FPGA – PXIe option):
Slice Logic Utilization:
Number of Slice Registers: 16,720 out of 64,000 26%
Number used as Flip Flops: 16,712
Number used as Latches: 2
Number used as Latch-thrus: 6
Number of Slice LUTs: 12,911 out of 64,000 20%
Number used as logic: 12,053 out of 64,000 18%
Number using O6 output only: 10,065
Number using O5 output only: 348
Number using O5 and O6: 1,640
Number used as Memory: 816 out of 19,840 4%
Number used as Dual Port RAM: 308
Number using O6 output only: 204
Number using O5 output only: 20
Number using O5 and O6: 84
Number used as Shift Register: 508
Number using O6 output only: 507
Number using O5 and O6: 1
Number used as exclusive route-thru: 42
Number of route-thrus: 441
Number using O6 output only: 389
Number using O5 output only: 51
Number using O5 and O6: 1
Slice Logic Distribution:
Number of occupied Slices: 7,335 out of 16,000 45%
Number of LUT Flip Flop pairs used: 21,153
Number with an unused Flip Flop: 4,433 out of 21,153 20%
Number with an unused LUT: 8,242 out of 21,153 38%
Number of fully used LUT-FF pairs: 8,478 out of 21,153 40%
Number of unique control sets: 987
Number of slice register sites lost
to control set restrictions: 2,113 out of 64,000 3%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
OVERMAPPING of BRAM resources should be ignored if the design is
over-mapped for a non-BRAM resource or if placement fails.
IO Utilization:
Number of bonded IOBs: 465 out of 640 72%
Number of LOCed IOBs: 465 out of 465 100%
IOB Flip Flops: 694
IOB Master Pads: 1
IOB Slave Pads: 1
Number of bonded IPADs: 10
Number of LOCed IPADs: 2 out of 10 20%
Number of bonded OPADs: 8
Specific Feature Utilization:
Number of BlockRAM/FIFO: 42 out of 228 18%
Number using BlockRAM only: 26
Number using FIFO only: 16
Total primitives used:
Number of 36k BlockRAM used: 22
Number of 18k BlockRAM used: 4
Number of 36k FIFO used: 14
Number of 18k FIFO used: 2
Total Memory used (KB): 1,404 out of 8,208 17%
Number of BUFG/BUFGCTRLs: 26 out of 32 81%
Number used as BUFGs: 26
Number of IDELAYCTRLs: 6 out of 22 27%
Number of BSCANs: 1 out of 4 25%
Number of BUFDSs: 1 out of 8 12%
Number of BUFIOs: 16 out of 80 20%
Number of DCM_ADVs: 8 out of 12 66%
Number of LOCed DCM_ADVs: 8 out of 8 100%
Number of GTX_DUALs: 2 out of 8 25%
Number of LOCed GTX_DUALs: 2 out of 2 100%
Number of PCIEs: 1 out of 3 33%
Number of LOCed PCIEs: 1 out of 1 100%
Number of PLL_ADVs: 1 out of 6 16%
Number of SYSMONs: 1 out of 1 100%
Number of RPM macros: 137
Average Fanout of Non-Clock Nets: 3.12
The parts mentioned above (XC5VLX110T, XC5FX70T, XC5FX100T) are also
footprint compatible with the SXT series: XC5VSX50T and XC5VSX95T. The SXT
series implements a DSP48E core, which if used on the SMT702 may result an
increase of the power consumption. Please contact Sundance if you require details
about the SXT series.
4.2.3 Configuration (CPLD+Flash)
On the SMT702, the FPGA is connected to a CPLD via a serial link. The CPLD is
responsible for controlling read and write operations to and from the Flash memory
and to route data to the FPGA configuration port.
The following diagram show how connections are made on the board between the
CPLD, the Flash memory and the FPGA:
Ctrl[4:0]
Switch[1:0]
Data[7:0]
Address[25:0]
jtag
Configuration port
Figure 5 - Configuration (Flash).
A reset coming from the bus (PXI or PXI Express) triggers a configuration cycle and
the FPGA is configured with the default firmware (stored in factory at location 0).
The on-board Flash memory (256-Mbit part) is big enough to store several versions
of firmware. A switch (SW1) at the back of the board allows the selection among 4
locations (Switches select the bitstream to be booted at power up). Each can contain
up to 8Mbytes of data, which is big enough to store an XC5LX110T bitstream (about
3.8 Mbytes) and some text (comments or description of the firmware version).
The user can store a ‘user’ bitstream at location 1 (see table below) for instance
using the SMT6002 piece of software, also called Flash Utility. The SMT6002 also
allows to add comments (text) above the bitstream in flash memory.
Note that switches don’t have any influence when programming the flash.
This architecture allows the SMT702 to be used as a development platform for
signal processing and algorithms implementation. The function Reboot can be used
from the SMT6002 GUI to boot from any flash location within seconds.
Both FPGA and CPLD can be reprogrammed/reconfigured at anytime via JTAG (J8
connector – Using a Xilinx parallel/USB programming cable) but it can cause
problems as it will break the access to the board from the host.
At power up or under a reset on the PXI or PXI Express bus, it takes 140ms for the
FPGA (XC5VLX110T-3) to be fully configured and ready to answer the requests from
the host.
The following table shows the settings that can be used and the start addresses of
the bitstream in the Flash memory.
Position
Switch 2
Position
Switch 1
Bitstream start
address in
Description
flash
ON ON 0x1800000
User Bitstream 2
(Location 3)
ON OFF 0x1000000
User Bitstream 1
(Location 2)
OFF ON 0x0800000
(Location 1)
OFF OFF 0x0000000
(Location 0)
User bitstream 0
Default
bitstream
Default
selection
Note that the CPLD routes the contents of the flash starting from the location
selected (SW1) until the FPGA indicates that it is configured. Addresses are
incremented by a counter that rolls over to 0 when the maximum address is
reached. For instance, in the case where Location 1 is selected and a corrupted
bitstream is loaded at that location (or if there is no bitstream at that location), the
default bitstream will end up being loaded.
The default bitstream returns ‘DEF’ as firmware version (see register ‘Firmware
Version and Revision numbers).
It is recommended to keep the Switch SW1 so the User bitstream 0 is selected and
store a custom/user bitstream at Location 1 is needed. The card would then boot
from this location. Otherwise the card would boot automatically from the default
firmware (Location 0)
Storing a new bitstream using the SMT6002 first involves erasing the appropriate
sectors before programming them with the bitstream. This is automatically handled
by the SMT6002. Storing a new bitstream at location 1 (User Bitstream 0) will only
require from the user to select the file (.bit for instance) and press the ‘Comit’
button. The advanced tab offers more options such as a full erase or a partial erase
of the flash memory. None of them should be required in normal mode of operation.
Note that a full erase will erase the entire contents of the flash including the default
firmware and that it can take up to 3-4 minutes. The partial erase will erase the User
bitstreams only.
4.2.4 DDR2 Memory
Two banks of DDR2 memory are available on the SMT702, directly connected to the
FPGA. Interfaces are part of the default FPGA design. Each bank is 64-bit wide and
128-Meg deep, so each bank can store up to 1 Giga bytes (or 8-bit ADC samples).
Each memory bank is dedicated to one ADC. Both DDR2 interfaces are independent.
The type of memory fitted on the board can be clocked at a maximum or 333MHz.
In order to achieve storage real-time of the ADC samples, the DDR2 interface is
clocked at 250MHz (Default bitstream).
4.2.5 Clock circuitry
An on-board PLL+VCO chip ensures a stable fixed sampling frequency (maximum
rate, i.e. 1500MHz), in order for the board to be used as a digitiser without the need
of external clock signal. The PLL will be able to lock its internal VCO either on the
10MHz PXI reference or the 100MHz PXI express reference or on an external
reference signal. The sampling clock for the converters can be either coming from
the PLL+VCO chip or from an external source. The chip used is a National
Semiconductor part: LMX2531LQ1500.
The selection Internal/External clock is made via a bit in the control register. The
same applies to the selection of the reference clock.
Note that the PLL+VCO chip also has the possibility to output half of the fixed VCO
frequency, i.e. 1500/2=750MHz.
Below is a block diagram of the clock circuitry.
Ref Out
#5
PXIe Ref (10MHz)
(back-plane)
PXIe Ref (100MHz)
(back-plane)
Ext Ref
#4
Ext Clk
#3
#2
“
1
0
”
“01
”
”
0
0
“
Reference Clock Sele ction
c_RF_CLK_SEL[1:0]
c_REF_CLK_
OUT_DIV
Fixed on-board clock g enerator
c_REF_CLK_ON
5-80
BOARD_DIV
MHz
500-1500
MHz
Clock Distribution LMX2531
National Semiconductor
(1.5GHz or half of it)
LMX2531
750 or 1500
M
H
z
“
0
”
”
1
“
LMX2531
c_CLK_SOURCE_SEL
National Semiconductor
500
-15
0
0
M
H
z
ADCA (8-bit,
3GSPS)
ADC083000
ADCB (8-bit,
#1
SMA connector on
#x
the front panel
Note that all blocks are control by the Register Block. Command are
received from the PXIe bus and decoded.
3GSPS)
ADC083000
National Semiconductor
Figure 6 - Clock circuitry Block Diagram.
4.2.6 Data (samples) path / Data capture
This section details how samples from the ADCs are being captured and stored. By
default and after a power-up or reset operation, all interfaces are in reset state. The
only exception is the PXI/Express Interface. Relevant interface should first be taken
out of the initial reset state.
The next step is to program both ADCs and the clock generator and make sure it
locked to a reference signal. This is not needed in case of using an external
sampling clock. An ADC calibration cycle can be run. ADCs are then ready to output
samples and a clock to the FPGA.
Here are the details of the following step. One Xilinx DCM per ADC clock is used
inside the FPGA to ensure a good capture of data. The status of these DCMs should
be checked to make sure they are ‘locked’. They are available in the Global Control
Register. After being latched, samples go through a multiplexer to be pipelined and
then stored into the DDR2 memory available on the board. The DDR2 interface uses
some Xilinx specific blocks, such as idelays, DCMs and Phy, which have to be
‘locked’ and ‘ready’ as well. These have to be checked the same way, using the bits
available from the Global Control Register.
Each ADC is being dedicated a DDR2 Memory bank, which can be seen as a Fifo.
Both Fifos have status bits to check whether they are empty or full (bit available
from Global Control Register). Each Fifo is connected to a DMA channel. DMA
channel are implemented as Xlinks.
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