Sundance SMT6040 User Manual
Sundance Multiprocessor Technology Limited
SMT6040 “Sundance Simulink Toolbox”
Unit / Module Description: Sundance Simulink Toolbox for DSP-FPGA code
generation
Unit / Module Number: SMT6040
Document Issue Number: 3.1.0
Issue Date: 8th January 2009
Original Author: Simone Boragno
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Date : 6 July 2006
SMT6040
“Sundance Simulink
Toolbox”
Abstract
This document describes the SMT6040, a flexible tool for the co-design and co-generation of
DSP and FPGA code from Simulink diagrams. The SMT6040 specifically targets Sundance
boards and comes with a number of demos for different systems.
The SMT6040 also allows the integration of Simulink designs with C code, VHDL code and
System Generator diagrams, thus giving the maximum flexibility to the user.
Sundance Italia SRL
This document is the property of Sundance and may not be copied nor
communicated to a third party without prior written permission.
© Sundance Italia SRL 2009
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Revision History
Issue Changes Made Date Initial
1.0.0 Initial version 11/06/09 S.B.
1.0.1 Minor updates to demo descriptions 21/07/09 S.B.
1.0.2 Added pictures and further information on the demos 06/08/09 S.B.
2.0.0 Added information on the demos 21/08/09 S.B.
3.0.0 New Version 3.0 12/10/09 S.B.
3.0.1 Added description of SMT8036E and SMT8096 demo 18/11/09 S.B.
3.1.0 New SDR, RF, MIMO and WiMAX demos 08/01/10 S.B.
s
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Table of Contents
1 The SMT6040 Toolbox ................................................................................ 7
2 How to use the SMT6040............................................................................. 7
2.1 Integrate a SMT6040 Simulink DSP design into Diamond.......................................... 9
2.1.1 SMT6040 project.......................................................................................................9
2.1.2 Diamond project ......................................................................................................10
2.2 Integrate a Simulink FPGA design into Diamond....................................................... 12
2.2.1 Required signals.......................................................................................................12
2.2.2 Channels...................................................................................................................12
2.2.3 Driving pins.............................................................................................................. 14
2.2.4 Creating the task......................................................................................................14
2.2.5 System Generator configuration .............................................................................14
2.2.6 Synthesizing the Task with XST Creating the task .................................................15
3 Main demo applications .............................................................................16
3.1 SDR and SDR + RF front-end demos .......................................................................... 16
3.1.1 SMT8036E SDR demo ...........................................................................................20
3.2 Video demo .................................................................................................................. 20
3.3 DVIP demo....................................................................................................................23
3.4 WiMAX demo ...............................................................................................................26
3.5 MIMO_LTE demo ....................................................................................................... 30
3.6 RadioGiga demo ...........................................................................................................33
4 The SMT6040 package............................................................................... 36
4.1 Overview .......................................................................................................................36
4.2 SMT6040_DSP.............................................................................................................37
4.3 SMT6040_FPGA..........................................................................................................37
4.4 SDR ...............................................................................................................................37
4.5 Video .............................................................................................................................39
4.6 DVIP..............................................................................................................................39
4.7 MIMO_LTE .................................................................................................................40
4.8 WiMAX......................................................................................................................... 40
4.9 RadioGiga..................................................................................................................... 40
4.10 SMT6040_ generic...................................................................................................... 40
4.11 Miscellanea .................................................................................................................. 40
5 Version 2 ....................................................................................................41
5.1 Version 2 functionalities ..............................................................................................41
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5.2 Simulate and run an application..................................................................................47
5.3 SDR demo – No Sysgen – Version 2........................................................................... 48
5.4 SDR demo SMT8036E – No Sysgen – Version 2....................................................... 50
5.5 Video demo – Version 2 ...............................................................................................52
6 Useful resources........................................................................................ 53
6.1 Links..............................................................................................................................53
6.2 Contacts.........................................................................................................................53
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Table of Figures
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Figure 1: integration of Simulink diagrams in Diamond.............................................................8
Figure 2: sample DSP diagram...................................................................................................10
Figure 3: Diamond project and connections...............................................................................11
Figure 4: data transfer .................................................................................................................11
Figure 5: channel configuration in System Generator...............................................................13
Figure 6: System Generator configuration.................................................................................15
Figure 7: netlist properties..........................................................................................................15
Figure 8 : SMT8246 SDR demo (FPGA tasks in red, DSP tasks in yellow).............................. 17
Figure 9: SMT6040 diagram for SDR demo..............................................................................18
Figure 10: Logical connections between DSP tasks (SDR demo)..............................................18
Figure 11: output of the SDR demo 3..........................................................................................19
Figure 12: SMT8036E SDR demo (FPGA tasks in red, DSP tasks in blue) .............................20
Figure 13: Video demo (FPGA tasks in red, DSP tasks in yellow).............................................21
Figure 14: logical connections between DSP tasks (Video demo).............................................22
Figure 15: Simulink diagram (Video demo)...............................................................................22
Figure 16: basic Video processing example................................................................................23
Figure 17: DVIP demo (FPGA tasks in red, DSP tasks in yellow)..............................................24
Figure 18: logical connections between DSP tasks (DVIP demo) .............................................25
Figure 19: Simulink diagram (DVIP demo) ...............................................................................25
Figure 20: basic Video processing example on DVIP................................................................26
Figure 21 : WiMAX demo (FPGA tasks in red, DSP tasks in yellow)........................................27
Figure 22: SMT6040 diagram for WiMAX demo..................................................................... 28
Figure 23: logical connections between DSP tasks (WiMAX demo).........................................29
Figure 24: output of the WiMAX demo......................................................................................29
Figure 25 : MIMO_LTE demo (FPGA tasks in red, DSP tasks in yellow) ............................... 30
Figure 26: SMT6040 diagram for MIMO_LTE demo............................................................... 31
Figure 27: logical connections between DSP tasks (MIMO_LTE demo)..................................32
Figure 28: output of the MIMO_LTE demo ..............................................................................32
Figure 29 : RadioGiga demo (FPGA tasks in red, DSP tasks in yellow)....................................33
Figure 30: SMT6040 diagram for RadioGiga demo..................................................................34
Figure 31: logical connections between DSP tasks (RadioGiga demo) .....................................35
Figure 32: output of the RadioGiga demo..................................................................................35
Figure 33: the SMT6040 Package ..............................................................................................37
Figure 34: a SMT6040 DSP-FPGA-ADC/DAC design...............................................................41
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Figure 35: root DSP sub-system.................................................................................................42
Figure 36: DSP hardware interface ............................................................................................43
Figure 37: Diamond channel hardware interface ......................................................................44
Figure 38: node1 DSP sub-system..............................................................................................44
Figure 39: SMT350 FPGA-ADC/DAC sub-system ...................................................................45
Figure 40: LEDs output ..............................................................................................................45
Figure 41: DAC configuration.....................................................................................................46
Figure 42: simulation results..................................................................................................... 48
Figure 43: SDR demo SMT6040 diagram..................................................................................49
Figure 44: SMT8036E demo ...................................................................................................... 51
Figure 45: Video demo 2 - DSP diagram....................................................................................52
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1 The SMT6040 Toolbox
The SMT6040 is a MATLAB toolbox that allows generating DSP and FPGA code for
Sundance boards from a Simulink diagram.
The users can describe their projects by means of a set of inter connected blocks, which are
functionally identical to those from the Simulink library (math and logical operators, nonlinear and trigonometric functions, vector and matrix operations, modulators, etc.).
The Sundance-provided blocks have a Data Flow calculation paradigm, just like Simulink
blocks. The SMT6040 blocks accurately simulate their digita l and analog count erparts; at the
same time, the entire system is kept hardware-independent. To gether with Sundance Legolike modular approach, the SMT6040 lets users port the sa me high-level Simulink project to
many different Sundance systems quickly and easily.
An advanced user can utilise the SMT6040 toolbox with all Sundance boards; however, a
number of demos targeting the most common Sundance systems are provided to make the
understanding and the use of the SMT6040 easier.
These ready and working diagrams give customers a great starting point for their projects.
The following chapter describes the SMT6040 functionalities. Chapter 3 provides an
overview of the main demos (SDR, Video, DVIP, MIMO_LTE, WiMAX, RadioGiga). Chapter
4 describes the structure of the package and how to navigate its folders. Chapter 5 is
dedicated only to the users of Version 2.1, which has now been replaced by the current
Version 3.0.
All demos and SMT6040 functionalities are accurately documented in the SMT6040 package. This
manual aims to give an overview of the SMT6040, useful Getting Started instructions for the main
demo applications, and a description of the main procedure to generate complex SMT6040 Simulink
designs.
2 How to use the SMT6040
This chapter describes how to benefit of the SMT6040 to design DSP-FPGA applications
from Simulink diagrams targeting Sundance hardware.
For this purpose, the SMT6040 requires the following SW tools:
• Matlab
• Real Time Workshop (version found in Matlab
• TI Code Composer Studio 3.3
• Xilinx
• Xilinx
7.5.0 and Simulink 7.0
ISE Foundation 10.1
System Generator 10.1
7.5.0)
• Diamond 3.1.10 or Diamond 3.2 (DSP & FPGA licenses)
The SMT6040 allows using 3L Diamond (the main development environment for Sundance
hardware) as the integrator of Simulink diagrams targeting DSP-FPGA multi-processor
systems.
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In fact, the SMT6040 takes advantage of Sundance modularity and scalability to generate
multi-DSP/multi-FPGA applications from Simulink diagrams. The same application can
target different systems by few changes in the configuration.
Moreover, the SMT6040 uses Diamond channels to implement the communication be tween
processors. So, the user just needs to set up these virtual channels.
Each channel will be then mapped onto a comport or a SHB connection, thus fully exploiting
Sundance communication resources. The SMT6040 will automatically configure the
hardware and then manage the inter-processor co mmunication. So the user does not need to
worry about interrupts, data flow, etc. This makes development much easier and faster.
To explain how SMT6040 and Diamond are combined to build a unique and powerful
development environment, we remind that Diamond users can divide the application into
different logical tasks and assign each task to the processor (DSP or FPGA) on which they
would like the task to be executed.
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Figure 1: integration of Simulink diagrams in Diamond
A DSP task can be implemented in C, but also generated from a Simulink Diagram t hanks to
the SMT6040.
Similarly, a FPGA task can be implemented in VHDL, but also generated from a Simulink
Diagram thanks to System Generator.
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This procedure is shown in Figure 1.
Section 2.1 describes how to integrate a Simulink DSP task into Diamond. Section 2.2
describes how to integrate a Simulink FPGA task.
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2.1 Integrate a SMT6040 Simulink DSP design into Diamond
The SMT6040 allows generating full applications targeting Sundance HW, but it also
supports Diamond DSP and it can be used to generate a DSP task. This is very useful as it
adds flexibility and it makes it possible to integrate a Simulink design into a Diamond project
and also into the Diamond demos provided by Sundance.
Therefore, users can combine their Simulink algorithms with C/VHDL projects developed in
Diamond (e.g. they can add their tasks – designed with the SMT6040 – to Diamond SDR or
Video demos, which are provided by 3L).
The design process for a combined SMT6040-Diamond application requires only the
following simple steps:
1- Create a SMT6040 design that targets a DSP;
2- Compile the SMT6040 project; this will create the “T6040_root.tsk” DSP task;
3- Select the Diamond project of your interest and add the “T6040_root.tsk” task to it;
4- Connect the input/output ports of the “T6040_root.tsk” task and the ports of the
Diamond task of your interest;
5- Set up the data transfer between the two tasks;
6- Build and run the demo in Diamond IDE.
An example that explains this procedure is provided in the “SMT6040_generic” directory.
This folder contains the Diamond project (based on the “fpga-example1” demo) and the
Simulink project (represented in Figure 2).
Please notice that this package targets the SMT362 DSP. If you need to target another board,
you can select the correct module type by double-clicking on the “Digital HW Interface” block
under the “DSP6040/root” sub-system.
Please check that you are targeting the proper DSP module also in Diamond.
2.1.1 SMT6040 project
The Simulink diagram is in this case performs three operations:
- A sum of the two inputs is outputted on Diamond write Channel 0;
- The second input is passed through to Diamond write Channel 1;
- The sentence “SMT6040 task” is printed on the screen.
To compile the “DSP6040.mdl” design, the following two steps are necessary:
1- Double click on “Digital HW Interface”, then click on “Compile To HW/SW Analog”
and “Overall Build”;
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2- Run the MATLAB command: Diamond(‘DSP6040’)
This command creates the file “T6040_root.tsk ” and runs a Diamon d application (that is not
important in this case as the task will be used within a different Diamond project).
2.1.2 Diamond project
The original “fpga-example1” Diamond project had only one DSP task (named “driver”). In
this case, another DSP task is added (named “T6040_root”).
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Figure 2: sample DSP diagram
This additional task must have two input and two output ports to match the Simulink
diagram in Figure 2. Moreover, the “Create Main Source File” checkbox must not be ticked
when creating the task.
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Figure 3: Diamond project and connections
Figure 4: data transfer
By right-clicking on “T6040_root”, clicking on “Add Existing Files”, and browsing to
“T6040_root.tsk”, it is possible to add the .tsk file to the new task, which therefore will
behave as the SMT6040 diagram.
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To let the “T6040_root” task communicate with the “driver” task, the “driver” task needs to
have two additional output ports (named “to6040_0” and “to6040_1” respectively) and two
additional input ports (named “from6040_0” and “from6040_1” respectively). Connections
are created as in Figure 3.
Finally, the data transfer between the two DSP tasks can be set up thanks to the functions
“chan_out_message” and “chan_in_message” as in Figure 4. The printed output of the demo
demonstrates the behaviour of the task created by the SMT 6040 (the s um of the two inputs is
calculated while the second input is passed through to the second output channel).
This procedure can be applied to any Diamond demo. Of course, the S MT6040 DSP task can
be modified in Simulink as for the users’ processing algorithms.
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2.2 Integrate a Simulink FPGA design into Diamond
System Generator is a popular design tool from Xilinx that allows designing Simulink
diagrams targeting Xilinx FPGAs.
As previously pointed out, it is possible to create a Diamond FPGA task from a System
Generator project.
Therefore, similarly to the DSP case described in the previous chapter, it is possible to modify
a Diamond project or a Diamond demo (e.g. SDR or Video demos) by adding FPGA tasks
generated from a Simulink diagram.
This section describes how to use System Generator with Diamond to create and integr ate a
Diamond FPGA task.
These instructions are extracted from Diamond User Guide. Please check it for more
information: http://www.3l.com/user-guides/3l-diamond-for-sundance
2.2.1 Required signals
System Generator will automatically add the following ports for you if there is at least one
synchronous element in the task. If your processing is purely asynchronous you can add a
register on the validwords signal to force system generator to implement these ports.
• clk
• ce
• rst
Port ce_clr is not added by Sys tem Generator. You should add an input gateway to your
model called 'ce_clr' to ensure this signal is present on the interfa ce on the core created by
System Generator.
2.2.2 Channels
.
Unfortunately, System Generator supports only those types defined in the IEEE.STD
package; in particular, it does not support record types. This means that you cannot use the
convenient Diamond types described in Diamond User Guide; to create a channel you must
implement all of the signals explicitly. The simplest approach is to name the signals in th e
same way as you would using record types, but replacing '.' with '_'. For example, th e data
bus would be ' x_chan_in_0_Data'. The ports are implemented using Gateway In and
Gateway Out elements.
Each input channel is specified as follows:
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Gateway In Bus Size
x_chan_in_index_data 64 bits
x_chan_in_index_ready 1 bit
x_chan_in_index_write 1 bit
x_chan_in_index_validwords 2 bits
Gateway Out Bus Size
y_chan_in_index_ready 1 bit
Each output channel is specified as follows:
Gateway In Bus Size
y_chan_out_index_ready 1 bit
Gateway Out Bus Size
x_chan_out_index_data 64 bits
x_chan_out_index_ready 1 bit
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x_chan_out_index_write 1 bit
x_chan_out_index_validwords 2 bits
Figure 5: channel configuration in System Generator
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index represents the channel number, the only variable part of the name. Both input and
output are numbered from zero and the channel numbers must be continuous.
You must still provide a package file that declares the task’s component; this declaration
must use a record type — it is not looked at by System Generator.
You shouldn’t specify any IOB Location Constraints when using System
Generator.
2.2.3 Driving pins
A System Generator task can connect to the pins of the FPGA. Gateways In and Out are used
to implement the I/O buffers. The pin location, the electric standard and any other constrain t
must be specified in a UCF file accompanying the task.
2.2.4 Creating the task
When you hit the "Generate" button System Ge nerator compiles the Simulink model into a
number of HDL files and netlists.
These files should be added to the FCD file of your task alon g with the Diamond package file
that you must create yourself.
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The following snippet shows an example of a System Generator task called 'addone_cw'. We
have pre-synthesized the HDL files produced by System Generator to obtain the netlist
'addone_cw.ngc'. Note that we used the syntax '*.edn' to gather all the netlists produced by
System Generator.
PACKAGE "addone_cw_pkg.vhd"
FILE "netlist\addone_cw.ngc"
FILE "netlist\*.edn"
2.2.5 System Generator configuration
System Generator is configured as in Figure 6 (this is an example, please change the
configuration according to your HW).
• Compilation must be set to 'HDL netlist'.
• Part must be set to the FPGA type you are targeting.
• Synthesis Tool must be set to XST.
• Hardware Description Language must be set to VHDL.
• FPGA Clock Period (ns) must be the frequency at which the task will be clocked. This
setting is overwritten by Diamond with the frequency of the clock domain to which
the task belongs.
• Clock Pin Location must be left unspecified. Di amond connects the clock to the task
according to the clock domain specified in the configuration file.
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Figure 6: System Generator configuration
2.2.6 Synthesizing the Task with XST Creating the task
The VHDL files produced by System Generator may be synthesized with XST to produce a
netlist.
Figure 7: netlist properties
The netlist generated must not have any I/O buffers, since the task will be used in a higher
level design. In most cases it shouldn’t implement any clock buffers since Diamond will
implement them for you. The configuration XST is shown in Figure 7. Add I/O buffers must
not be ticked; all the other options can be set to values you choose.
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3 Main demo applications
This chapter illustrates the main demos targeting some of Sundance most common systems.
Please notice that these demos can easily be changed to target other systems.
For a complete list of examples, please see Chapter 4.
More detailed instructions can be found in the SMT6040 package.
3.1 SDR and SDR + RF front-end demos
! Demo: “..\Release_3.0\Applications\_Sundance\SDR\SDR_8146_8246_8096”
! Demo: “..\Release_3.0\Applications\_Sundance\SDR\SMT8036E_SDRDemo”
(The demos targeting SMT8096, SMT8146 and SMT8246 are identical with the exception of
the DSP type. The SMT8246 demo is described below, but these explanations apply also to
the SMT8146, SMT8096 demos. A similar structure is the base of the SMR8036E. For this
system the few differences with respect to the SMT8246 demo are explained in Paragraph
3.1.1).
Same requirements apply as the ones described in Chapter 2.
This is the recommended demo for Special University Offer SDR users.
This demo targets the SMT8246 system but it can be easily changed to target other SDR
systems.
These demos have the structure described in Chapter 2. Ther efore, th ey are mad e of Simulink
projects implementing DSP/FPGA tasks and a Diamond IDE project that acts as integrator.
In particular, in this same Diamond workspace different projects are available, in order to
target different SDR systems: SMT8146 and SMT8246 (with SMT350 or SMT950, and with
optional SMT349), SMT8096.
Each project can be considered separately and the same Simulink diagram is valid for all the
demos (only the DSP processor type should be changed to match the one of the system in use
– i.e. SMT362, SM374 or SMT395).
The diagram in Figure 8 represents a more detailed structure of the demo.
The SDR_2 demo is composed by a number of DSP and FPGA tasks. The “main” function is
in the DSP task named “smt350”. This task receives the data from the FPGA and sends the
proper data to the display and FFT processing tasks.
As described in Chapter 2, a Diamond DSP task (e.g. named “T6040_root.tsk”) can be
created by the SMT6040.
This task can be added to the SDR Diamond project as explained in Chapter 3. This new ta sk
can communicate, for example, with the “smt350” DSP task. For this purpose, two input and
one output ports have to be added to the “smt350” task.
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