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SMT6025
User Manual v.2.9
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Sundance SMT6025 User Manual v.2.9

SMT6025
User Manual
Version 2.9
User Manual (QCF42); Version 2.9, 22/02/02; © Sundance Multiprocessor Technology Ltd. 2002
1 Table of Contents
1 Table of Contents ........................................................................................................................... 2
List of abbreviations................................................................................................................................. 5
2 List of figures................................................................................................................................... 5
3 Introduction ..................................................................................................................................... 6
4 Conventions .................................................................................................................................... 7
5 Prerequisites ................................................................................................................................... 7
6 Software Installation and Setup...................................................................................................... 7
6.1 Configuring Visual Studio.......................................................................................................8
7 Design philosophy .......................................................................................................................... 9
8 Hardware overview ....................................................................................................................... 10
8.1 Comport................................................................................................................................ 10
8.2 The CPLD............................................................................................................................. 10
8.3 State of the IIOF lines .......................................................................................................... 11
8.4 The PCI bridge chip .............................................................................................................11
9 Software design ............................................................................................................................ 12
9.1 Interface mechanism............................................................................................................ 12
10 Functions exported by SmtDrv.dll................................................................................................. 12
10.1 SmtOpen .............................................................................................................................. 12
10.2 SmtGetBoardCount.............................................................................................................. 12
10.3 SmtOpenBoard ....................................................................................................................13
10.4 SmtCloseBoard .................................................................................................................... 13
10.5 SmtGetBoardIndex............................................................................................................... 13
10.6 SmtGetBoardInfo .................................................................................................................14
10.7 SmtGetError ......................................................................................................................... 15
10.8 SmtGetDLLVer..................................................................................................................... 15
10.9 SmtGetPluginVersion........................................................................................................... 15
11 Functional description................................................................................................................... 16
12 Host comport................................................................................................................................. 16
12.1 CpRead ................................................................................................................................ 16
12.2 CpWrite ................................................................................................................................ 17
12.3 CpCancel.............................................................................................................................. 17
13 Downloading files.......................................................................................................................... 17
13.1 BinaryLoad ........................................................................................................................... 17
13.2 CoffLoad............................................................................................................................... 18
14 Mailboxes...................................................................................................................................... 18
14.1 MbWrite................................................................................................................................ 19
14.2 MbRead................................................................................................................................ 20
14.3 MbCancel ............................................................................................................................. 20
15 High speed channel ...................................................................................................................... 21
15.1 Introduction .......................................................................................................................... 21
User Manual (QCF42); Version 2.9, 22/02/02; © Sundance Multiprocessor Technology Ltd. 2002
15.2 Command word....................................................................................................................22
15.3 Reply word ........................................................................................................................... 23
15.4 Associated data.................................................................................................................... 23
15.4.1 Carrier board SRAM.................................................................................................... 23
15.4.2 Host memory ............................................................................................................... 24
15.5 Channel handler................................................................................................................... 24
15.5.1 Handler not interfacing to host software...................................................................... 25
15.5.2 Handler interfacing to host software............................................................................ 25
15.5.3 Implementing a handler............................................................................................... 27
15.5.4 Opening a channel handler ......................................................................................... 28
15.5.5 Closing a handler......................................................................................................... 28
15.5.6 Development guidelines .............................................................................................. 28
15.6 The HSC object.................................................................................................................... 29
15.6.1 GetIFHw ...................................................................................................................... 29
15.6.2 GetChannel ................................................................................................................. 29
15.6.3 GetHandlerName......................................................................................................... 29
15.6.4 PciOpen....................................................................................................................... 30
15.6.5 PciClose ...................................................................................................................... 30
15.6.6 GetData ....................................................................................................................... 30
15.6.7 SetData........................................................................................................................ 31
15.6.8 ArgsPut........................................................................................................................ 31
15.6.9 ArgsGet ....................................................................................................................... 31
15.7 The default handler .............................................................................................................. 32
15.7.1 SRamPutSync ............................................................................................................. 32
15.7.2 SRamPutDone............................................................................................................. 32
15.7.3 SRamGetSync............................................................................................................. 33
15.7.4 SRamGetDone ............................................................................................................ 33
15.7.5 SramCancel................................................................................................................. 33
15.7.6 PciOpenSync............................................................................................................... 34
15.7.7 PciCloseSync .............................................................................................................. 34
15.7.8 PciPutSync .................................................................................................................. 34
15.7.9 PciPutDone.................................................................................................................. 34
15.7.10 PciGetSync.................................................................................................................. 35
15.7.11 PciGetDone ................................................................................................................. 35
15.7.12 PciCancel .................................................................................................................... 35
16 Board state.................................................................................................................................... 36
16.1 ResetTIMs............................................................................................................................ 36
16.2 ResetBoard .......................................................................................................................... 36
17 Read and write carrier board registers ......................................................................................... 36
17.1 Read32................................................................................................................................. 36
17.2 Read16................................................................................................................................. 36
17.3 Read8................................................................................................................................... 37
17.4 Write32................................................................................................................................. 37
17.5 Write16................................................................................................................................. 37
User Manual (QCF42); Version 2.9, 22/02/02; © Sundance Multiprocessor Technology Ltd. 2002
17.6 Write8................................................................................................................................... 37
18 PCI bridge chip register access .................................................................................................... 37
18.1 PciRead32............................................................................................................................ 38
18.2 PciWrite32............................................................................................................................ 38
18.3 PciWrite16............................................................................................................................ 38
18.4 PciWrite8.............................................................................................................................. 38
18.5 PciVirtualAddr ...................................................................................................................... 38
19 DSP interrupt ................................................................................................................................ 38
19.1 DspAttatchInt........................................................................................................................ 39
20 Memory allocation......................................................................................................................... 39
20.1 MemLock.............................................................................................................................. 39
20.2 MemUnlock .......................................................................................................................... 40
21 Performance figures ..................................................................................................................... 40
22 Handling errors ............................................................................................................................. 40
22.1 Exported functions ............................................................................................................... 40
22.2 Exception mechanism .......................................................................................................... 41
23 Extras............................................................................................................................................ 41
23.1 Confidence test dialog..........................................................................................................42
23.2 SMT310Q comport switching dialog .................................................................................... 43
23.3 PCI Information dialog..........................................................................................................44
User Manual (QCF42); Version 2.9, 22/02/02; © Sundance Multiprocessor Technology Ltd. 2002
List of abbreviations
BAR Base Address Region
COFF Common Object File Format
CPLD Complex PLDs
DMA Direct Memory Access
DSP Digital Signal Processor
HSC High Speed Channel
JTAG Joint Test Action Group
MDL Memory Descriptor List
PCI Peripheral Component Interconnect
PLD Programmable Logic Device
SMT Sundance Multiprocessor Technology Ltd.
TIM Texas Instruments Module
2 List of figures
Figure 1 - The SMT6025 interfaces to Sundance hardware ....................................... 6
Figure 2 - Directory structure after installing the SMT6025......................................... 8
Figure 3 - Adding the path to the include directories to the compiler options ............. 9
Figure 4 - Adding the path to the library directories to the compiler options ............. 9
Figure 5 - Overview of the hardware. ....................................................................... 10
Figure 6 - Mailboxes with the SMT6025 ................................................................... 19
Figure 7 - Standard HSC transaction........................................................................ 21
Figure 8 - Layout of the SRAM memory ................................................................... 24
Figure 9 - Operation of a handler.............................................................................. 25
Figure 10 - Confidence test dialog............................................................................ 42
Figure 11 - The SMT310Q comport switch dialog .................................................... 43
Figure 12 - The PCI information dialog..................................................................... 44
User Manual (QCF42); Version 2.9, 22/02/02; © Sundance Multiprocessor Technology Ltd. 2002
3 Introduction
The SMT6025 SDK provides you with an easy and efficient way to access Sundance carrier boards. It allows you to control these boards from the host as well as to exchange data between the carrier board and the host. The SMT6025 is ideal for customers that wish to develop their own code to interface with Sundance hardware.
Your application
SMT6025 SDK
Comport
Status
Sundance carrier board
PCI
State control
Figure 1 - The SMT6025 interfaces to Sundance hardware
Figure 1 - shows the SMT6025 forming the link between your application and the Sundance carrier boards in your system. Having a standard interface such as the SMT6025 ensures that you do not need to recompile and link your software when the hardware in the system changes. The SMT6025 hides the details of the device driver, allowing you to concentrate on the development process.
The SMT6025:
• Provides the host side support for 3L Diamond board services.
• Shorten development time by providing you with a ready-to-use interface to
the hardware.
• Transfer data between the carrier board and the host.
• Downloads applications to the carrier board.
• Obtains information about the carrier board.
• Controls the state of the carrier board.
User Manual (QCF42); Version 2.9, 22/02/02; © Sundance Multiprocessor Technology Ltd. 2002
• Gives you a basic building block for more complex systems.
• Provides you with direct access to the hardware registers of the carrier board.
• Provides you with a C++ type interface to the carrier board.
The SMT6025 currently supports the following carrier boards.
Carrier board Description Functionality
SMT300 1 TIM site Compact PCI carrier board Full support
SMT300Q 4 TIM site Compact PCI carrier board Full support
SMT310 1 TIM site PCI carrier board Full support
SMT310Q 4 TIM site PCI carrier board Full support
SMT320 (Obsolete) 4 TIM site PCI carrier board Partial support
SMT327 (Obsolete) 4 TIM site Compact PCI carrier board Partial support
4 Conventions
UINT A 32 bit unsigned value (unsigned int).
DWORD 32 bit unsigned value (unsigned long).
Root TIM The TIM on site 1 of your carrier board.
Root DSP The DSP on TIM site 1.
5 Prerequisites
C++ is used for the software interfaces. Even if you are not familiar with C++, you should be able to find your way by referring to the samples. The samples have been compiled and tested with Microsoft Visual Studio Version 6.0.
6 Software Installation and Setup
Insert the SMT6025 CD into your CD drive. The setup program should start automatically; if it doesn’t you can start it yourself by opening Explorer, browsing to the CD, and then double-clicking Setup.exe. The installation program will give you the option of installing samples. We recommend that you become familiar with the SMT6025 by installing and reviewing the sample code.
User Manual (QCF42); Version 2.9, 22/02/02; © Sundance Multiprocessor Technology Ltd. 2002
The default directory is “C:\Program Files\Sundance\SMT6025”. Installation should give you the directory structure shown below.
Figure 2 - Directory structure after installing the SMT6025
Applications need access to smtdrv.h and smtdrv.lib. You need to arrange that these files can be found during compilation and linking. We strongly recommend that you do not make copies of these files, but access them from the installation directory as follows:
6.1 Configuring Visual Studio
The installation process configures the examples to compile and link correctly without any user intervention. However, for your own applications, you need to configure visual studio to add the paths to the include and lib directories to your compiler options.
You do this as follows:
• Open Visual studio.
• Select "Tools->Options" from the menu.
• Select the “Directories” tab.
• Select “Include files” from the "Show directories for" drop down list.
• Add the path to the include directory for the SMT6025 installation to the
list of directories.
User Manual (QCF42); Version 2.9, 22/02/02; © Sundance Multiprocessor Technology Ltd. 2002
Figure 3 - Adding the path to the include directories to the compiler options
• Next select “Library files” from the "Show directories for" drop down list.
• Add the path to the library files for the SMT6025 to the to the list of
directories.
Figure 4 - Adding the path to the library directories to the compiler options
7 Design philosophy
The design of the SMT6025 allows developers to:
• Obtain a simple interface for controlling the host comport, Mailboxes, High Speed Channel, and DSP interrupts.
• Access the low-level functionality of the hardware.
User Manual (QCF42); Version 2.9, 22/02/02; © Sundance Multiprocessor Technology Ltd. 2002
8 Hardware overview
You need to be aware of the assumptions the SMT6025 makes about hardware resources. This section provides a basic overview of the main hardware features and shows how the SMT6025 interacts with them. The carrier board’s User Manual contains a more detailed description of the hardware.
CPLD (BAR 1)

Comport

IntD
PCI Bridge (BAR 0)
Comport
IntA
PCI
LINT (IIOF2)
Comport
IIOF1
IIOF2
IIOF0
Reset
The Bridge chip forms the link between the host and the DSP. The mailbox registers are contained in the bridge chip.
TIM site 1
(Boot loader
supports
loading binary
files from comport)
TIM site
2
TIM site
3
TIM site
4
Figure 5 - Overview of the hardware.
The figure above illustrates the main hardware concepts of a typical Sundance carrier board.
8.1 Comport
A comport is a general mechanism for transferring data between components of your system. Most TIM modules have several comports that can connect to other TIMs or the host. These connections are usually made with FMS cables, but some boards have built-in connections that can be controlled by carrier board registers; the User Manual for your board will describe these registers in detail. The standard board configuration will connect comport 3 on TIM site 1 to the host.
8.2 The CPLD
The CPLD is used to configure the carrier board. It allows you to select the direction of signals on the carrier board, select interrupt sources and set the routing of the IIOF lines. The CPLD registers are mapped in BAR1 of the PCI
User Manual (QCF42); Version 2.9, 22/02/02; © Sundance Multiprocessor Technology Ltd. 2002
bridge chip. The carrier board’s User Manual gives more information about the CPLD.
8.3 State of the IIOF lines
The LINT (local interrupt) line on the global bus side of the PCI bridge chip can be switched to any of the IIOF lines that go to the DSP.
The initial configurations of the IIOF lines are as follows:
Line Use or direction
IIOF0 Host to DSP
IIOF1 DSP to Host
IIOF2 Used internally by the SMT6025 to signal mailbox interrupts
to the DSP.
Table 1 - Initial state of the IIOF lines when the SMT6025 starts up.
8.4 The PCI bridge chip
The bridge chip forms the link between the host and the carrier board. It connects the local bus on the carrier board with the PCI bus of the host and provides apertures that allow the local bus access to the PCI bus. These apertures act like windows through which the local bus can access data on the PCI bus.
The internal PCI bridge registers are mapped in BAR0, allowing access by both the local bus (DSP side) and the PCI bus (host side). Contained in the bridge chip are the 16 x 8-bit mailbox registers (Section 14).
The bridge chip provides a local bus interrupt line (LINT) as well as a PCI bus interrupt line (IntA). These interrupt lines allow both the host and the DSP to interrupt each other.
More information about the bridge chip can be found at
http://www.quicklogic.com
.
User Manual (QCF42); Version 2.9, 22/02/02; © Sundance Multiprocessor Technology Ltd. 2002
9 Software design
9.1 Interface mechanism
The design makes use of a C++ style interface pointer to the hardware.
SmtDrv.dll exports functions that gather information about the installed boards and provide an interface pointer for later use.
To use the SMT6025, you need to:
• Obtain an interface pointer to the hardware by calling SmtOpenBoard().
• Use the interface pointer to call functions related to the hardware.
Example:
IFHw *pBoard = SmtOpenBoard(0); // open the first board found pBoard->ResetTIMs(); pBoard->BinaryLoad("MyFile.app");
10 Functions exported by SmtDrv.dll
This section describes each of the functions exported by SmtDrv.dll. These functions are described in the header file SmtDrv.h.
10.1 SmtOpen
Initialise the SMT6025 library. Applications must call this function before using any other features of the library.
Prototype
SMTRet SmtOpen( void );
Return value
The function returns SMT_OK on successful completion; other return values indicate failure. SmtGetError() can be used to translate error values into descriptive strings.
10.2 SmtGetBoardCount
Return the number of Sundance carrier boards found in the system.
Prototype
Return value
DWORD SmtGetBoardCount(void);
The number of Sundance carrier boards found in the system.
User Manual (QCF42); Version 2.9, 22/02/02; © Sundance Multiprocessor Technology Ltd. 2002
10.3 SmtOpenBoard
Obtain an interface to a Sundance carrier board.
Prototype
IFHw * SmtOpenBoard( UINT nIndex );
Parameters
nIndex The zero based index of the carrier board. nIndex should
be in the range 0 <= nIndex < GetBoardCount().
Return value
The return value is an interface of type IFHw that can be used to access the carrier board. Refer to section 11 for a description of the functions provided by this interface. NULL (0) is returned on error.
10.4 SmtCloseBoard
Close an interface to a board. You should not use the interface pointer any more after calling SmtCloseBoard().
Prototype
void SmtCloseBoard( UINT nBoard );
Parameters
nBoard The index of the board that should be closed. nIndex
should be in the range 0 <= nIndex < GetBoardCount().
10.5 SmtGetBoardIndex
Find the zero based index for the board at the specified base address.
Prototype
INT SmtGetBoardIndex( UINT nBaseAddress );
Parameters
nBaseAddress The board base address. The base address is the PCI
address that the host operating system has assigned to the carrier board.
Return value
The zero based index of the board at base address nBaseAddress.
The function returns –1 when no board is found.
User Manual (QCF42); Version 2.9, 22/02/02; © Sundance Multiprocessor Technology Ltd. 2002
10.6 SmtGetBoardInfo
Return information about a carrier board. For a description of the information returned see the remarks.
Prototype
SMTRet SmtGetBoardInfo( UINT nIndex, SMTBI& info );
Parameters
nIndex The zero based index of the board.
info The structure that is to be filled in with the board
information.
Return value
The function returns SMT_OK on successful completion; other return values indicate failure. SmtGetError() can be used to translate error values into descriptive strings.
Remarks
The information is returned in the SMTBI structure described below:
struct SMTBI { SMTBoardType Type; char cszType[32]; UINT nBase; UINT nRange; SMTHWStatus HwStatus; SMTLock LockStatus; SMTOpen OpenRes; };
The information returned is summarized in the table below:
Field Description
Type Specify the type of carrier board.
cszType String description of the type of carrier board. For example
“SMT310Q”
nBase The PCI base address that the host operating system has assigned
to this carrier board.
nRange The number of bytes from the base address that has been assigned
to this carrier board.
HwStatus The hardware status of the carrier board. Valid values are SMT_On
and SMT_Off.
LockStatus If the carrier board could be opened successfully, this value will be
SMT_LOCK_OK.
User Manual (QCF42); Version 2.9, 22/02/02; © Sundance Multiprocessor Technology Ltd. 2002
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