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SMT498
User Manual
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Sundance SMT498 User Manual

SMT498
User Manual
User Manual; Version 1.2, 11/01/05; © Sundance Digital Signal Processing Inc. 2004
Page 1
Revision History
Changes Made Issue Initials
6/1/05 Updates based on feedback 1.1 PTM
11/1/05 Update on System ACE and JTAG 1.2 SM
Page 2
List of Abbreviations
Abbreviation Explanation
ASIC Application Specific Integrated Circuit BOM Bill Of Materials CMC Common Mezzanine Card Comport Communications Port DSP Digital Signal Processor FPDP Front Panel Data Port FPGA Field Programmable Gate Array NA Not Applicable OTP One-Time Programmable PC Personal Computer PCB Printed Circuit Board PCI Peripheral Component Interconnect PMC PCI Mezzanine Card PrPMC Processor PMC SDB Sundance Digital Bus SDRAM Synchronous Dynamic Random Access Memory SHB Sundance High-speed Bus SMT Sundance Multiprocessor Technology TBD To Be Determined TI Texas Instruments
Page 3
Table of Contents
Introduction........................................................................................................................... 7
Overview............................................................................................................................. 7
Module Features................................................................................................................. 7
Related Documents ............................................................................................................ 7
Block Diagram.......................................................................................................................8
Mechanical Standard............................................................................................................ 8
SMT498 Support.................................................................................................................... 9
SMT498 Installation .............................................................................................................. 9
QL5064................................................................................................................................. 10
Local bus........................................................................................................................... 10
Virtex FPGA configuration ................................................................................................ 11
Virtex FPGA design .......................................................................................................... 11
Virtex II FPGA...................................................................................................................... 12
FPGA Block Diagram........................................................................................................12
Configuration..................................................................................................................... 12
Memory............................................................................................................................. 12
SHBs................................................................................................................................. 13
SHB Connectors ........................................................................................................... 13
SHB Cable Assembly.................................................................................................... 14
SHB Inter Modules solutions......................................................................................... 14
Half Word Interface (16-bit SHB Interface) ................................................................... 14
RSLs .................................................................................................................................15
RSL Connector.............................................................................................................. 15
RSL Cable Assembly.................................................................................................... 15
Miscellaneous I/O’s........................................................................................................... 16
System ACE SC................................................................................................................... 17
PROM ...............................................................................................................................17
Configuration Controller.................................................................................................... 17
Flash.................................................................................................................................17
Power Supplies ................................................................................................................... 18
DC/DC converter............................................................................................................... 18
Linear Voltage regulator.................................................................................................... 18
Daughter Module................................................................................................................. 19
PMC Standard ..................................................................................................................... 20
Voltage keying .................................................................................................................. 20
Connectors........................................................................................................................ 20
Page 4
Component heights........................................................................................................... 20
Board Weight .................................................................................................................... 20
Standoffs........................................................................................................................... 20
Bezel and I/O capability .................................................................................................... 20
Power consumption .......................................................................................................... 20
Grounding ......................................................................................................................... 21
Conduction Cooling........................................................................................................... 21
Power Supply.................................................................................................................... 21
Standalone operation........................................................................................................ 21
Only use this connector for standalone operation (i.e. when not plugged into a PCI slot)!21
Reset Structure................................................................................................................. 21
Header Pinout...................................................................................................................... 22
PCI.................................................................................................................................... 22
SHBs................................................................................................................................. 24
RSL Header ...................................................................................................................... 26
RSL Side 1 Pinout (LVDS only) .................................................................................... 26
RSL Side 2 Pinout (LVDS only) .................................................................................... 26
JTAG headers................................................................................................................... 27
Power connector............................................................................................................... 28
PCB Layout.......................................................................................................................... 28
Safety................................................................................................................................... 29
EMC...................................................................................................................................... 30
Appendix.............................................................................................................................. 30
Configuring the FPGA....................................................................................................... 31
PCI Mode...................................................................................................................... 31
JTAG/Boundary Scan ................................................................................................... 32
System ACE SC............................................................................................................ 33
Status Bit Encoding:.................................................................................................. 34
Creating System ACE programming file (.MPM)............................................................... 35
Page 5
Table of Figures
Figure 1 - Block diagram of the SMT498................................................................................8
Figure 2 – Single-Size PMC card (from IEEE 1386-2001)...................................................... 8
Figure 3 – QL5064 Connection............................................................................................. 10
Figure 4 - Default FPGA Configuration................................................................................. 12
Figure 5 – SHB Connector.................................................................................................... 13
Figure 6 – RSL Top Connector............................................................................................. 15
Figure 7 - RSL Bottom Connector........................................................................................ 15
Figure 8 – Location of JTAG IN, OUT and DIP Switches ..................................................... 27
Figure 9 - Module Side 1 View............................................................................................. 29
Figure 10 – Module Side 2 View........................................................................................... 29
Figure 11 – Module Side View.............................................................................................. 29
Figure 12 - Location of the DIP Switches and the PROM..................................................... 31
Table of Tables
Table 1 - SHB configuration Matrix....................................................................................... 14
Table 2 – RSL Speed VS FPGA Speed Grade..................................................................... 16
Table 3 – Board Clocks......................................................................................................... 16
Table 4 – PMC P11/P12 Interface........................................................................................23
Table 5 – PMC P13/P14 Interface........................................................................................24
Table 6 – SHB Interface........................................................................................................ 25
Table 7 – RSL Side 1 Pinout................................................................................................. 26
Table 8 – RSL Side 2 Pinout................................................................................................. 26
Table 9 – JTAG Header Pinout............................................................................................. 27
Table 10 – Status Bits Encoding........................................................................................... 34
Page 6

Introduction

Overview

The SMT498 is Sundance’s latest FPGA PrPMC module. This module uses a Xilinx Virtex II
Pro XC2VP100, which is configured to provide two comport links, five SHB’s, two RSL’s and
other functions.

Module Features

The main features of the SMT498 are listed below:
Xilinx 128MB of DDR2 SDRAM Five
In System Configuration using System ACE Soft Controller Tall single-size PrPMC module
66MHz 64-bit PCI interface with over 500MB/s data rate
Virtex II Pro XC2VP100 (FF1704 package)
SHB, two RSL, and two 8-bit Comport interfaces for easy interconnection to
Sundance products
Related Documents [1] PCI Mezzanine Card (PMC) Spec – IEEE.
http://shop.ieee.org/store/product.asp?prodno=SS94922
[2] Sundance High-speed Bus (SHB) specifications – Sundance.
http://sundance.com/docs/SHB%20Technical%20Specification.pdf
[3] Rocket Serial Link (RSL) specifications – Sundance.
http://sundance.com/docs/RSL%20­%20Technical%20Specification%20Rev01%20Iss03.pdf
[4] Processor PMC (PrPMC) Spec – VITA.
http://www.vita.com/
[5] System ACE SC Solution Datasheet – Xilinx.
http://direct.xilinx.com/bvdocs/publications/ds088.pdf
Page 7

Block Diagram

The following diagram shows the block diagram of the SMT498.
Figure 1 - Block diagram of the SMT498.

Mechanical Standard

PMC is a variant of CMC that uses PCI to communicate over the backplane. The IEEE CMC standard describes both single- and double-size mezzanine cards. SMT498 will be a single-size card.
Figure 2 – Single-Size PMC card (from IEEE 1386-2001)
Page 8
Dimensions of the single-size CMC are 74.0mm wide by 149.0mm deep.

SMT498 Support

The SMT498 is supported by the SMT6041-498 software package available from SUNDANCE. Please register on the SUNDANCE Support Forum if not yet registered. Then enter your company’s forum and you can request the SMT6041-498 from there.

SMT498 Installation

Do NOT connect any external TTL (5v) signals to the SMT498 I/Os, which connect directly to the FPGA, as the FPGA is NOT 5v tolerant. However the lines on connector P14 of the carrier board are made 5V tolerant for some applications.
You can fit the SMT498 on its own on any PMC compatible carrier board. When mated with a carrier board such as Twin Industries Xtend1000, it may then be plugged into a host computer (e.g. Windows PC).
Please, follow these steps to install the SMT498 module on a Host system:
1. Remove the carrier board from the host system.
2. Place the SMT498 module on a PMC site. (See your carrier board User Manual.)Make sure that the board is firmly seated before screwing the SMT498 to the two main mounting holes. Use 10mm M3 Standoffs (Digikey 4391K-ND) and M3 5mm bolts (Digikey H742-ND) to secure the module to any carrier card.
3. Connect the SHB and/or RSL cables to the SMT498 (if required by your application).
4. Install the carrier board in the host system and start the PC.
5. The SMT498 can also be used as a standalone FPGA board. Connect a molex power connector similar to the one used for the hard disk to provide 5V.
(Note only 5V should be provided, do not provide 12 V)
Page 9

QL5064

The PCI bridge chip from QuickLogic is installed on a SMT498. This device combines a 66MHz/64-bit PCI Master/Target ASIC core with a one-time
programmable (OTP) FPGA fabric. The configuration of the FPGA fabric in the QL5064 is performed prior to
manufacturing of the module and cannot be changed by the user.

Local bus

QL5064 provides a bridge between the PCI bus of the host system and the Local bus of the SMT498. This interface will allow software on the host PC to transfer data to and from the other interfaces in this design. The interface between the FPGA and PCI bridge is clocked at a speed of 64MHz with a data bus width of 64 bits.
There are two primary functions of the Local bus on SMT498:
1) Configuration of the Virtex FPGA
2) Communication with logic designs loaded in the Virtex FPGA
CS[3..0]
CS[0]
64-Bit/ 66 MHz
PCI BUS
QL5064
64-Bit/ 64 MHz
8/64-Bit
Local Bus
Virtex FPGA
Config / User
Defined
CS[3..1]
64-Bit
User Defined
Figure 3 – QL5064 Connection
More information about the Local bus interface and protocols can be obtained from QuickLogic at:
http://www.quicklogic.com/images/QL5064_CD_UM.pdf
Page 10

Virtex FPGA configuration

Programming of the Virtex FPGA can be achieved over the PCI bus using the SelectMAP interface. This interface is 8-bits wide and runs at the full speed of the Local bus. By simply writing a stream of configuration bytes to the location at CS[0] the FPGA can be programmed.
An example of this is provided in the SMT6041-498 software package available from SUNDANCE.

Virtex FPGA design

Once the FPGA has been programmed the user may then communicate with the design by means of CS regions 1, 2 and 3. 12 address lines allow for a total addressable space of 4kB per CS region. Accesses to these regions may be up to 64-bits wide.
An example of this is provided in the SMT6041-498 software package available from SUNDANCE
Page 11

Virtex II FPGA

The module can be fitted with an XC2VP70 or XC2VP100 FPGA. Only flip-chip FF1152 package will fit on this board. The choice of FPGA will be price/performance driven.
This Xilinx Virtex II Pro, is responsible for the provision of 5 SHBs, 2 Comports via the SHB user IO pins, a PCI Local bus interface, and 14 RSLs (see Ordering Information).

FPGA Block Diagram

SHBA
16-bit SDB
60
16-bit SDB
16-bit SDB
16-bit SDB
SHBC
60
SHBB
60
32-bit SDB
SHBE
32-bit SDB
60
16-bit SDB
16-bit SDB
SHBD
60
Com p o r t A
Com p o r t B
Comport
Local Bus
Interface
QuickLogic
Comport
Figure 4 - Default FPGA Configuration

Configuration

The FPGA can be configured in three different ways:
•Loading the FPGA on power up from flash on the board using System ACE SC.
•Using the SMT6041-498 utility to load the FPGA over the PCI bus.
•Using the on-board JTAG header and Xilinx JTAG programming tools. (See the Appendix for full details)

Memory

Two banks of DDR SDRAM are attached directly to the FPGA for storage of incoming data. Each bank consists of two 133 MHz DDR SDRAM components (Micron MT46V32M16FN or equivalent) providing a total of 128 MB of storage capacity on the module.
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