Sundance SMT407 User Manual

SMT407

User Manual

User Manual; Version 1.0.2, 4/8/04; © Sundance Digital Signal Processing, Inc. 2004

Version 1.0.0 Page 2 of 38 SMT407 User Manual

Revision History

Date Comments

Engineer Version

2/28/05 First released version PTM 1.0.0

Version 1.0.0 Page 3 of 38 SMT407 User Manual

Revision History....................................................................................................... 2

Table of Contents ..................................................................................................... 3

Table of Figures........................................................................................................ 6

Table of Tables ......................................................................................................... 6

Physical Properties.................................................................................................. 7

Introduction............................................................................................................... 8

Related Documents ................................................................................................ 8

Block Diagram .......................................................................................................... 8

Mechanical Interface: PMC Standard...................................................................... 9

SMT407 Support ....................................................................................................... 9

SMT407 Installation.................................................................................................. 9

QL5064 .................................................................................................................... 11

Local bus............................................................................................................... 11

Virtex FPGA configuration..................................................................................... 11

Virtex FPGA design .............................................................................................. 12

TI JTAG controller................................................................................................. 12

TMS320C6416T....................................................................................................... 13

Boot Mode............................................................................................................. 13

EMIF Control Registers......................................................................................... 13

SDRAM................................................................................................................. 14

FLASH .................................................................................................................. 14

Virtex FPGA.......................................................................................................... 15

FPGA ....................................................................................................................... 17

Configuration......................................................................................................... 17

JTAG/Boundary Scan........................................................................................ 17

Configuring with MultiLINX................................................................................ 18

SHBs..................................................................................................................... 19

SHB Connectors................................................................................................ 19

SHB Cable Assembly........................................................................................ 20

SHB Inter Modules solutions............................................................................. 20

Half Word Interface (16-bit SHB Interface)........................................................ 20

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Constraint File Signal Names............................................................................ 21

RSLs..................................................................................................................... 22

RSL Connector.................................................................................................. 22

RSL Cable Assembly......................................................................................... 23

RSL Interface .................................................................................................... 23

Local bus............................................................................................................... 23

Clocks................................................................................................................... 23

Miscellaneous I/O ................................................................................................. 24

Power Supplies..................................................................................................... 25

DC/DC converter............................................................................................... 26

Linear Voltage regulator.................................................................................... 26

Power Consumption.............................................................................................. 27

FPDP........................................................................................................................ 28

Further details....................................................................................................... 28

Software .................................................................................................................. 28

Further details....................................................................................................... 28

Verification Procedures ......................................................................................... 29

Review Procedures ................................................................................................ 29

Validation Procedures............................................................................................ 29

FPGA Constraint File General Information........................................................... 29

Ordering Information.............................................................................................. 29

FPGA-only ............................................................................................................ 29

With DSPs............................................................................................................. 29

Custom.................................................................................................................. 30

FPGA................................................................................................................. 30

Memories........................................................................................................... 30

DSPs................................................................................................................. 30

SHBs................................................................................................................. 30

RSLs.................................................................................................................. 30

PCB Layout Details ................................................................................................ 31

Components placement........................................................................................ 31

Headers Pinout ....................................................................................................... 33

SHB Headers........................................................................................................ 33

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SHB Pinout (LVTTL only) (J3,JA3).................................................................... 33

RSL Header.......................................................................................................... 34

RSL Side 1 Pinout (LVDS only) (J2).................................................................. 34

RSL Side 2 Pinout (LVDS only) (JA4) ............................................................... 34

JTAG/Multilinx headers......................................................................................... 35

JTAG Boundary scan pinout (J4) ...................................................................... 35

PMC Pn4 Header.................................................................................................. 36

PMC Pn4 Pinout (LVTTL only) (P14)................................................................. 36

Safety....................................................................................................................... 38

EMC ......................................................................................................................... 38

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Table of Figures

Figure 1: SMT407 Block Diagram............................................................................... 8

Figure 2: Single-size PMC card (from IEEE 1386-2001) ............................................ 9

Figure 3: QL5064 connection ................................................................................... 11

Figure 4: Flash logical sections ................................................................................ 15

Figure 5: JTAG Chain on the SMT407 ..................................................................... 18

Figure 6: SHB Connector.......................................................................................... 19

Figure 7: RSL Top Connector................................................................................... 22

Figure 8: RSL Bottom Connector.............................................................................. 22

Figure 9: FPDP daughter card .................................................................................. 28

Figure 10: SMT407 Components placement-Top view............................................. 31

Figure 11: SMT407 Components placement-Bottom view ....................................... 31

Figure 12: Location of JTAG/Multilinx header........................................................... 35

Figure 13: Top View IEEE 1386 Board-to-Board Plug.............................................. 36

Table of Tables

Table 1: FPGA Choices............................................................................................ 17

Table 2: RSL Speed vs. FPGA Speed Grade........................................................... 23

Table 3: LED Identification........................................................................................ 25

Table 4: Powering the devices.................................................................................. 25

Table 5: Power Consumption ................................................................................... 27

Table 6: SHB interfaces table................................................................................... 33

Table 7: RSL Side 1 interface table.......................................................................... 34

Table 8: RSL Side 2 interface table.......................................................................... 34

Table 9: JTAG Connector pinout.............................................................................. 35

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Physical Properties

Dimensions Single-sized PMC form factor Weight TBD g (FPGA only)

TBD g (with DSPs)

TBD g (with DSPs and daughter module) Supply Voltages See Power Supplies section Supply Current See Power Supplies section

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Introduction

Related Documents [1] PCI Mezzanine Card (PMC) Spec – IEEE.

http://shop.ieee.org/store/product.asp?prodno=SS94922

[2] Sundance High-speed Bus (SHB) specifications – Sundance.

http://sundance.com/docs/SHB%20Technical%20Specification.pdf

[3] Front Panel Data Port Spec – VITA.

http://www.fpdp.com

[4] External Interface User Manual – Sundance.

http://sundance.com/docs/Firmware.pdf

[5] Rocket Serial Link (RSL) specifications – Sundance.

http://sundance.com/docs/RSL%20%20Technical%20Specification%20Rev01%20Iss03.pdf

[6] Processor PMC (PrPMC) Spec – VITA.

http://www.vita.com/

Block Diagram

HPI/McBSP

R S

EMIFB

SDRAM

EMIFA

DSPA

Virtex II Pro

EMIFA

DSPB

PMC

SDRAM

P14

HPI/McBSP

Flash

PCI

Bridge

PCI

Host

Figure 1: SMT407 Block Diagram

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Mechanical Interface: PMC Standard

This module conforms to the PMC standard (PCI Mezzanine Card, See Related Documents.) for single width modules.

It requires a PMC carrier board. The carrier board provides power, ground, and a PCI bus between the module and

host, for a non stand-alone system.

Figure 2: Single-size PMC card (from IEEE 1386-2001)

SMT407 Support

The SMT407 is supported by the SMT6041-407 software package available from SUNDANCE. Please register on the SUNDANCE

Support Forum if not yet registered.

Then enter your company’s forum and you can request the SMT6041-407 from there.

SMT407 Installation

Do NOT connect any external TTL (5v) signals to the SMT407 I/Os which connect directly to the FPGA as the FPGA is NOT 5v tolerant. This implies that the lines on connector P14 of the carrier board MUST be LVTTL and that any device driving signals on the SHB connectors must drive at LVTTL (3.3v).

You can fit the SMT407 on its own on any PMC compatible carrier board. When mated with a carrier board such as Twin Industries Xtend1000, it may then be plugged into a host computer (e.g. Windows PC).

Please, follow these steps to install the SMT407 module on a Host system:

1. Remove the carrier board from the host system.

2. Connect the SHB and/or RSL cable(s) to the top side of SMT407 (if required by your application).

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3. Place the SMT407 module on a PMC site. (See your carrier board User Manual.)Make sure that the board is firmly seated before screwing the SMT407 to the two main mounting holes. Use 10mm M3 Standoffs(Digikey 4391K-ND)and M3 5mm bolts(Digikey H742-ND)to secure the module to any carrier card.

4. Connect the SHB and/or RSL cables to the back side of the SMT407 (if required by your application).

5. Replace the carrier board in the host system or power on for a stand-alone carrier.

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QL5064

The QuickLogic PCI bridge is installed on all configurations of SMT407. This device combines a 66MHz/64-bit PCI Master/Target ASIC core with a one-time

programmable (OTP) FPGA fabric.

The configuration of the FPGA fabric in the QL5064 is performed prior to manufacturing of the module and can not be changed by the user.

Local bus

QL5064 provides a bridge between the PCI bus of the host system and the Local bus of the SMT407. There are three primary functions of the Local bus on SMT407:

1) Configuration of the Virtex FPGA

2) Communication with logic designs loaded in the Virtex FPGA

3) Communication with DSPs over JTAG (applies to DSP boards only)

CS[3:0] CS[1]

TI JTAG controller

(DSP boards only)

Virtex FPGA config

Virtex FPGA design

PCI bus

66MHz/

64-bit

QL5064

50MHz/

64-bit

Local bus

16-bit

CS[0]

8-bit

CS[3:2]

64-bit

Figure 3: QL5064 connection

More information about the Local bus interface and protocols can be obtained from QuickLogic at:

http://www.quicklogic.com/images/QL5064_CD_UM.pdf

Virtex FPGA configuration

Programming of the Virtex FPGA can be achieved over the PCI bus using the SelectMAP interface. This interface is 8-bits wide and runs at the full speed of the Local bus. By simply writing a stream of configuration bytes to the location at CS[0] the FPGA can be programmed.

An example of this is provided in the SMT6041-407 software package available from SUNDANCE.

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Virtex FPGA design

Once the FPGA has been programmed the user may then communicate with the design by means of CS regions 2 and 3. 12 address lines allow for a total addressable space of 4kB per CS region. Accesses to these regions may be up to 64-bits wide.

An example of this is provided in the SMT6041-407 software package available from SUNDANCE.

TI JTAG controller

For DSP boards the Texas Instruments SN74ACT8990 is installed. This Test Bus Controller (TBC) provides XDS510 compatible performance.

Special driver software is required to operate this device. Please contact SUNDANCE for more information.

+ 26 hidden pages

Sundance SMT407 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Revision History

Table of Contents

Table of Figures

Table of Tables

Physical Properties

Introduction

Block Diagram

Mechanical Interface: PMC Standard

SMT407 Support

SMT407 Installation

QL5064

Local bus

Virtex FPGA configuration

Virtex FPGA design

TI JTAG controller