Sundance SMT399-160 User Manual
Sundance Multiprocessor Technology Limited
User Manual
Unit / Module Description: Multi-output DDS based SLB Mezzanine
Unit / Module Number: SMT399-160
Document Issue Number: 3
Issue Date: 24/05/2007
Original Author: PSR
Form : QCF42
Date : 6 July 2006
User Manual
for
SMT399-160
Sundance Multiprocessor Technology Ltd, Chiltern House, Waterside,
Chesham, Bucks. HP5 1PS.
This document is the property of Sundance and may not be copied nor
communicated to a third party without prior written permission.
© Sundance Multiprocessor Technology Limited 2006
User Manual SMT399-160 Last Edited: 24/05/2007 17:12:00
Revision History
Issue Changes Made Date Initial
1 Original Document 08/01/2007 PSR
2 Power consumption added 12/01/2007 PSR
3 Modification: MMBX connectors fitted 24/05/2007 SM
s
User Manual SMT399-160 Page 2 of 39 Last Edited: 24/05/2007 17:12:00
Table of Contents
1 Introduction............................................................................................... 6
2 Related Documents .................................................................................... 7
3 Examples of application. ............................................................................8
4 Functional Description............................................................................... 9
4.1 Block Diagram ................................................................................................................9
4.2 Module Description........................................................................................................9
4.3 SMT399-160 characteristics. .......................................................................................10
4.4 Power Supply structure. ...............................................................................................10
4.5 On-board crystal. ...........................................................................................................11
4.6 Output Variable Gain Amplifier....................................................................................11
4.7 Dau ghter sub-module interface. ...................................................................................11
4.8 Cascading modules.......................................................................................................11
4.9 Dual-tone Mode............................................................................................................12
4.10 External Trigger............................................................................................................ 12
4.11 LEDs..............................................................................................................................13
5 Control Register Settings...........................................................................13
5.1 Control Packet Structure .............................................................................................. 13
5.2 Reading and Writing Registers ....................................................................................14
5.3 Memory Map.................................................................................................................14
5.4 Register Descriptions ...................................................................................................16
5.4.1 Reset and Update Register – 0x0............................................................................16
5.4.2 Profile Register – 0x1. .............................................................................................18
5.4.3 VGA0 Register – 0x2...............................................................................................18
5.4.4 VGA1 Register – 0x3................................................................................................19
5.4.5 VGA2 Register – 0x4 ...............................................................................................19
5.4.6 VGA3 Register – 0x5. ..............................................................................................19
5.4.7 DDS0 Register – 0x6 – Control Function Register............................................... 20
5.4.8 DDS0 Register – 0x7 – Control Function Register................................................22
5.4.9 DDS0 Register – 0x8 – Control Function Register................................................23
5.4.10 DDS0 Register – 0x9 – Amplitude Scale Factor. ...................................................25
5.4.11 DDS0 Regis ter – 0xA – Amplitude Ramp Ra te. .....................................................25
5.4.12 DDS0 Register – 0xB – Frequency Tuning Word 0...............................................25
5.4.13 DDS0 Register – 0xC – Frequency Tuning Word 0...............................................26
5.4.14 DDS0 Register – 0xD – Phase Offset Word. ..........................................................26
5.4.15 DDS0 Register – 0xE – Frequency Tuning Word 1. ..............................................26
5.4.16 DDS0 Register – 0xF – Frequency Tuning Word 1................................................27
User Manual SMT399-160 Page 3 of 39 Last Edited: 24/05/2007 17:12:00
5.4.17 DDS0 Register – 0x10 – RAM Segment Control Word 0. .....................................27
5.4.18 DDS0 Register – 0x11 – RAM Segment Control Word 0.......................................27
5.4.19 DDS0 Register – 0x12 – RAM Segment Control Word 0. .................................... 28
5.4.20 DDS0 Register – 0x13 – RAM Segment Control Word 1...................................... 28
5.4.21 DDS0 Register – 0x14 – RAM Segment Control Word 1...................................... 28
5.4.22 DDS0 Register – 0x15 – RAM Segment Control Word 1...................................... 28
5.4.23 DDS0 Register – 0x16 – RAM Segment Control Word 2.......................................29
5.4.24 DDS0 Register – 0x17 – RAM Segment Control Word 2.......................................29
5.4.25 DDS0 Register – 0x18 – RAM Segment Control Word 2. .....................................29
5.4.26 DDS0 Register – 0x19 – RAM Segment Control Word 3.......................................29
5.4.27 DDS0 Register – 0x1A – RAM Segment Control Word 3. .................................... 30
5.4.28 DDS0 Register – 0x1B – RAM Segment Control Word 3. .................................... 30
5.4.29 DDS0 Register – 0x1C – Falling Delta Frequency Tuning.................................... 30
5.4.30 DDS0 Register – 0x1D – Falling Delta Frequency Word.......................................31
5.4.31 DDS0 Register – 0x1E – Falling Sweep Ramp Rate Word. ................................... 31
5.4.32 DDS0 Register – 0x1F – Rising Delta Frequency Tuning...................................... 31
5.4.33 DDS0 Register – 0x20 – Rising Delta Frequency Word........................................32
5.4.34 DDS0 Register – 0x21 – Rising Sweep Ramp Rate Word......................................32
6 PCB Layout............................................................................................... 33
6.1 Top View .......................................................................................................................33
6.2 Bottom View..................................................................................................................34
7 Connector Location.................................................................................. 35
8 Support Packages..................................................................................... 36
9 Physical Properties .................................................................................. 37
10 Safety .......................................................................................................38
11 EMC ......................................................................................................... 39
User Manual SMT399-160 Page 4 of 39 Last Edited: 24/05/2007 17:12:00
Table of Figures
Figure 1 - Examples of applications..............................................................................................8
Figure 2 - SMT399-160 Block Diagram. ......................................................................................9
Figure 3 - Output main characteristics. .....................................................................................10
Figure 4 - Connections for cascading modules. ..........................................................................11
Figure 5 - Multi module synchronisation connectors................................................................12
Figure 6 - Dual-Tone Mode. .......................................................................................................12
Figure 7 – Setup Packet Structure..............................................................................................13
Figure 8 – Control Register Read Sequence. .............................................................................14
Figure 9 – Register Memory Map. .............................................................................................16
Figure 10 - Layout - Top Side. ....................................................................................................33
Figure 11 - Layout - Bottom Side. ...............................................................................................34
Figure 12 - Connector Location. ................................................................................................ .35
User Manual SMT399-160 Page 5 of 39 Last Edited: 24/05/2007 17:12:00
1 Introduction
The SMT399-160 is a multi-output mezzanine single width module, which is able to generate
sine waves at up to 160MHz. This mezzanine board is to be fitted on one of Sundance SLB
(Sundance LVDS Bus) base modules, such as
cannot be used on its own. It is built around two
Analog Devices) featuring
are separately programmable, can contain up to 4 profiles and have the possibility of being
synchronised. The architecture allows generating single-tone or dual-tone signals. DDS
outputs are split into two legs, each of them featuring a programma ble amplifier (VGA). The
SMT399-160 has got in total two pairs of outputs.
A Xilinx FPGA Virtex-II Pro (or Virtex4) from the base module, is used to control DDSs and
Variable Gain Amplifiers (VGAs) of the SMT399-160, after receiving command words via a
Comport.
SMT399-160 modules can be cascaded and work into the AD9954 Master/Slave mode.
14-bit DAC operating/sampling at up to 400 MHz. Both devices
SMT338-VP or SMT398-VP or SMT368 and
AD9954s, Direct Digital Synthesizer (DDS –
PCB connectors are
It can be used in the following application:
- Radio systems, as a clock generator (fine tuning),
- Test systems (dual tone and fast hopping),
- Programmable system (software programmable),
- Etc…
MMBXs from Hubert Suhner.
User Manual SMT399-160 Page 6 of 39 Last Edited: 24/05/2007 17:12:00
2 Related Documents
AD9954 Datasheet - Analog Devices:
http://www.analog.com/Analog_Root/productPage/productHome/0,2121,AD9954,00.html
Sundance High-speed Bus (SHB) specifications – Sundance.
ftp://ftp2.sundance.com/Pub/documentation/pdf-files/SHB_Technical_Specification.pdf
Sundance LVDS Bus (SLB) – Sundance.
http://www.sundance.com/docs/SLB%20-%20Technical%20Specifications.pdf
TIM specifications - TI.
ftp://ftp2.sundance.com/Pub/documentation/pdf-files/tim_spec_v1.01.pdf
Xilinx Virtex-II PRO FPGA - Xilinx.
http://direct.xilinx.com/bvdocs/publications/ds083.pdf
MMBX Connectors – Hubert Suhner.
MMBX Connectors
User Manual SMT399-160 Last Edited: 24/05/2007 17:12:00
3 Examples of application.
The SMT399-160 module can be used in the following application:
- Radio systems
. Compatible with Sundance’s TIM Modules, it can be combined with
DAQ modules such as ADCs and DACs, as a clock generator. The SMT399-160 finetuning makes it even more suitable for such platform to generate up-to-four
synchronised and/or quadrature signals.
- Test systems
. It is sometimes very helpful to have a signal generator capable of
generators various frequencies to evaluate some radio system. Fast hopping is the key
word here. Dual tone signals are useful to characterise a receiver system to evaluate
its capabilities of receiving signals close to each other in frequency. DDSs also to
generate a ramp, a pattern or a frequency sweep.
- Programmable system
. As most of system, it a very important top control every part
of a system. The SMT399-160 is fully controllable via software.
- Etc…
As both pairs of DDSs are synchronised and coupled master/slave, the module can generate
90-degree phase shift signals and be part of a quadrature modulator system.
Ext. Clk ADCs
Ext. Clk DAC
SMT370
Dual ADC/DAC
Analogue Converters
ChA0
ChA1
Up to 160MHz
Quadrature
Ext.
Clock
SMT390-VP
Dual 210-MSPS ADC
Analogue Converters
I
Q
ChA0
Up to 160MHz
ChA1
SMT399-160
ChB0
ChB1
Channel A and Channel B
synchronised
Dual Quadrature Sampling
Up to 160MHz
Quadrature
Ext.
Clock
SMT390-VP
Dual 210-MSPS ADC
Analogue Converters
SMT399-160
SMT399-160
ChB0
I
All channels synchronised
ChB1
Q
Multi-DAQ synchronisation
ChA0
ChA1
ChB0
ChB1
Up to 160MHz
Up to 160MHz
or test pattern
Ext.
Clocks
Analog
Inputs
SMT390-VP
Dual 210-MSPS ADC
Analogue Converters
Sampling with test pattern
Up to 160MHz
Ext. Clk ADCs
Ext. Clk DAC
SMT370
Dual ADC/DAC
Analogue Converters
Figure 1 - Examples of applications.
User Manual SMT399-160 Last Edited: 24/05/2007 17:12:00
4 Functional Description
In this part, we will see the general block diagram and some comments on the main entities.
4.1 Block Diagram
The following diagram shows the block diagram of the SMT399-160.
Sundance SLB base
module (SMT338-VP,
SMT398-VP or SMT368
for example)
68 I/O pins
+3.3V, +5V
SMT399-160 SLB
Syn
in
squ
are
A
TrigATrig
B
External
Reference
(Option)
On-board
Crystal
I/Os
I/Os
Daughter Module - SMT399-160
Figure 2 - SMT399-160 Block Diagram.
I/Os
1xAD9954 DDS (Channel A)
14-bit @ 400MSPS
48-pin TQFP
Synchronisation
1xAD9954 DDS (Channel B)
14-bit @ 400MSPS
48-pin TQFP
I/Os
Syn
out
AD8370
VGA
AD8370
VGA
AD8370
VGA
AD8370
VGA
A0
A1
B0
B1
squ
are
B
4.2 Module Description
The module is built around two Direct Digital Synthesizers (DDS): two AD9954.
The AD9954 is a DDS featuring 14-bit DAC operating at up to 400MSPS. It forms a digitally
programmable high frequency synthesizer capable of generating an analog output sinusoidal
waveform at up to 160MHz. The AD9954 provides fast frequency hopping and fine-tuning
resolution (32-bit frequency tuning word). The AD9954 includes an integrated 1024x32 static
RAM to support flexible frequency sweep capability in several modes. It also supports a user
defined linear sweep mode of operation. The frequency resolution of the AD9954 is 0.0931
Hz when clocked at 400MHz. Both analog outputs can be linked together via jumpers in
order to generate a dual tone signal.
User Manual SMT399-160 Last Edited: 24/05/2007 17:12:00
DDS outputs are doubled and combined with Variable Gain Amplifiers (VGA).
Analog signals are all single-ended and output on MMBX connec tors (J13, J14, J15 and J20)
for connection to a 50-Ohm load.
Output Sine waves can be turned into ‘sharp’ square signals using the AD9954 built-in
comparator. Square signals (one per DDS) are also available on MMBX connectors (J24 and
J25) on LVTTL format.
All DDS settings travel via the FPGA present on SLB base module. Information comes from a
Comport and the FPGA stores it first into internal registers and interfaces it to the DDS chips
via the SLB connector. Comports follow the Texas Instrument C4x standard.
4 green LEDs are also available and driven by the FPGA to report working or failing
conditions to the user. Other green LEDs show that all power supplies are ON and working.
Two external triggers (J11 and J23) are also available.
4.3 SMT399-160 characteristics.
Analog Outputs (J13, J14, J15 and J20).
0 to 2.12 Volts without saturation (sine wave)
Analog Output Voltage Range
Output Impedance
Frequency range
Frequency resolution
Square Outputs (J24 and J25).
Output Format
Frequency range
Frequency Resolution
External Triggers (J11 and J23).
Input Range
Frequency Range
Input Reference (Option – J21)
Frequency range
Figure 3 - Output main characteristics.
0 to 3.0 Volts with saturation
(Output level set via Control Register - VGA)
Terminated to be connected to a 50-Ohm load.
Up to 160 MHz
0.0931 Hz
LVTTL
Up to 160 MHz
0.0931 Hz
LVTTL (default FPGA PAD setting)
Up to 160 MHz
0 to 400 MHz.
4.4 Power Supply structure.
The SMT399-160 conforms to the TIM standard for single width modules. The TIM
connectors supply 5 Volts to the base module, which also requires an additional 3.3-Volt
power supply, which must be provided by the two diagonally opposite mounting holes. This
3.3-volt is present on all Sundance TIM carrier boards. From these two power rails, are
generated a filtered 3.3-volt as well as a 1.8-volt source for both
Greens LEDs placed on the board report the state of the power supplies.
The SMT399-160 requires 2 power rails from the SLB power connector: +3.3 and +5 Volts.
User Manual SMT399-160 Page 10 of 39 Last Edited: 24/05/2007 17:12:00
AD9954s.
4.5 On-board crystal.
The AD9954 are clocked from a crystal (20MHz). The master DDS then passes the sampling
clock to the slave DDS to ensure synchronisation. Synchronisation can also be achiev ed when
cascading several SMT399-160 daughter modules. There is an automatic synchronisation
available from the DDS registers.
4.6 Output Variable Gain Amplifier.
Each output is driven by a Variable Gain Amplifier (VGA – AD8370), digitally controlled that
uses 8 bits to code the gain and provides a power-down mode. Two ranges of gains are
available: from –11 to +17dBs or from +6 to +34dBs.
4.7 Daughter sub-module interface.
The link between the main and the daughter sub-module is made via two Samtec connec tors.
There is no fast signal travelling between both cards. The first connector passes control
signals and the second one passes a 3.3-volt and 5-volt s upplies and a ground between submodules.
The female differential connector is located on the m ain module. The Samtec Part Number
for this connector is QTH-060-01-F-D-DP-A.
The female power connector is located on the main module. The Samtec Part Numbe r for this
connector is BKS-133-03-F-V-A
The male differential connector is located on th e daughter card. The S amtec Part Nu mber for
this connector is QSH-060-01-F-D-DP-A
The male power connector is located on the daughter card. The Samtec Part Nu mber for this
connector is BKT-133-03-F-V-A
The mated height between the main module and the daughter card is 5 mm.
4.8 Cascading modules
Several SMT399-160s can be cascaded. All DDSs can be synchronised by linking the modul es
via connectors J1 and J3, both are 2-mm 3-pin head ers. J1 of the master module should be
connected to J3 of the slave module as follows:
SMT399-160
Master (J1)
Crystal Out
(J1 – pin 1)
Gnd
SMT399-160
Slave (J3)
Crystal In
(J3 – pin 3)
Gnd
(J1 – pin 2)
Synch In
(J1 – pin 3)
Figure 4 - Connections for cascading modules.
User Manual SMT399-160 Page 11 of 39 Last Edited: 24/05/2007 17:12:00
(J3 – pin 2)
Synch Out
(J3 – pin 1)
Figure 5 - Multi module synchronisation connectors.
4.9 Dual-tone Mode.
The SMT399-160 can used as a dual-tone generator. Both DDS outputs can be mixed
together. In this case, all four analog outputs (J13, J14, J15 and J20) would show the same
signal, at relevant amplitudes.
To configure the SMT399-160 into the dual-tone mo de, simply fit J16, J17, J18 and J19 in
place.
The normal mode of operation is obtained by leaving J16, J17, J18 and J19 open.
Figure 6 - Dual-Tone Mode.
4.10 External Trigger.
Two external triggers are available on J23 and J11. Both are straight through, i.e. the
connector is directly connected to the FPGA. There is no protection so it is to the user to
make sure levels present on the connector are compatible with th e pad implemented in the
FPGA. In the default firmware provided, J23 is connected to LED1 and J11 to LED3 (see
silkscreen for LED locations).
User Manual SMT399-160 Page 12 of 39 Last Edited: 24/05/2007 17:12:00
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