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SMT398VP
User Manual
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Sundance SMT398VP User Manual

USER GUIDE
FOR
SMT398VP
Copyright © Sundance
All rights reserved. No part of this document may be reproduced, translated,
stored in a retrieval system, or transmitted, in any form or by any means,
written permission of the owner.
If this copy is no longer in use, return to sender.
SMT398VP-D000058H-guide.doc
Document No.
Note:
Revision
2.4.2
Date
Page 1 of 34
08/02/07

APPROVAL PAGE

Name Signature Date

AUTHOR/S

Name Signature Date
E. Puillet 29/01/2005 G. Parker 9/12/2005
SMT398VP-D000058H-guide.doc
Document No.
Revision
2.4.2
Date
Page 2 of 34
08/02/07

DOCUMENT HISTORY

Date Initials Revision Description of change
06/05/06 E.P 2.0 New document 12/07/06 E.P 2.0.1 Update of figure 5 28/07/06 E.P 2.0.2 Update of figure 3 02/08/06 E.P 2.1 Addition of SMT398VP Reset scheme. 21/08/06 E.P 2.2 Addition of JTAG Header pinout. 25/08/06 E.P 2.3 Update of RSLs’ pinout. 18/09/06 E.P 2.4 Clarifications on clock synthesizer crystal frequency.
Update of board Top view with T1.
19/09/06 E.P 2.4.1 Correction of the amount of Leds available.
Addition of TIM connector reference in chapter Pinout.
08/02/07 E.P 2.4.2 Clarification of Switch name and positions.
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Document No.
Revision
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TABLE OF CONTENTS

1. SCOPE.................................................................................................................................................................................7
1.1. INTRODUCTION ............................................................................................................................................................7
1.2. PURPOSE ......................................................................................................................................................................7
1.3. APPLICABILITY ............................................................................................................................................................7
2. APPLICABLE DOCUMENTS AND REFERENCES....................................................................................................8
2.1. APPLICABLE DOCUMENTS............................................................................................................................................8
2.1.1. External Documents ...............................................................................................................................................8
2.1.2. Internal documents.................................................................................................................................................8
2.1.3. Project Documents .................................................................................................................................................8
2.2. REFERENCES ................................................................................................................................................................8
2.2.1. External documents................................................................................................................................................8
2.2.2. Internal documents.................................................................................................................................................8
2.2.3. Project documents..................................................................................................................................................8
2.3. PRECEDENCE................................................................................................................................................................8
3. ACRONYMS, ABBREVIATIONS AND DEFINITIONS ............................................................................................10
3.1. ACRONYMS AND ABBREVIATIONS..............................................................................................................................10
3.2. DEFINITIONS ..............................................................................................................................................................10
4. FEATURES.......................................................................................................................................................................11
4.1. THE SMT398VP TIM ................................................................................................................................................11
4.1.1. SMT398VP Diagram............................................................................................................................................11
4.1.2. Interface Definition ..............................................................................................................................................12
4.1.3. Major features......................................................................................................................................................12
4.1.4. Prime Item Characteristics...................................................................................................................................12
4.1.5. Performance.........................................................................................................................................................20
4.1.6. Physical Characteristics.......................................................................................................................................21
5. FOOTPRINT ....................................................................................................................................................................23
5.1. TOP VIEW ..................................................................................................................................................................23
5.2. BOTTOM VIEW...........................................................................................................................................................24
6. PINOUT.............................................................................................................................................................................25
6.1. FPGA ........................................................................................................................................................................25
6.1.1. RSLs ......................................................................................................................................................................25
6.2. CONNECTORS.............................................................................................................................................................27
6.2.1. RSLs ......................................................................................................................................................................27
6.3. SHB...........................................................................................................................................................................29
6.4. SLB ...........................................................................................................................................................................29
6.5. JTAG.........................................................................................................................................................................29
6.6. TIM CONNECTORS.....................................................................................................................................................30
7. ORDERING INFORMATION........................................................................................................................................31
8. QUALIFICATION REQUIREMENTS .........................................................................................................................32
8.1. QUALIFICATION TESTS...............................................................................................................................................32
8.1.1. Meet Sundance standard specifications ...............................................................................................................32
8.1.2. Speed qualification tests.......................................................................................................................................33
8.1.3. Integration qualification tests...............................................................................................................................33
9. HARDWARE SUPPORT PACKAGE............................................................................................................................34
Document No.
Revision
Date
Page 4 of 34
SMT398VP-D000058H-guide.doc
2.4.2
08/02/07

TABLE OF FIGURES

Figure 1: Block Diagram.............................................................................................................................11
Figure 2: CPLD state machine.....................................................................................................................14
Figure 3: FPGA connections to Bank1 of QDRII .......................................................................................15
Figure 4: Clocking distribution diagram .....................................................................................................19
Figure 5: Top View......................................................................................................................................23
Figure 6: Bottom View................................................................................................................................24
Figure 7: JTAG connector Top View..........................................................................................................29
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Revision
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TABLE OF TABLES

Table 1: Communication standard supported by Rocket IO transceivers...................................................17
Table 2: DIP switch for special reset feature...............................................................................................18
Table 3: DIP switch for the selection of the configuration bitstream source..............................................18
Table 4: Clock synthesizer Configurations for Rocket IO standard application.........................................20
Table 5: Power budget.................................................................................................................................21
Table 6: QDR II termination scheme...........................................................................................................22
Table 7:RSL reference clocks......................................................................................................................25
Table 8:RSL-TOP (J5) connector Type A...................................................................................................27
Table 9: RSL-BOTTOM (J6) connector Type B.........................................................................................27
Table 10:RSL-TOP (J3) connector Type B.................................................................................................28
Table 11: RSL-BOTTOM (J4) connector Type A ......................................................................................28
Table 12: JTAG connector pinout. ..............................................................................................................30
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Document No.
Revision
2.4.2
Date
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08/02/07

1. SCOPE

This document provides practical information on the resources available on the SMT398VP. It also describes how to use the features of SMT398VP FPGA Tim module.

1.1. INTRODUCTION

The SMT398VP is an FPGA TIM module designed to be integrated in modular systems. It is designed to connect to the huge range of other TIM modules and carriers developed by
Sundance. Sundance modular solutions provide flexible and upgradeable systems. The SMT398VP is a TIM module aimed at completing the range of Sundance Virtex II-Pro
FPGA modules like SMT351, SMT338-VP, SMT387 and SMT395.
It provides a communications platform between an XC2VP70 Virtex-II Pro FPGA and
• On-board Double Data Rate Dual Port QDR II memory at frequencies of up to
200MHz.
• Rocket IOs for high speed serial connections capable of various high-speed serial
standards.
• LVDS connections for high speed parallel connections
• LVTTL connections and connectors.
This variety of connectors and interfaces provides a wide range of development options for designers to explore the capabilities of the comprehensive Sundance TIM modules and carriers family.

1.2. PURPOSE

The SMT398VP provides:
• High-speed interface to Sundance ADC/DAC modules/mezzanines.
• High-speed interface to Sundance DSP modules.
• High-speed interface to a Host via Sundance RSL carriers. (SMT145)
• Provide high-speed serial or parallel interface to the outside world.
• Fit in any configuration on Sundance carriers, i.e on its own, on a stand-alone carrier or
in a Host as part of a system.

1.3. APPLICABILITY

Interface to other FPGA, DSP, ADC/DAC modules and in stand alone systems.
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Revision
2.4.2
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2. APPLICABLE DOCUMENTS AND REFERENCES

2.1. APPLICABLE DOCUMENTS

2.1.1. External Documents

TI TIM specification & user’s guide. Samtec QSH Catalogue page Samsung QDR II Datasheet Virtex II Pro Datasheet

2.1.2. Internal documents

SUNDANCE SDB specification. SUNDANCE SHB specification SUNDANCE SLB specification SUNDANCE RSL specification SUNDANCE SMT6500 SUNDANCE SMT6400 Sundance Help file
Sundance D000110-spec.pdf clock synthesizer FPGA task design.

2.1.3. Project Documents

D000058H-proj.mpp Software Planning Document for SMT398VP.

2.2. REFERENCES

2.2.1. External documents

N.A

2.2.2. Internal documents

N.A

2.2.3. Project documents

N.A

2.3. PRECEDENCE

In the event of conflict between the text of this document, and the applicable documents cited herein, the text of this document takes precedence. Nothing in this document however,
SMT398VP-D000058H-guide.doc
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Revision
2.4.2
Date
Page 8 of 34
08/02/07
supersedes applicable laws and regulations unless a specific exemption has been obtained and is identified in the text of this document.
SMT398VP-D000058H-guide.doc
Document No.
Revision
2.4.2
Date
Page 9 of 34
08/02/07

3. ACRONYMS, ABBREVIATIONS AND DEFINITIONS

3.1. ACRONYMS AND ABBREVIATIONS

TIM Texas Instruments Module TI© DSP Texas Instrument Digital Signal Processor Xilinx©
Xilinx© Field Programmable Gate Array.
FPGA QDR Quad Data Rate CP ComPort. Communication interface SDB Sundance Digital Bus. Communication interface SHB Sundance High-Speed Bus. Communication interface RSL Rocket io Serial Link. Communication interface MGT Multi Gigabit Transceiver

3.2. DEFINITIONS

DSP Module Typically a TIM module hosting a TI DSP and, a Xilinx FPGA. FPGA-only Module A TIM with no on-board DSP, where the FPGA provides all
functionality.
Firmware A proprietary FPGA design providing some sort of functionality.
Sundance Firmware is the firmware running in an FPGA of a DSP module.
SMT398VP-D000058H-guide.doc
Document No.
Revision
2.4.2
Date
Page 10 of 34
08/02/07

4. FEATURES

4.1. THE SMT398VP TIM

This module conforms to the TIM standard (Texas Instrument Module, See TI TIM
specification & user’s guide) for single width modules.
It sits on a carrier board. The carrier board provides power, Ground, communication links (ComPort links, RSL links)
between all the modules fitted and a pathway to the host, for a non stand-alone system. The SMT398VP requires an additional 3.3V power supply (as present on all Sundance TIM
carrier boards), which must be provided by the two diagonally opposite mounting holes.

4.1.1. SMT398VP Diagram

Figure 1 shows a simplified version of the SMT398VP module.
JTAG Header
JTAG
Xilinx Coolrunner II
CPLD XC2C128VQ100
on Comport[0;3] and
Config&control
4 Mbytes QDR II-SRAM
2x (512kx36)
4 LEDs or
4 I/O pins
PROM
XCF32PVO48
JTAG
16 I/O pins
208 I/O pins; 36-bit data
50MHz
Oscillator
Virtex-II Pro FF1517
852 to 964 I/O Pins
48 I/O pins
4x Comm-Port/SDL
25MHz Crystal
Clock
Synthesizer
FPGA
XC2VP70
1.5V Core
1.5V/3.3V I/O
External
clock
MMCX
(optional)
120 I/O pins
20 differential pairs
40 TTL IOs
16 RocketIO links
24 I/O pins
2x Comports/SDL
5 I/O pins
Interrupts&Reset
Sundance High
speed Bus (2 Conn.)
Sundance Low
voltage Bus (1 Conn.)
Sundance Rocket io
Serial Link (4 Conn.)
J2 Bottom Primary TIM
Connector
4xComport/SDL 1;2;4 & 5
Figure 1: Block Diagram
SMT398VP-D000058H-guide.doc
Document No.
Revision
2.4.2
J1 Top Primary TIM
Connector
Comport 0 & 3
Date
Page 11 of 34
08/02/07
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