Sundance SMT398 User Manual
SMT398
User Manual
Version 1.2.0 Page 2 of 52 SMT398 User Manual
Revision History
Date Comments
Engineer Version
18.07.03 First released version E.P 1.0.0
22.08.03 TIM CONFIG signal feature described E.P 1.1.0
27.08.03 Minor corrections E.P 1.1.1
05.09.03 Detailed description of FPGA I/Os constraint
E.P 1.1.2
file signal names.
14.10.03 Addition of SHB connector names A, B ,C ,D. E.P 1.1.3
28.10.03 Addition of figure 12 and details about pInout
E.P 1.1.4
for SHB connectors in basic or full
configuration
02.11.03 Minor clarification about the ZBTRAM Memory
E.P 1.1.5
banks available depending on the board
configuration and speed grade
27.07.04 Update of the Reset Control section to be more
E.P 1.1.6
explicit about the various ways of handling
reset control.
01.12.04 Removed statement saying that the
E.P 1.1.7
FPGAfullconfig and loadbitstream code can be
recompiled for any C6x-processor-board to use
under Code Composer Studio and/or 3L
Diamond.
12.01.05 Block Diagram update: removed wrong CPLD
E.P 1.1.8
description (Timer)
20.05.05 Added: Start and End keys values SM 1.1.9
17.10.05 Changed: Hyperlink for ZBTRAM datasheets SM 1.2.0
Version 1.2.0 Page 3 of 52 SMT398 User Manual
Table of Contents
Revision History.......................................................................................................... 2
Table of Contents....................................................................................................... 3
Table of Figures.......................................................................................................... 6
Table of Tables........................................................................................................... 6
Physical Properties..................................................................................................... 8
Introduction................................................................................................................. 9
Related Documents ................................................................................................ 9
Block Diagram............................................................................................................ 9
Mechanical Interface: TIM Standard......................................................................... 10
SMT398 Support ...................................................................................................... 10
SMT398 Installation.................................................................................................. 10
SMT398 Alone...................................................................................................... 10
SMT398 + DSP TIM.............................................................................................. 12
FPGA Configuration ................................................................................................. 13
Electrical Interface.................................................................................................... 13
The service CPLD................................................................................................. 13
CPLD Functions................................................................................................ 14
Virtex II Bitstream Format.................................................................................. 19
Bitstream Re-formatting..................................................................................... 20
CPLD code versions.......................................................................................... 20
FPGA.................................................................................................................... 20
FPGA in system programming .......................................................................... 22
JTAG/Boundary Scan........................................................................................ 23
Configuring with MultiLINX................................................................................ 24
FPGA Readback and Partial reconfiguration..................................................... 24
Memory................................................................................................................. 25
Pipelined ZBTRAM............................................................................................ 25
Constraints File Signal Names.......................................................................... 27
QDR (Quad Data Rate)..................................................................................... 27
Constraints File Signal Names.......................................................................... 29
Comports .............................................................................................................. 29
Version 1.2.0 Page 4 of 52 SMT398 User Manual
Constraints File signal Names........................................................................... 31
SHB ...................................................................................................................... 31
SHB Connector ................................................................................................. 31
SHB Cable Assembly........................................................................................ 33
SHB Inter Modules solutions............................................................................. 33
Half Word Interface (16-bit SHB Interface)........................................................ 33
Constraint File Signal Names............................................................................ 34
Global bus............................................................................................................. 36
Constraints File Signals Names ........................................................................ 37
Clocks................................................................................................................... 37
Constraints file signal Names............................................................................ 38
Power Supplies..................................................................................................... 38
DC/DC Converter .............................................................................................. 39
Linear Voltage regulator.................................................................................... 40
Fan.................................................................................................................... 40
Power Consumption.............................................................................................. 40
Verification Procedures ............................................................................................ 41
Review Procedures .................................................................................................. 41
Validation Procedures .............................................................................................. 41
FPGA Constraint File general Information................................................................ 41
Ordering information:................................................................................................ 43
Full configuration................................................................................................... 43
Basic configuration................................................................................................ 44
Memories........................................................................................................... 44
SHBs................................................................................................................. 44
Comports........................................................................................................... 44
Global Bus......................................................................................................... 45
External Clock................................................................................................... 45
PCB Layout Details .................................................................................................. 46
Components placement........................................................................................ 46
Headers Pinout......................................................................................................... 48
SHB Header.......................................................................................................... 48
SHB Pinout (LVTTL only).(J8-J9-J10-11).......................................................... 49
Version 1.2.0 Page 5 of 52 SMT398 User Manual
JTAG/Multilinx headers......................................................................................... 50
JTAG/Boundary scan pinout (J13) .................................................................... 50
MultiLINX SelectMap Pin Descriptions (J12-J13).............................................. 51
Safety ....................................................................................................................... 52
EMC ......................................................................................................................... 52
Version 1.2.0 Page 6 of 52 SMT398 User Manual
Table of Figures
Figure 1:SMT398 Block Diagram.............................................................................................9
Figure 2: FPGA configuration in SelectMap mode using CPLD.............................................14
Figure 3: Comport word Byte order........................................................................................15
Figure 4: CPLD state machine...............................................................................................16
Figure 5: V II Configuration Bitstream Word Format..............................................................20
Figure 6: JTAG Chain on the SMT398...................................................................................23
Figure 7:SMT398 ZBT Memory Banks arrangement .............................................................26
Figure 8: ZBT Constraints file signal names ..........................................................................27
Figure 9:SMT398 QDR Width expansion arrangement..........................................................28
Figure 10: QDR Constraints file signal names.......................................................................29
Figure 11:SMT398 Comports connections.............................................................................30
Figure 12: Comport Constraints file signal name...................................................................31
Figure 13: SHB Connector.....................................................................................................32
Figure 14: SHB constraints file control signals names...........................................................35
Figure 15: SHB constraints file data signals names...............................................................35
Figure 16: SHB constraints file User pins signals names.......................................................36
Figure 17: Global Bus constraints file signal names. .............................................................37
Figure 18: DC/DC converter dimensions (in inches)..............................................................39
Figure 19:SMT398 Components placement-Top view...........................................................46
Figure 20: SMT398 Components placement-Bottom view.....................................................47
Figure 21: Top View QSH 30 .................................................................................................48
Figure 22: Top View of JTAG/Multilinx headers.....................................................................50
Table of Tables
Table 1: FPGA Choices.......................................................................................................... 21
Table 2: ZBTRAM sizes .........................................................................................................26
Table 3: QDR RAM sizes.......................................................................................................28
Table 4: External clock specification......................................................................................38
Table 5: powering the devices................................................................................................39
Table 6: Duplicate pins...........................................................................................................42
Table 7: Virtex II, ZBT/QDR combinations in FULL configuration..........................................44
Table 8: Virtex II, ZBT combinations in BASIC configuration.................................................45
Table 9: SHB interfaces table.................................................................................................49
Table 10: Connector J13-JTAG Header.................................................................................50
Version 1.2.0 Page 7 of 52 SMT398 User Manual
Table 11: Connector J13-Flying Lead Set #1.........................................................................51
Table 12: Connector J12 Flying Lead Sets 3&4.....................................................................52
Version 1.2.0 Page 8 of 52 SMT398 User Manual
Physical Properties
Dimensions See Physical specifications of TI TIM specification &
user’s guide
Weight Varies in function of board configuration
Supply Voltages See Power Supplies
Supply Current See Power Supplies
Version 1.2.0 Page 9 of 52 SMT398 User Manual
Introduction
Related Documents
SUNDANCE SHB specification
Sundance SDB specification.
TI TIM specification & user’s guide.
Samtec QSH Catalogue page
SMT6500 help file: FPGA support package
Block Diagram
SelectMAP Header
JTAG Header
Xilinx XC95288 CS280 CPLD
or Sundance High-speed Bus
on Comm-Port #0 and #3
and Config&Reset
Sundance Digital Bus
connector x4
4 LEDs or
4 I/O pins
16 I/O pins
240 I/O Pins
J1 Top Primary TIM
Connector
Comm-Port 0 & 3
24 I/O pins
2x Comm-Ports/SDL
Interrupts&Reset
FPGA
Virtex-II FF896/1152
XC2V1000 - XC2V8000
432 to 824 I/O Pins
1.5V Core
1.5V/3.3V I/O
5 I/O pins
On-board
Oscillator
External Clock
120 I/O pins; 16-bit data
183 I/O pins; 16-bit data
Clk
2, 4 Mbytes QDR-SRAM
2x (1 or 2Mx18)
2,4,8 or 16Mbytes ZBT-
RAM as SMT358
J3 Global Expansion
Figure 1:SMT398 Block Diagram
Connector
78 I/O pins
Global Bus
48 I/O pins
4x Comm-Port/SDL
J2 Bottom Primary TIM
Connector
4xComm-Port/SDL 1;2;4 & 5
Version 1.2.0 Page 10 of 52 SMT398 User Manual
Mechanical Interface: TIM Standard
This module conforms to the TIM standard (Texas Instrument Module, See TI TIM
specification & user’s guide.) for single width modules.
It sits on a carrier board.
The carrier board provides power, Ground, communication links (Comport links)
between all the modules fitted and a pathway to the host, for a non stand-alone
system.
The SMT398 requires an additional 3.3V power supply (as present on all Sundance
TIM carrier boards), which must be provided by the two diagonally opposite mounting
holes.
SMT398 Support
The SMT398 is supported by the SMT6500 software package available from
SUNDANCE. Please register on SUNDANCE
Then enter your company’s forum and you can request the SMT6500 from there.
Support Forum if not yet registered.
SMT398 Installation
Do NOT connect any external TTL (5v) signals to the SMT398 I/Os as the FPGA
is NOT 5v compliant. This implies that the Comports and global bus lines of
the carrier board MUST be LVTTL and that any device driving signals on the
SHB connectors must drive at LVTTL (3.3v).
Two types of configuration are described here; nevertheless, you shouldn’t be
restricted and should consult Sundance if your system architecture differs.
SMT398 Alone
You can fit the SMT398 on its own, on the first TIM site of one of Sundance’s 3.3v
compatible carrier boards plugged in a host computer (PC, PCI, VME carrier etc…),
like SMT310Q, SMT328, SMT300 etc…)
Please, follow these steps to install the SMT398 module on a Host system:
1. Remove the carrier board from the host system.
2. Place the SMT398 module on the first TIM site. This TIM site communicates
with the host. (See your carrier board User Manual.) This allows you to use
Global Bus and Comport 3 to communicate with the host.
Version 1.2.0 Page 11 of 52 SMT398 User Manual
3. Make sure that the board is firmly seated, and then provide the 3.3V to the
board by screwing the SMT398 on the two main mounting holes with the bolts
and screws provided with the board.
4. Connect the SHB links if required by your application.
5. Replace the carrier board in the host system or power on for a stand-alone
carrier.
Version 1.2.0 Page 12 of 52 SMT398 User Manual
SMT398 + DSP TIM
You can fit the SMT398 coupled with a DSP module on any of Sundance carrier
boards: Stand alones or plugged in a Host.
The DSP module can then be used to provide the SMT398 FPGA configuration
bitstream and to communicate with the host.
Please, follow these steps to install the SMT398 module and the DSP TIM on a
carrier:
1. Remove the carrier board from the host system or turn the power off for a standalone carrier.
2. Place the SMT398 module onto one of the TIM sites on the carrier board.
• Preferably, fit the DSP TIM on the first TIM site. This TIM site
communicates with the host. (See your carrier board User Manual.).
This allows the processor board to handle the interactions with the Host
by software instead of having to implement a communication interface
in the SMT398 FPGA. (Global Bus interface or Comport interface on
Comport 3).
• Fit the Comport communication links between the DSP TIM and the
SMT398 respecting the rules on polarity at reset. (See your carrier
board User Manual.)
• To configure the SMT398 FPGA using the DSP TIM, then you need a
link between the 2 modules: Comport 3 of the SMT398
MUST be
connected to one of the transmit Comport at Reset (Comport 0,1 or 2)
available on the DSP TIM.
3. Make sure that the board is firmly seated, and then provide the 3.3V to the board
by screwing the SMT398 on the two main mounting holes with the bolts and
screws provided with the board.
4. Connect the SHB links if required by your application.
5. Replace the carrier board in the host system or power on for a stand-alone
carrier.
Version 1.2.0 Page 13 of 52 SMT398 User Manual
FPGA Configuration
The FPGA can be configured 2 different ways:
• Using Comport 3 to provide the bitstream. (See The service CPLD)
• Using the on-board JTAG header and Xilinx JTAG programming tools. (See
FPGA in system programming)
At power up the FPGA is not configured.
LED L5 (See Figure 19:SMT398 Components placement-Top view, bottom right
hand corner of the picture) will be lit upon FPGA configuration.
Electrical Interface
The service CPLD
The CPLD allows for FPGA configuration in slave SelectMap mode.
At power up or after a Reset of the SMT398, the CPLD is configured and
implements a Comport link receiver on Comport 3.
The CPLD is connected to Comport number 3 of the SMT398 TIM connector.
Consequently, the Comport on the other end of the link must be configured as
transmitter at power-up or after reset, i.e. Comport channels 0, 1, or 2.
The typical SMT398 user does not need an in depth understanding of the
configuration sequence and of the Virtex II. However, for the purpose of debugging
and designing for the SMT398 an overview of the necessary configuration protocol
and bitstream formatting is recommended.
Therefore, this section describes the CPLD functions, the Virtex II bitstream format
and the necessary bitstream re-formatting when downloading the bitstream to the
FPGA via CPLD + Comport 3.
Figure 2: FPGA configuration in SelectMap mode using CPLD provides waveforms to
illustrate the descriptions below.
Version 1.2.0 Page 14 of 52 SMT398 User Manual
Figure 2: FPGA configuration in SelectMap mode using CPLD
CPLD Functions
• Decode Commands coming on Comport 3.
• To Implement a Comport Receiver on Comport 3 after Reset or at Power up.
• Configure FPGA.
• Reset FPGA.
Version 1.2.0 Page 15 of 52 SMT398 User Manual
Decode Commands
At power up, after a TIM global Reset, or once the FPGA configuration process is
over, the CPLD reads any word coming on its Comport.
If a received word cannot be recognized as a command, the word is read completely
but ignored. The CPLD recognizes the following two commands:
• STARTKEY (0xBCBCBCBC)
• ENDKEY (0xBCBCBC00)
Comport Receiver
At power up or after a TIM global Reset, the CPLD takes control of Comport 3.
Once the ENDKEY command is received, the CPLD releases Comport 3.
The Comport communication is performed in 32-bit words, where each word consists
of four consecutive bytes. The Comport protocol transmits words starting with the
least-significant byte (LSByte), i.e. byte0, as shown in Figure 3: Comport word Byte
order, and 1 byte at a time.
Byte3 Byte2 Byte1 Byte0
31 24 23 16 15 8 7 0
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21D20D19D18D17D16D15D14D13D12D11 D10D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 3: Comport word Byte order
Configure FPGA
The signals INITn and DONE are CPLD inputs, the other one are CPLD outputs that
the CPLD drives to configure the FPGA.
On reception of the STARTKEY command the CPLD clears the FPGA configuration
memory by asserting the PROGRAMn pin low. On INITn going low, the CPLD brings
PROGRAMn high and waits for INITn to come back high before starting the FPGA
configuration.
Afterwards, the CPLD asserts CSn and WRITEn low for the rest of the configuration
process.
The CPLD pulses high CCLK to loads in the FPGA any new byte present on the
Comport by.
Version 1.2.0 Page 16 of 52 SMT398 User Manual
The CPLD does not implement any operation on the bitstream and passes it straight
through to the FPGA once the STARTKEY has been decoded and until the ENDKEY
is decoded.
Once the FPGA DONE pin has gone high, LED L5 (See Figure 19:SMT398
Components placement-Top view, bottom right hand corner of the picture) becomes
on, indicating that the FPGA configured.
The CPLD disables the SelectMap interface and waits for the ENDKEY command on
Comport3.
Once the ENDKEY command is received, the CPLD releases Comport 3.
Reset Control
TIM Reset or TIM Config
INIT
FPGA Configured and
STARTKEY Received
ENDKEY Received
CONFIG
IDLE
FPGA Configured
and ENDKEY Received
Figure 4: CPLD state machine
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