Sundance SMT395Q User Manual
SMT395Q
User Manual
User Manual (QCF42); Version 3.0, 5/2/01; © Sundance Multiprocessor Technology Ltd. 2001
Version 1.0.7 Page 2 of 31 SMT395Q User Manual
Revision History
Date Comments Engineer Version
12/04/05 First rev, based on 395 GP 1.0.0
20/05/05 Added: SDRAM memory map for DSPs
MS 1.0.1
Corrected: FPGA memory map
14/05/05 Corrected: Block diagram MS 1.0.2
08/11/05 Corrected: Comport description MS 1.0.3
16/01/06 DDR links added GP 1.0.4
03/03/06 ComPorts architecture added SM 1.0.5
11/04/06 External power connector description added SM 1.0.6
20/11/06 Changed DSPs’ core clock to fixed osc. GP 1.0.7
Version 1.0.7 Page 3 of 31 SMT395Q User Manual
Table of Contents
Revision History ....................................................................................................... 2
Table of Contents ..................................................................................................... 3
Contacting Sundance............................................................................................... 5
Notational Conventions ........................................................................................... 5
C60 ......................................................................................................................... 5
Register Descriptions.............................................................................................. 5
Outline Description .................................................................................................. 6
Block Diagram .......................................................................................................... 7
Architecture Description.......................................................................................... 8
TMS320C6416T ......................................................................................................... 8
Boot Mode............................................................................................................... 9
Flash Boot.......................................................................................................... 9
EMIF Control Registers......................................................................................... 10
SDRAM .................................................................................................................... 11
FLASH ..................................................................................................................... 11
FLASH Paging ................................................................................................. 11
Virtex-II Pro FPGA .................................................................................................. 12
External Clock......................................................................................................... 12
Version control ....................................................................................................... 12
Reprogramming the firmware and boot code ...................................................... 12
FPGA resources ..................................................................................................... 13
Interrupts............................................................................................................... 13
DDR SDRAM ........................................................................................................ 13
SDB ...................................................................................................................... 13
SDB Clock selection .......................................................................................... 13
RSL....................................................................................................................... 13
Global bus............................................................................................................. 13
ComPorts .............................................................................................................. 14
CONFIG & NMI ..................................................................................................... 15
Timer..................................................................................................................... 15
Version 1.0.7 Page 4 of 31 SMT395Q User Manual
IIOF interrupt......................................................................................................... 15
LED....................................................................................................................... 15
TTL ....................................................................................................................... 15
System Control ....................................................................................................... 16
Board Operating Parameters ................................................................................ 19
Code Composer Studio.......................................................................................... 22
3L Diamond Issues................................................................................................. 22
Operating Conditions............................................................................................. 23
Safety.................................................................................................................... 23
EMC...................................................................................................................... 23
General Requirements.......................................................................................... 23
Power Consumption.............................................................................................. 23
PCB description...................................................................................................... 24
Component Side ................................................................................................... 24
Solder Side ........................................................................................................... 25
Power Connector.................................................................................................... 26
Jumpers/Links ........................................................................................................ 26
JP3 – Prog Sel. ..................................................................................................... 26
JP1 – FPGA JTAG................................................................................................ 26
JP2- TTL I/O ......................................................................................................... 27
SHB pin-out........................................................................................................... 27
RSL pin-out ........................................................................................................... 27
Virtex Memory Map................................................................................................. 28
FPGA Pinout ........................................................................................................... 29
Bibliography............................................................................................................ 30
INDEX ...................................................................................................................... 31
Version 1.0.7 Page 5 of 31 SMT395Q User Manual
Contacting Sundance
You can contact Sundance for additional information by logging onto the technical support
system.
Notational Conventions
C60
The terms C60, C64xx and TMS320C64xx will be used interchangeably throughout this
document.
Register Descriptions
The format of registers is described using diagrams of the following form:
31–24 23–16 15–8 7–0
LEVEL
R,00000000 RW,10000000 R,00000000 R,10000000
The digits at the top of the diagram indicate bit positions within the register and the central
section names bits or bit fields. The bottom row describes what may be done to the field and
its value after reset. Shaded fields are reserved and should only ever be written with zeroes.
R Readable by the CPU
W
RW Readable and writeable by the CPU
Binary digits indicate the value of the field after reset.
Writeable by the CPU
Version 1.0.7 Page 6 of 31 SMT395Q User Manual
Outline Description
The SMT395Q is Sundance’s 4th generation of Texas Instruments ‘C6x DSP TIM (Texas
Instruments Module). This module uses 4 TMS320C6416T DSPs which have clock speeds
of up to 1GHz.
The module also includes a
to provide ‘C4x style ComPorts, a TIM compatible enhanced Global bus, two
Xilinx VirtexII-Pro (XC2VP70FF1704) FPGA which is configured
Sundance
High-Speed Busses (SHBs), 14 Sundance RSL, and other control functions.
The SMT395Q is, from the user’s perspective, a multi-DSP version of the SMT395 Module,
and an upgrade to the SMT361Q.
The SMT395Q is supported by the TI
Code Composer Studio and 3L Diamond RTOS to
enable full MultiDSP systems with minimum efforts by the programmers.
The SMT395Q is a C64xx-based size 2 TIM offering the following features:
Four TMS320C6416T processors running at 1GHz
Four external 20MB/s ComPorts
320MB of DSP SDRAM (120MHz)
8MB Flash ROM for Bootloader and FPGA programming
Global expansion connector
High bandwidth data I/O via 2 Sundance High-speed Buses (SHB).
256MB DDR memory for FPGA
Fourteen 2.5Gb/sec Rocket Serial Links (RSL) for Inter-Module communications
Power and temperature monitoring
Version 1.0.7 Page 7 of 31 SMT395Q User Manual
Block Diagram
8 LEDs &
4 I/O pins
JTAG Header
Sundance High-
Speed Bus
60-way x2
DRAM
64Mbytes
DRAM
64Mbytes
DRAM
64Mbytes
DRAM
128Mbytes
120 I/O Pins; 16-bit D ata
64 bit
64 bit
64 bit
64 bit
FPGA
(XC2VP70)
VirtexII-Pro, FF1704
996 I/O Pins
1.5V
Serial
port
D
C
B
A
Oscillators
voltage
convertors
1.5V & 1.2V
Power
monitoring
Flash (CE1)
64Mbit
Sundance RSL
256Mbytes
DDR memory
x14
'C64xx
DSP
HPI
EMIFB
'C64xx
DSP
HPI
EMIFB
'C64xx
DSP
HPI
EMIFB
'C64xx
DSP
EMIFA EMIFA EMIFA EMIFA
HPI
16 bit
JTAG
chain
J3 Global Expansion
Connector
Control
24 I/O pins
74 I/O pins
Global Bus
24 I/O pins
2x Comm-Ports
J2 Bottom Primary TIM
Connector
Comm-Port 1 & 4
2x Comm-Ports
J1 Top Primary TIM
Connector
Comm-Port 0 & 3
Timer &
Version 1.0.7 Page 8 of 31 SMT395Q User Manual
Architecture Description
The SMT395Q TIM consists of 4 Texas Instruments TMS320C6416Ts running at up to
1GHz. Modules are populated with 320MBytes of SDRAM for the DSPs, and 256Mbytes of
DDR memory for the FPGA.
A Field Programmable Gate Array (FPGA) is used to manage global bus accesses and
implement four ComPorts and two Sundance High Speed Buses. This is a Xilinx Virtex-II Pro
device.
TMS320C6416T
These processors will run with zero wait states from internal SRAM.
An on-board crystal oscillator provides the clock used for the C60. Alternatively an on-board
clock synthesiser provides the clock for the C60 (build option). The synthesiser frequency
can be altered under DSP control. These clocks are multiplied by 20 by the DSP.
The following table shows the main DSP characteristics.
Features C6416T
DMA / McBSP / Timer 64/3/3
On-chip memory 1056KB
Speed 1GHz
Others UTOPIA
Viterbi and Turbo decoders
The SMT395Q implementation using this DSP provides interfaces using the EMIFs (External
Memory Interfaces A & B), timers and JTAG.
The JTAG interface is provided to enable application debugging via a suitable JTAG
controller and software. Typically, this will be an
SMT310 and TI Code Composer Studio.
This is an invaluable interface which enables the application programmer to quickly debug a
‘chain’ of processors in single or multi-processor situations.
The EMIF_A is used to connect to a 120MHz, 64MB bank of SDRAM (128MB for DSP_A,
and the VirtexII-Pro).
The flash (DSP_A only) is connected via EMIF_B as a 16-bit device. The EMIF_A supplies 4
‘chip selects’ which are used for these selections.
Version 1.0.7 Page 9 of 31 SMT395Q User Manual
Boot Mode
The SMT395Q is configured to boot from flash after a reset.
Flash Boot
1. The processor copies a bootstrap program from the first part of the flash memory into
internal program RAM starting at address 0.
2. Execution starts at address 0.
The standard bootstrap supplied with the SMT395Q then performs the following
operations:
1. All relevant C60 internal registers are set to default values;
2. The FPGA is configured from data held in flash memory and sets up the ComPorts,
the global bus and the Sundance High-speed Buses. This step must have been
completed before data can be sent to the ComPorts from external sources such as
the host or other TIMs;
3. A C4x-style boot loader is executed. This will continually examine the ComPorts until
data appears on one of them. The bootstrap will then load a program in boot format
from that port; the loader will not read data arriving on other ports. See “Application
Development” for details of the boot loader format;
4. Finally, control is passed to the loaded program.
The delay between the release of the board reset and the FPGA configuration is around
2s for a SMT395Q.
A typical time to wait after releasing the board reset should be in excess of this delay, but
no damage will result if any of I/Os are used before they are fully configured. In fact, the
ComPorts will just produce a not ready signal when data is attempted to be transferred
during this time, and then continue normally after the FPGA is configured.
Version 1.0.7 Page 10 of 31 SMT395Q User Manual
EMIF Control Registers
The C6416 has two external memory interfaces (EMIFs). One of these is 64 bits wide,
the other 16 bits.
The C60 contains several registers that control the external memory interfaces (EMIFs).
A full description of these registers can be found in the
SMT6400 help file.
The standard bootstrap will initialise these registers to use the following resources:
Memory space
(EMIF_A)
Memory space
(EMIF_B)
Resource Address range
Internal program memory (1M) 0x00000000 - 0x000FFFFF
CE0 SDRAM (64Mbytes) 0x80000000 - 0x83FFFFFF
CE1 SDRAM (64Mbytes) DSP_A
0x90000000 - 0x93FFFFFF
only
CE2 Virtex-II 0xB0000000 - 0xBFFFFFFF
Resource Address range
CE0 HPI of adjacent DSP 0x60000000 - 0x600000FF
CE1 2MB section of flash (DSP_A
0x64000000 – 0x640FFFFF
only)
CE2 FPGA PROG controls (DSP_A
0x68000000
only). Write to this address to
assert PROG and clear the
FPGA configuration.
CE3 FPGA CCLK control (DSP_A
only)
The boot code sets-up the EMIF as follows:
GCTLB = 0x0001277C;
CECTL0A = 0x000000D0;
CECTL1A = 0x000000D0;
CECTL2A = 0xFFFFFF23
CECTL3A = 0x00000030;
SDCTRLA = 0x53227000;
CECTL0B = 0x10d20415;
0x6C000000
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