Sundance SMT395 User Manual
SMT395
User Manual
User Manual (QCF42); Version 3.0, 5/2/01; © Sundance Multiprocessor Technology Ltd. 2001
Version 1.1.7 Page 2 of 26 SMT395 User Manual
Revision History
Date Comments Engineer Version
19/04/04 First rev, based on 365 J.V. 1.0.0
26/04/04 Update typos J.V. 1.1.0
26/05/04 Connector JP1 and JP3 inverted J.V. 1.1.1
13/08/04 Reference to general firmware updated
J.V. 1.1.2
RSL section added
28/09/04 Corrected: CCS 2.0 to CCS 2.20 in section
S.M. 1.1.3
Code Composer (p.16/25)
05/04/05 Updated EMIF Control Registers section JP.A 1.1.4
12/09/05 Added: picture of top view for JP1, JP2, JP3 S.M. 1.1.5
22/09/05 JP1 and JP3 description updated J.V. 1.1.6
24/11/05 Corrected JPx description S.M. 1.1.7
Version 1.1.7 Page 3 of 26 SMT395 User Manual
Table of Contents
Revision History....................................................................................................... 2
Contacting Sundance............................................................................................... 4
Notational Conventions ........................................................................................... 5
C60 ......................................................................................................................... 5
Register Descriptions.............................................................................................. 5
Outline Description .................................................................................................. 6
Block Diagram .......................................................................................................... 7
Architecture Description.......................................................................................... 7
TMS320C6416T......................................................................................................... 8
Boot Mode............................................................................................................... 9
Flash Boot.......................................................................................................... 9
EMIF Control Registers......................................................................................... 10
SDRAM .................................................................................................................... 11
FLASH ..................................................................................................................... 11
FLASH Paging ................................................................................................. 11
Virtex-II Pro FPGA .................................................................................................. 11
External Clock......................................................................................................... 12
Version control....................................................................................................... 12
Reprogramming the firmware and boot code ...................................................... 12
FPGA resources ..................................................................................................... 13
Interrupts............................................................................................................... 13
Communication ports............................................................................................ 13
SDB ...................................................................................................................... 13
SDB Clock selection.......................................................................................... 13
RSL....................................................................................................................... 13
Global bus............................................................................................................. 13
CONFIG & NMI..................................................................................................... 13
Timer..................................................................................................................... 14
IIOF interrupt......................................................................................................... 14
LED....................................................................................................................... 15
TTL ....................................................................................................................... 15
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Code Composer...................................................................................................... 16
Operating Conditions............................................................................................. 16
Safety.................................................................................................................... 16
EMC...................................................................................................................... 16
General Requirements.......................................................................................... 16
Power Consumption.............................................................................................. 17
PCB description...................................................................................................... 17
Component Side................................................................................................... 17
Solder Side ........................................................................................................... 18
Connector Pinouts ................................................................................................. 19
FPGA JTAG (JP1) ................................................................................................ 19
FPGA PROG Pin Control (JP2) ............................................................................ 19
TTL (JP3).............................................................................................................. 20
SHB pin-out........................................................................................................... 21
RSL pin-out........................................................................................................... 22
Virtex Memory Map................................................................................................. 23
FPGA Pin-Out.......................................................................................................... 25
Bibliography............................................................................................................ 25
Index........................................................................................................................ 26
Contacting Sundance
You can contact Sundance for additional information by login onto the support
system
support.sundance.com
Version 1.1.7 Page 5 of 26 SMT395 User Manual
Notational Conventions
C60
The terms C60, C64xx and TMS320C64xx will be used interchangeably throughout
this document.
Register Descriptions
The format of registers is described using diagrams of the following form:
31–24 23–16 15–8 7–0
LEVEL
R,00000000 RW,10000000 R,00000000 R,10000000
The digits at the top of the diagram indicate bit positions within the register and the
central section names bits or bit fields. The bottom row describes what may be done
to the field and its value after reset. Shaded fields are reserved and should only ever
be written with zeroes.
R Readable by the CPU
W Writeable by the CPU
RW Readable and writeable by the CPU
Binary digits indicate the value of the field after reset.
Version 1.1.7 Page 6 of 26 SMT395 User Manual
Outline Description
The SMT395 is Sundance’s 4th generation of Texas Instruments ‘C6000 DSP TIM
(Texas Instruments Module). This module uses the
clock speed of up to 1GHz, and a 64 bit external data bus.
TMS320C6416 DSP which has a
The module also includes a
‘C4x style Comm ports or alternatively the
compatible enhanced global bus,
Xilinx VirtexII-Pro FPGA which is configured to provide
Sundance Digital Link (SDL), a TIM
Sundance High-speed Bus (SHB), Sundance RSL
(RocketIO) interfaces and other control functions.
All external interfaces (global bus, ComPorts etc) are fully compatible with 5V
systems including the C40 based modules and carrier boards.
The SMT395 is, from the user’s perspective, a faster version of the
based Module and an improved version of the
The SMT395 is supported by the T.I.
Code Composer Studio and 3L Diamond RTOS
SMT365.
SMT335 ‘C6201
to enable full MultiDSP systems with minimum efforts by the programmers.
The SMT395 is a C64xx-based size 1 TIM offering the following features:
TMS320C6416T processor running at 1GHz
Six 20MB/s communication ports (ComPorts)
256MB of SDRAM (133MHz)
8MByte Flash ROM for boot code and FPGA programming
Global expansion connector
High bandwidth data I/O via 2 Sundance High-speed Buses (SHB)
Eight 2.5Gbit/sec Rocket Serial Links (RSL) for intermodule communications
5V tolerant pins
Version 1.1.7 Page 7 of 26 SMT395 User Manual
Block Diagram
J1 Top Primary TIM
JTAG Header
2 x Sundance High-
speed Bus (SHB)
60-way Samtec QSH
2 x Sundance RSL
connectors (Xilinx
Rocket-IO)
28-way Samtec QxE
120 I/O Pins; 32-bit Data
8 differential serial links
Connector
Comm-Port 0 & 3
2x Comm-Ports/SDL
5V<>3V3 level translator
FPGA Controller
Virtex-II Pro, FF896
XC2VP20,30
1.5V Core
3.3V I/O
5V<>3V3 level translator
Clocks, Timer, Interrupts, PXI.
4 LEDs &
4 I/O pins
104 I/O pins
133MHz EMIFA
DC-DC Converters
1.5V & 1.4V
McBSP/Utopia/GPIO
(all non-TIM I/O pins)
DSP
1GHz 'C6416
525 pins - 1.4V
256Mbytes SDRAM
(4 x 32M x16 133MHz)
EMIFA
Oscillators
4 LEDs
J3 Global Expansion
Connector
Global Bus
4x Comm-Port/SDL
J2 Bottom Primary TIM
Connector
Comm-Port 1, 2, 4 & 5
8Mbyte Flash (EMIFB CE1)
Architecture Description
The SMT395 TIM consists of a Texas Instruments TMS320C6416T running at up to
1GHz. Modules are populated with 256MBytes of SDRAM.
A Field Programmable Gate Array (FPGA) is used to manage global bus accesses
and implement six communication ports and two Sundance High Speed Buses. This
is a Xilinx VirtexII-Pro device.
Version 1.1.7 Page 8 of 26 SMT395 User Manual
TMS320C6416T
The processor will run with zero wait states from internal SRAM.
An on-board crystal oscillator provides the clock used for the C60, which then
multiplies this by 12 internally.
The following table shows the main DSP characteristics.
Feature C6416T
DMA / McBSP / Timer 64/3/3
On-chip memory 1056k bytes
Speed 1GHz
Others UTOPIA
Viterbi and
Turbo
decoders
The SMT395 implementation using this DSP provides interfaces using the EMIFs
(External Memory Interfaces A & B), timers and JTAG.
The JTAG interface is provided to enable application debugging via a suitable JTAG
controller and software. Typically, this will be an
SMT310 and TI Code Composer
Studio. This is an invaluable interface which enables the application programmer to
quickly debug a ‘chain’ of processors in single or multi-processor situations.
The EMIFA is used to connect to a 133MHz, 256Mbyte bank of SDRAM (4 devices of
64M bytes, Samsung K4S511632M-TC75), and the VirtexII-Pro.
The flash is connected via EMIFB as a 16 bit device. The EMIFA supplies 4 ‘chip
selects’ which are used for these selections.
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