SMT395
User Manual
User Manual (QCF42); Version 3.0, 5/2/01; © Sundance Multiprocessor Technology Ltd. 2001
Version 1.1.7 Page 2 of 26 SMT395 User Manual
Revision History
Date Comments Engineer Version
19/04/04 First rev, based on 365 J.V. 1.0.0
26/04/04 Update typos J.V. 1.1.0
26/05/04 Connector JP1 and JP3 inverted J.V. 1.1.1
13/08/04 Reference to general firmware updated
J.V. 1.1.2
RSL section added
28/09/04 Corrected: CCS 2.0 to CCS 2.20 in section
S.M. 1.1.3
Code Composer (p.16/25)
05/04/05 Updated EMIF Control Registers section JP.A 1.1.4
12/09/05 Added: picture of top view for JP1, JP2, JP3 S.M. 1.1.5
22/09/05 JP1 and JP3 description updated J.V. 1.1.6
24/11/05 Corrected JPx description S.M. 1.1.7
Version 1.1.7 Page 3 of 26 SMT395 User Manual
Table of Contents
Revision History....................................................................................................... 2
Contacting Sundance............................................................................................... 4
Notational Conventions ........................................................................................... 5
C60 ......................................................................................................................... 5
Register Descriptions.............................................................................................. 5
Outline Description .................................................................................................. 6
Block Diagram .......................................................................................................... 7
Architecture Description.......................................................................................... 7
TMS320C6416T......................................................................................................... 8
Boot Mode............................................................................................................... 9
Flash Boot.......................................................................................................... 9
EMIF Control Registers......................................................................................... 10
SDRAM .................................................................................................................... 11
FLASH ..................................................................................................................... 11
FLASH Paging ................................................................................................. 11
Virtex-II Pro FPGA .................................................................................................. 11
External Clock......................................................................................................... 12
Version control....................................................................................................... 12
Reprogramming the firmware and boot code ...................................................... 12
FPGA resources ..................................................................................................... 13
Interrupts............................................................................................................... 13
Communication ports............................................................................................ 13
SDB ...................................................................................................................... 13
SDB Clock selection.......................................................................................... 13
RSL....................................................................................................................... 13
Global bus............................................................................................................. 13
CONFIG & NMI..................................................................................................... 13
Timer..................................................................................................................... 14
IIOF interrupt......................................................................................................... 14
LED....................................................................................................................... 15
TTL ....................................................................................................................... 15
Version 1.1.7 Page 4 of 26 SMT395 User Manual
Code Composer...................................................................................................... 16
Operating Conditions............................................................................................. 16
Safety.................................................................................................................... 16
EMC...................................................................................................................... 16
General Requirements.......................................................................................... 16
Power Consumption.............................................................................................. 17
PCB description...................................................................................................... 17
Component Side................................................................................................... 17
Solder Side ........................................................................................................... 18
Connector Pinouts ................................................................................................. 19
FPGA JTAG (JP1) ................................................................................................ 19
FPGA PROG Pin Control (JP2) ............................................................................ 19
TTL (JP3).............................................................................................................. 20
SHB pin-out........................................................................................................... 21
RSL pin-out........................................................................................................... 22
Virtex Memory Map................................................................................................. 23
FPGA Pin-Out.......................................................................................................... 25
Bibliography............................................................................................................ 25
Index........................................................................................................................ 26
Contacting Sundance
You can contact Sundance for additional information by login onto the support
system
support.sundance.com
Version 1.1.7 Page 5 of 26 SMT395 User Manual
Notational Conventions
C60
The terms C60, C64xx and TMS320C64xx will be used interchangeably throughout
this document.
Register Descriptions
The format of registers is described using diagrams of the following form:
31–24 23–16 15–8 7–0
LEVEL
R,00000000 RW,10000000 R,00000000 R,10000000
The digits at the top of the diagram indicate bit positions within the register and the
central section names bits or bit fields. The bottom row describes what may be done
to the field and its value after reset. Shaded fields are reserved and should only ever
be written with zeroes.
R Readable by the CPU
W Writeable by the CPU
RW Readable and writeable by the CPU
Binary digits indicate the value of the field after reset.
Version 1.1.7 Page 6 of 26 SMT395 User Manual
Outline Description
The SMT395 is Sundance’s 4th generation of Texas Instruments ‘C6000 DSP TIM
(Texas Instruments Module). This module uses the
clock speed of up to 1GHz, and a 64 bit external data bus.
TMS320C6416 DSP which has a
The module also includes a
‘C4x style Comm ports or alternatively the
compatible enhanced global bus,
Xilinx VirtexII-Pro FPGA which is configured to provide
Sundance Digital Link (SDL), a TIM
Sundance High-speed Bus (SHB), Sundance RSL
(RocketIO) interfaces and other control functions.
All external interfaces (global bus, ComPorts etc) are fully compatible with 5V
systems including the C40 based modules and carrier boards.
The SMT395 is, from the user’s perspective, a faster version of the
based Module and an improved version of the
The SMT395 is supported by the T.I.
Code Composer Studio and 3L Diamond RTOS
SMT365.
SMT335 ‘C6201
to enable full MultiDSP systems with minimum efforts by the programmers.
The SMT395 is a C64xx-based size 1 TIM offering the following features:
TMS320C6416T processor running at 1GHz
Six 20MB/s communication ports (ComPorts)
256MB of SDRAM (133MHz)
8MByte Flash ROM for boot code and FPGA programming
Global expansion connector
High bandwidth data I/O via 2 Sundance High-speed Buses (SHB)
Eight 2.5Gbit/sec Rocket Serial Links (RSL) for intermodule communications
5V tolerant pins
Version 1.1.7 Page 7 of 26 SMT395 User Manual
Block Diagram
J1 Top Primary TIM
JTAG Header
2 x Sundance High-
speed Bus (SHB)
60-way Samtec QSH
2 x Sundance RSL
connectors (Xilinx
Rocket-IO)
28-way Samtec QxE
120 I/O Pins; 32-bit Data
8 differential serial links
Connector
Comm-Port 0 & 3
2x Comm-Ports/SDL
5V<>3V3 level translator
FPGA Controller
Virtex-II Pro, FF896
XC2VP20,30
1.5V Core
3.3V I/O
5V<>3V3 level translator
Clocks, Timer, Interrupts, PXI.
4 LEDs &
4 I/O pins
104 I/O pins
133MHz EMIFA
DC-DC Converters
1.5V & 1.4V
McBSP/Utopia/GPIO
(all non-TIM I/O pins)
DSP
1GHz 'C6416
525 pins - 1.4V
256Mbytes SDRAM
(4 x 32M x16 133MHz)
EMIFA
Oscillators
4 LEDs
J3 Global Expansion
Connector
Global Bus
4x Comm-Port/SDL
J2 Bottom Primary TIM
Connector
Comm-Port 1, 2, 4 & 5
8Mbyte Flash (EMIFB CE1)
Architecture Description
The SMT395 TIM consists of a Texas Instruments TMS320C6416T running at up to
1GHz. Modules are populated with 256MBytes of SDRAM.
A Field Programmable Gate Array (FPGA) is used to manage global bus accesses
and implement six communication ports and two Sundance High Speed Buses. This
is a Xilinx VirtexII-Pro device.
Version 1.1.7 Page 8 of 26 SMT395 User Manual
TMS320C6416T
The processor will run with zero wait states from internal SRAM.
An on-board crystal oscillator provides the clock used for the C60, which then
multiplies this by 12 internally.
The following table shows the main DSP characteristics.
Feature C6416T
DMA / McBSP / Timer 64/3/3
On-chip memory 1056k bytes
Speed 1GHz
Others UTOPIA
Viterbi and
Turbo
decoders
The SMT395 implementation using this DSP provides interfaces using the EMIFs
(External Memory Interfaces A & B), timers and JTAG.
The JTAG interface is provided to enable application debugging via a suitable JTAG
controller and software. Typically, this will be an
SMT310 and TI Code Composer
Studio. This is an invaluable interface which enables the application programmer to
quickly debug a ‘chain’ of processors in single or multi-processor situations.
The EMIFA is used to connect to a 133MHz, 256Mbyte bank of SDRAM (4 devices of
64M bytes, Samsung K4S511632M-TC75), and the VirtexII-Pro.
The flash is connected via EMIFB as a 16 bit device. The EMIFA supplies 4 ‘chip
selects’ which are used for these selections.
Version 1.1.7 Page 9 of 26 SMT395 User Manual
Boot Mode
The SMT395 is configured to boot from flash after a reset
Flash Boot
1. The processor copies a bootstrap program from the first part of the flash
memory into internal program RAM starting at address 0.
2. Execution starts at address 0.
The standard bootstrap supplied with the SMT395 then performs the following
operations:
1. All relevant C60 internal registers are set to default values;
2. The FPGA is configured from data held in flash memory and sets up the
communication ports, the global bus and the Sundance High-speed Buses.
This step must have been completed before data can be sent to the ComPorts
from external sources such as the host or other TIMs;
3. A C4x-style boot loader is executed. This will continually examine the six
communication ports until data appears on one of them. The bootstrap will
then load a program in boot format from that port; the loader will not read data
arriving on other ports. See “Application Development” for details of the boot
loader format;
4. Finally, control is passed to the loaded program.
The delay between the release of the board reset and the FPGA configuration is
around 1s for a SMT395.
A typical time to wait after releasing the board reset should be in excess of this
delay, but no damage will result if any of the I/Os are used before they are fully
configured. In fact, the comm. Ports will just produce a not ready signal when data
is attempted to be transferred during this time, and then continue normally after
the FPGA is configured.
Version 1.1.7 Page 10 of 26 SMT395 User Manual
EMIF Control Registers
The C6416 has two external memory interfaces (EMIFs). One of these is 64 bits
wide, the other 16 bits.
The C60 contains several registers that control the external memory interfaces
(EMIFs). A full description of these registers can be found in the C60 Peripherals
Reference Guide[0].
The standard bootstrap will initialise these registers to use the following
resources:
Memory space
(EMIFA)
CE0 SDRAM (256M) 0x80000000 - 0x8FFFFFFF
CE1 Virtex 0x90000000 - 0x900FFFFF
Memory space
(EMIFB)
CE1 8Mbyte flash in 4 pages.
CE2 Any access asserts FPGA
CE3 A write programs data bit
Resource Address range
Internal program memory
(1M)
Resource Address range
Page selected with GPIO9
and GPIO10
PROG line
D0 serially in the FPGA and
make a CCLK edge.
0x00000000 - 0x000FFFFF
0x64000000 – 0x641FFFFF
0x68000000 – 0x641FFFFF
0x68000000 – 0x641FFFFF
The boot code sets-up the EMIF as follows:
GBCTLA = 0x0001277C ;
CECTL0A = 0x000000D0;
CECTL1A = 0x000000A0;
SDCTRLA = 0x6A227000;
CECTL1B = 0xFFFFFF13;
CECTL2B = 0xFFFFFF23;
CECTL3B = 0x105FFF23;
SDEXTA = 0x00017F3F
Version 1.1.7 Page 11 of 26 SMT395 User Manual
SDRAM
256Mbytes of SDRAM is available (4 devices of 64M bytes, Samsung K4S511632MTC75) The SDRAM operates at EMIF clock speed. It is typically 133MHz for the
SMT395.
FLASH
An 8Mbyte flash memory is provided with direct access by the DSP. This device
contains boot code for the DSP and the configuration data for the FPGA.
This is a 16-bit wide device.
The flash device can be re-programmed by the DSP at any time. There is a software
protection mechanism to stop most errant applications from destroying the device’s
contents.
Note that the flash memory is connected as a 16 bit device, but during a C6x boot
(internal function of the C6x) only the bottom 8 bits are used.
As the C60 only provides 20 address lines on its EMIFB, two GPIO lines (9 and 10)
are used to access this device. So the device should be seen as divided in 4x
2MBytes pages.
FLASH Paging
Selecting the visible flash memory page (4 pages of 2Mbytes) involves setting up the
GPIO registers bit 9 and 10. Make sure that the setup of the other GPIO is kept
untouched as they are used for external interrupt and leds.
Virtex-II Pro FPGA
This device, either a Xilinx XC2VP20 or 30, is responsible for the provision of the
SHBs, RSLs, 6 comm ports and the global bus. On power-up, this device is unconfigured (SRAM based FPGA technology). During the DSP boot process, the
FPGA is configured for normal operation.
The standard configuration for the primary FPGA uses approximately 3800 slices and
128 dual port rams. The remainder can be used for additional functionality.
Note that the ComPorts and global bus interfaces provided by the FPGA are 5V
tolerant and can thus be interfaced with older systems using the ‘C40 based modules
and TIM carriers.
All of the external interfaces provided by the FPGA are fully described in the
SMT6400 help file.
The Sundance High-speed BUS (SHB) specification can be found
here.
Version 1.1.7 Page 12 of 26 SMT395 User Manual
The SDL specification can be found here.
The RSL specification (Xilinx Rocket IO) can be found
here.
The FPGA configuration is done in two steps:
First asserting the prog line clears the FPGA configuration. This is simply done by an
access in EMIFB CE2.
Then after the FPGA configuration has cleared the FPGA configuration is
programmed serially by writing the data from the flash in EMIFB CE3.
At the end of the programming a register is polled to wait until the FPAG is
configured and proceed with the application loading process.
External Clock
An external clock input is provided to the FPGA. This signal is directly connected to
the secondary TIM connector user defined pin 12.
Version control
Version number for FPGA firmware and boot code is stored in the Flash ROM during
programming as zero-terminated ASCII strings. These are displayed when using the
SMT6001 utility.
Reprogramming the firmware and boot code
The reprogramming of the module is done using the SMT6001.
It contains the latest boot code and FPGA firmware for it and allows storing a user
application in it.
Version 1.1.7 Page 13 of 26 SMT395 User Manual
FPGA resources
Interrupts
SMT6400 help file
See
Communication ports
The SMT395 provides 6 ComPorts. They are ComPort 0, 1, 2, 3, 4 and 5.
See SMT6400 help file
SDB
The SMT395 provides two SHB which are 32-bit SDB.
They are numbered SDB0 for SHBA, SDB1 for SHBB.
See
SMT6400 help file
SDB Clock selection
The SDB clock selection is not implemented. The clock is running at the EMIF speed
i.e. 133MHz.
RSL
This interface is still under test. It needs to be standardized across the Sundance
module range.
The status so far:
-5 FPGA are limited to 2Gbit/s serial links (see Xilinx datasheet).
-6 FPGA theoretical limit is 3.125Gb/s. This hasn’t been verified on the hardware yet.
Tests have been performed with aurora protocol with on-board 100MHz clock. A
single lane solution gives around 170MB/s between DSPs. The first tests on the 4
lanes interface have been performed and we are evaluating the best architecture.
The board also includes a differential oscillator (EG-2121CA LV-PECL) for faster
speed rate.
The interface is not fixed and not provided yet.
Global bus
The SMT395 provides one global bus interface.
See
SMT6400 help file
CONFIG & NMI
See
SMT6400 help file
Version 1.1.7 Page 14 of 26 SMT395 User Manual
Timer
SMT6400 help file
See
IIOF interrupt
The firmware can generate pulses on the external interrupt lines of the TIM.
See SMT6400 help file
Version 1.1.7 Page 15 of 26 SMT395 User Manual
LED
The SMT395 has 7 LEDs.
The LED on the top right corner of the module (above P3 label) always displays the
state of the FPGA DONE pin. This LED is off when the FPGA is configured
(DONE=1) and on when it is not configured (DONE=0).
This LED should go on when the board is first powered up and go off when the FPGA
has been successfully programmed (this is the standard operation of the boot code
resident in the flash memory device). If the LED does not light at power-on, check
that you have the mounting pillars and screws fitted properly. If it stays on, the DSP
is not booting correctly, or is set to boot in a non-standard way.
Two of the LEDs (D7-D8) can be controlled with the LED register.
Writing 1 will illuminate the LED; writing 0 will turn it off.
Two of the LEDs (D9-D10) can be controlled by the FPGA but their use hasn’t been
allocated yet.
LED Register
LED 0x900D0000
31–4 3 2 1 0
TTL1 TTL0
RW,0 RW,0 RW,0 RW,0
LED
D8
LED
D7
The four remaining LEDs (D11-14) are connected to the C60’s GPIO pins 12-15.
TTL
The SMT395 has 4 TTL (TTL0, TTL1, TTL2 and TTL3) signals available on
connector JP3.
TTL0 and TTL1 have been mapped in the LED register and TTL2 and TTL3 are left
unconnected for future use.
Version 1.1.7 Page 16 of 26 SMT395 User Manual
Code Composer
This module is fully compatible with the Code Composer Studio (CCS) debug
environment (version 2.20 or later). This extends to both the software and JTAG
debugging hardware.
The name of the C64xx CCS device driver is tixds64xx_11.dvr, and should be
obtained from Texas Instruments. In case of difficulty please ask assistance via our
online support forum.
Operating Conditions
Safety
The module presents no hazard to the user.
EMC
The module is designed to operate within an enclosed host system that provides
adequate EMC shielding. Operation within the EU EMC guidelines is only guaranteed
when the module is installed within an appropriate host system.
The module is protected from damage by fast voltage transients introduced along
output cables from outside the host system.
Short-circuiting any output to ground does not cause the host PC system to lock up
or reboot.
General Requirements
The module must be fixed to a TIM40-compliant carrier board.
The SMT395 TIM is in a range of modules that must be supplied with a 3.3v power
source. In addition to the 5v supply specified in the TIM specification, these new
generation modules require an additional 3.3v supply to be presented on the two
diagonally-opposite TIM mounting holes. The lack of this 3.3v power supply should
not damage the module, although it will obviously be inoperable; prolonged operation
under these circumstances is not recommended.
The SMT395 is compatible with all Sundance TIM carrier boards. It is a 5v tolerant
module, and as such, it may be used in mixed systems with older TIM modules,
carrier boards and I/O modules.
Use of the TIM on SMT327 (cPCI) motherboards may require a firmware upgrade. If
the top right LED on the SMT395 remains illuminated once the TIM is plugged in and
powered up, the SMT327 needs the upgrade. The latest firmware is supplied with all
new boards shipped. Please contact Sundance directly if you have an older board
and need the upgrade.
Version 1.1.7 Page 17 of 26 SMT395 User Manual
The external ambient temperature must remain between 0°C and 40°C, and the
relative humidity must not exceed 95% (non-condensing).
Power Consumption
The power consumption of this TIM is dependent on the operating conditions in terms
of core activity and I/O activity. The maximum power consumption is 10W.
PCB description
Component Side
Version 1.1.7 Page 18 of 26 SMT395 User Manual
Solder Side
Version 1.1.7 Page 19 of 26 SMT395 User Manual
Connector Pinouts
FPGA JTAG (JP1)
The following shows the pin-outs for JP1 (FPGA) JTAG connector:
Signal Pin Pin Signal
V33 1 4 TDI
TMS 2 5 TDO
TCK 3 6 GND
Note: The Pin 1 is marked by a white mark on the silkscreen (see white spot on the
previous picture).
FPGA PROG Pin Control (JP2)
The FPGA PROG pin is used to clear the FPGA configuration.
It is to be used as a safety in case the FPGA has been programmed with a bad
bitstream that corrupts the dsp external bus and prevents which any further
programming. Changing the jumper allows the user to clear the FPGA configuration
and reprogram the FPGA.
1-2 PROG under control of DSP
2-3 or out PROG asserted
Version 1.1.7 Page 20 of 26 SMT395 User Manual
Note: The Pin 1 is marked by a white mark on the silkscreen (see white spot on the
previous picture).
TTL (JP3)
The following shows the pin-outs for JP3 TTL connector:
Signal Pin Pin Signal
V33 1 4 TTL2
TTL0 2 5 TTL3
TTL1 3 6 GND
Note: The Pin 1 is marked by a white mark on the silkscreen (see white spot on the
previous picture).
Version 1.1.7 Page 21 of 26 SMT395 User Manual
SHB pin-out
Pin Signal Signal Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
SHB_CLK SHB_D0
SHB_D1 SHB_D2
SHBL_D3 SHB_D4
SHB_D5 SHB_D6
SHB_D7 SHB_D8
SHB_D9 SHB_D10
SHB_D11 SHB_D12
SHB_D13 SH_D14
SHB_D15 SHB_U0
SHB_U1 -
- SHB_WEN
SHB_REQ SHB_ACK
- -
- -
- -
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
- -
- -
- -
SHB_CLK SHB_D16
SHB_D17 SHB_D18
SHB_D19 SHB_D20
SHB_D21 SHB_D22
SHB_D23 SHB_D24
SHB_D25 SHB_D26
SHB_D27 SHB_D28
SHB_D29 SHB_D30
SHB_D31 SHB_U0
SHB_U1 -
- SHB_WEN
SHB_REQ SHB_ACK
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
Not implemented
Version 1.1.7 Page 22 of 26 SMT395 User Manual
RSL pin-out
The RSL pinout (Xilinx Rocket IO) can be found in this
The board has 4 RSL pairs per connectors (8 Links).
specification.
Version 1.1.7 Page 23 of 26 SMT395 User Manual
Virtex Memory Map
See general firmware description.
The memory mapping is as follows:
#define CP0 (volatile unsigned int *)0x90000000
#define CP1 (volatile unsigned int *)0x90008000
#define CP2 (volatile unsigned int *)0x90010000
#define CP3 (volatile unsigned int *)0x90018000
#define CP4 (volatile unsigned int *)0x90020000
#define CP5 (volatile unsigned int *)0x90028000
#define CP0_STAT (volatile unsigned int *)0x90004000
#define CP1_STAT (volatile unsigned int *)0x9000C000
#define CP2_STAT (volatile unsigned int *)0x90014000
#define CP3_STAT (volatile unsigned int *)0x9001C000
#define CP4_STAT (volatile unsigned int *)0x90024000
#define CP5_STAT (volatile unsigned int *)0x9002C000
#define GB_STAT (volatile unsigned int *)0x90034000
#define SDB_STAT (volatile unsigned int *)0x90038000
#define STAT (volatile unsigned int *)0x9003C000
#define SDBA (volatile unsigned int *)0x90040000
#define SDBB (volatile unsigned int *)0x90050000
#define SDBC (volatile unsigned int *)0x90060000
#define SDBD (volatile unsigned int *)0x90070000
#define SDBA_STAT (volatile unsigned int *)0x90048000
#define SDBB_STAT (volatile unsigned int *)0x90058000
#define SDBA_INPUTFLAG (volatile unsigned int *)0x90044000
#define SDBB_INPUTFLAG (volatile unsigned int *)0x90054000
#define SDBA_OUTPUTFLAG (volatile unsigned int *)0x9004C000
#define SDBB_OUTPUTFLAG (volatile unsigned int *)0x9005C000
#define GLOBAL_BUS (volatile unsigned int *)0x900A0000
#define GLOBAL_BUS_CTRL (volatile unsigned int *)0x90080000
#define GLOBAL_BUS_START (volatile unsigned int *)0x90088000
#define GLOBAL_BUS_LENGTH (volatile unsigned int *)0x90090000
#define TCLK (volatile unsigned int *)0x900C0000
#define TIMCONFIG (volatile unsigned int *)0x900C8000
#define LED (volatile unsigned int *)0x900D0000
#define INTCTRL4 (volatile unsigned int *)0x900E0000
Version 1.1.7 Page 24 of 26 SMT395 User Manual
#define INTCTRL4_EXT (volatile unsigned int *)0x900E4000
#define INTCTRL5 (volatile unsigned int *)0x900E8000
#define INTCTRL5_EXT (volatile unsigned int *)0x900EC000
#define INTCTRL6 (volatile unsigned int *)0x900F0000
#define INTCTRL6_EXT (volatile unsigned int *)0x900F4000
#define INTCTRL7 (volatile unsigned int *)0x900F8000
#define INTCTRL7_EXT (volatile unsigned int *)0x900FC000
Version 1.1.7 Page 25 of 26 SMT395 User Manual
FPGA Pin-Out
See board schematics.
Bibliography
1. Peripherals Reference Guide (literature number SPRU190)
http://www.ti.com/
Describes common peripherals available on the TMS320C6x digital signal processors. This book
includes information on the internal data and program memories, the external memory interface
(EMIF), the host port, multichannel-buffered serial ports, direct memory access (DMA), clocking
and phase-locked loop (PLL), and the power-down modes.
2. TIM-40 MODULE SPECIFICATION Including TMS320C44 Addendum
ftp://ftp2.sundance.com/Pub/documentation/pdf-files/tim_spec_v1.01.pdf
3. SDB Technical Specification
ftp://ftp2.sundance.com/Pub/documentation/pdf-files/sdb_tech_spec.pdf
4. SHB Technical Specification
ftp://ftp2.sundance.com/Pub/documentation/pdf-files/SHB_Technical_Specification_v1_0.pdf
5. TMS320C4x User's Guide (literature number SPRU063)
http://www-s.ti.com/sc/psheets/spru063c/spru063c.pdf
Describes the C4x 32-bit floating-point processor, developed for digital signal processing as well
as parallel processing applications. Covered are its architecture, internal register structure,
instruction set, pipeline, specifications, and operation of its six DMA channels and six
communication ports. Software and hardware applications are included.
6. Xilinx Virtex-II Pro data sheet:
http://www.xilinx.com/
7. General firmware description:
ftp://ftp2.sundance.com/Pub/documentation/pdf-files/External_Interface_User_manual.pdf
Version 1.1.7 Page 26 of 26 SMT395 User Manual
Index
Architecture Description..................7
Bibliography....................................25
Block Diagram ..................................7
Board not working
LED illuminated.............................15
Boot Mode.........................................9
bootstrap program ...........................9
carrier boards .................................16
Code Composer..............................16
Contacting Sundance.......................4
email address....................................4
EMIF Control Registers..................10
field values after reset......................5
Flash................................................11
FPGA .................................................7
configuration ...................................9
LEDs ................................................15
FPGA DONE pin...........................15
memory space................................ 10
motherboards................................. 16
NMI.............................................13, 14
Notational Conventions .................. 5
Operating Conditions.................... 16
Power
3.3v.............................................. 16
power consumption...................... 17
register descriptions....................... 5
revision numbers
FPGA firmware............................. 12
SDB................................................. 13
clock speed.................................. 13
Timer............................................... 14
TMS320C6416T ................................ 8
Virtex
memory map................................ 23
LED register..................................15
Loading...