Sundance SMT391-VP User Manual

SMT391-VP

User Manual

Version 1.3 Page 2 of 41 SMT391-VP User Manual

Revision History

Date Comments Engineer Version

25/04/05 First release JPA 1.0
07/06/05 Added: power consumption SM 1.1
16/08/05 Updated: firmware

JPA 1.2
Updated: triggers
Updated: ddr sdram
Updated: software
Updated: registers
Updated: introduction
Updated: comport

22/11/05 Updated: firmware/SMT391 interface block

JPA 1.3
Updated: description of the registers
Updated: software
Added link to SMT391 daughter module.

Version 1.3 Page 3 of 41 SMT391-VP User Manual

Table of Contents

Revision History.......................................................................................................... 2

Table of Contents....................................................................................................... 3

Introduction................................................................................................................. 6

Overview................................................................................................................. 6

Module Features..................................................................................................... 6

Possible Applications.............................................................................................. 6

Related Documents ................................................................................................ 7

Hardware overview..................................................................................................... 8

Block diagram......................................................................................................... 8

ADC

AT84AD001B ................................................................................................. 9

Analogue features................................................................................................... 9

FPGA...................................................................................................................... 9

DDR SDRAM.......................................................................................................... 9

SLB....................................................................................................................... 10

SDB ...................................................................................................................... 10

RSL....................................................................................................................... 10

Comport................................................................................................................ 10

LED....................................................................................................................... 10

External triggers.................................................................................................... 10

Clocks generation................................................................................................. 11

Firmware................................................................................................................... 11

Block diagram....................................................................................................... 11

SMT391 interface block ........................................................................................ 11

ADC data interface............................................................................................ 12

ADC 3-wire interface ......................................................................................... 12

PLL - VCO (LMX2330U) interface..................................................................... 12

Clock synthesiser (SY89430) interface.............................................................. 12

External clocks.................................................................................................. 12

Triggers............................................................................................................. 12

Registers block ..................................................................................................... 14

SDB ...................................................................................................................... 14

Version 1.3 Page 4 of 41 SMT391-VP User Manual

RSL....................................................................................................................... 14

Comport................................................................................................................ 14

MPS430 block....................................................................................................... 14

Design Resource Usage....................................................................................... 14

Software ................................................................................................................... 16

Library SMT391 .................................................................................................... 16

SMT391_Config().............................................................................................. 16

SMT391_Adc_Init()............................................................................................ 17

Config_LMX2330U().......................................................................................... 17

Library LMX2330U................................................................................................ 17

LMX2330U_Parameters().................................................................................. 17

Library SY89430V................................................................................................. 18

SY89430V_Parameters() .................................................................................. 18

Description of the registers....................................................................................... 19

Accessing the registers......................................................................................... 19

Memory map......................................................................................................... 21

Register Descriptions............................................................................................ 23

Reset Register................................................................................................... 23

Firmware Version Register (Read Add 0x000).................................................. 24

Temperature Registers (Read Add 0x020, 0x021, 0x028, 0x029)..................... 24

Serial Number Registers (Read Add 0x022 - 0x025 and 0x02A - 0x02D)......... 25

ADC Clock Source Registers (Write Add 0x801)............................................... 26

Clock Synthesizer Setup Register (Write Add 0x800) ....................................... 26

PLL Setup Registers (Write Add 0x802 – 0x809).............................................. 27

ADC Setup Registers (Write Add 0x80B, 0x80C).............................................. 29

Trigger register (0x042)..................................................................................... 29

Installation ................................................................................................................ 30

How to connect your SMT391 to your SMT338-VP? ............................................ 30

Configuring the FPGA........................................................................................... 33

Appendix................................................................................................................... 33

PLL (LMX2330U) interface.................................................................................... 33

Clock synthesiser interface................................................................................... 35

ADC interface........................................................................................................ 37

Version 1.3 Page 5 of 41 SMT391-VP User Manual

Physical Properties................................................................................................... 40

Power Supply........................................................................................................ 40

Power consumption .............................................................................................. 41

Module Dimensions .............................................................................................. 41

Version 1.3 Page 6 of 41 SMT391-VP User Manual

Introduction

Overview

The SMT391-VP is a single width TIM module. It is capable of sampling two analog
inputs at 1 GSPS with a resolution of 8 bits. An Atmel dual channel ADC

(AT84AD001) performs the analogue to digital conversion.

Digital data is output to a

Xilinx Virtex-II Pro FPGA (XC2VP30-6 - FF896 package).

Data samples from the ADC are transferred onto the RocketIO Serial Links on the
module (

RSL) for real time applications.

It is also possible to capture a frame of data and transfer it over the Sundance High-
speed Bus (

SHB). This interface is compatible with a wide range of Sundance

processor and I/O modules.

Module Features

The main features of the SMT391-VP are listed underneath:

• Dual channel ADC (Ideal for I & Q channel applications)

• 1GHz sampling frequency

• 8 Bit data resolution

• 128 Mbytes DDR SDRAM for sample captures

• Custom trigger inputs via external connectors

• Two Standard Sundance Comports

• Two SHB interfaces for easy interconnection to Sundance products (interfaces

for data sample and non-real-time processing)

1

• RSL interface for data streaming applications

• On-board MSP430 microprocessor

Possible Applications

The SMT391-VP can be used for the following applications (this non-exhaustive list
should be taken as an example):

• Broadband cable modem head-end systems

• 3G Radio transceivers

• High-data-rate point-to-point radios

• Medical imaging systems

• Spectrum analyzers

1

The memory is available on the board but isn’t supported by the firmware

Version 1.3 Page 7 of 41 SMT391-VP User Manual

Related Documents

[1] Sundance High-speed Bus (SHB) specifications – Sundance.

ftp://ftp2.sundance.com/Pub/documentation/pdf­files/SHB_Technical_Specification_v1_0.pdf

[2] RocketIO Serial Links (RSL) specifications – Sundance.

ftp://ftp2.sundance.com/Pub/documentation/pdf­files/RSL_Technical_Specification_v1_0.pdf

[3] TIM specifications.

ftp://ftp2.sundance.com/Pub/documentation/pdf-files/tim_spec_v1.01.pdf

[4] Sundance LVDS Bus (SLB) specifications – Sundance.

http://www.sundance.com/docs/SLB%20-%20Technical%20Specifications.pdf

[5] Virtex-II Pro FPGA datasheet - Xilinx.

http://direct.xilinx.com/bvdocs/publications/ds083.pdf

[6] Dual 8-bit ADC datasheet - Atmel.

http://www.atmel.com/dyn/resources/prod_documents/doc2153.pdf

[7] Comport specification – Texas Instruments.

http://focus.ti.com/lit/ug/spru63c.pdf

[8]

SMT391 daughter module user manual.

Version 1.3 Page 8 of 41 SMT391-VP User Manual

Hardware overview

Block diagram

The following diagram represents the architecture of the SMT391-VP module.

4 RocketIO

Data through p ut)

SHB for Channel A

ChA Da ta , Clock

and Contr ol ( 60)

256MBit

DDR SDRAM

Da ta, Cloc k and

Control (93)

256MBit

DDR SDRAM

512MBit for

Chan ne l A

(1GByte/s effective

Links for Channe l A

DataTx (4d)

DataRx (4d)

Conn ectors

Top an d B ottom TIM

ComPorts and

Control (59)

XC2VP30

Virtex-II Pro

FF89 6 Package

4 RocketIO

Data through p ut)

(1GByte/s effective

Links for Channe l A

DataTx (4d)

DataRx (4d)

50 8 / 556 IO s

Data, Clock and

SHB for Channel B

ChB Da ta , Clock

and Contr ol ( 60)

256MBit

DDR SDRAM

Control (93)

256MBit

DDR SDRAM

51 2MBi t f or

Channel B

ChA Dat a, Clock

Cont rol (6 )

Cont rol (4 )

Cloc k (1d)

Clock (2d)

Clock

Lo w Jit t er

Local Oscillator

LVPECL

Distribution

Generation and

Input

Clock

Connector

a nd Co nt ro l (1 8d )

ChB Dat a, Clock

a nd Co nt ro l (1 8d )

Dual 8Bit

1GSP S A DC

AT84 AD00 1-A

Vin A

(1d)

Vin B

(1d)

Sign al

Chan nel A

Input

Chan ne l A

Sign al

Chan nel B

Cond itio nin g

Connector

Cond itio nin g

Input

Chan ne l B

Connector

Trigger (1d)

Cont rol (4 )

Trigger

LVPECL

Distribution

Input

Trigger

Connector

Data (21)

an d L EDs

Debu g I Os

Power

The numbers in brackes denote

the amount of FPGA IO pins

requires. 'd' is used for differential

pairs. 1d Will thus requre 2 IOs

Notes:

Version 1.3 Page 9 of 41 SMT391-VP User Manual

The SMT391-VP is made of two sub-modules combined. To make a SMT391-VP
you combine the base module SMT338-VP to the daughter module SMT391.

The SMT391 is responsible for the analogue side of the functionality. The ADC is on
this module. The

user manual of the SMT391 gives all information about the

analogue features of the SMT391 (performances, analogue inputs, …)

The SMT338-VP is responsible for the digital side of the functionality. It implements
the interface to the SMT391 and the communication interfaces used to output the
data. These functionalities are implemented in a Xilinx Virtex-II Pro FPGA
(

XC2VP30-6 in FF896 package).

ADC

AT84AD001B

The SMT391-VP is based on the Atmel dual 8-bit 1 Gsps ADC

AT84AD001B provides 1 Gsps sampling per channel or 2 Gsps sampling from

The

AT84AD001B .

one channel (in the interleaving mode) and integrates dual on-chip track/holds that
provide excellent dynamic performance over 1.5 GHz input frequency bandwidth with
low 1.4 W power consumption.

This Dual ADC is dedicated to high speed, low power applications such as digital
sampling oscilloscopes and direct RF down-conversion.

Refer to Atmel website for the details of this ADC.

Analogue features

The description of the analogue features of the SMT391-VP is available in the

user

manual of the SMT391.

FPGA

The SMT391-VP is populated with a Xilinx Virtex-II Pro FPGA (

XC2VP30-6 in FF896

package).
The digital data coming from the ADC is sent to the FPGA. The FPGA is used to

implement various communication interfaces. It implements the interface to the
daughter module SMT391.

It also implements the RSL and SDB communication interfaces used to send the data
out of the module as well as the comport communication interface used to control the
module. The FPGA also implement the interface to the on-board DDR SDRAM.

DDR SDRAM

The DDR SDRAM is not supported by the SMT391-VP.

Version 1.3 Page 10 of 41 SMT391-VP User Manual

SLB

The SMT391-VP is composed of the SMT391 module plugged on the base module
SMT338-VP. Both modules communicate via the SLB.

SDB

The SMT391-VP comes with two SHB connectors. A 32-bits SDB interface is
mapped on each of the SHB to output the data stored in the DDR SDRAM.

RSL

The SMT391-VP comes with 8 RSL that can carry the data stream coming from the
ADC at up to 1GB/s. RSL are used for real time applications.

Refer to RSL specification for a complete description.

Comport

The SMT391-VP provides two comports: comport 0 and comport 3. The comport 3 is
used to control the module.

The FPGA is configured at power-up over Comport 3. The configuration process is
controlled by a microprocessor (a Texas Instruments

MSP430 family microprocessor)

which shared the comport with the FPGA. Once the FPGA is configured the
configuration Comport is used for configuring control registers in the FPGA to control
the functions of the FPGA.

LED

Refer to the SMT338-VP user guide for the description of the LEDs.

External triggers

Two external triggers are available with the SMT391-VP. They are used to start the
acquisition of the analogue signal.

The external trigger input is received by a LVPECL input buffer on the SMT391. The
buffered signal is passed down as a differential LVPECL to the FPGA on the
SMT338-VP. For compatibility reasons with other daughter card modules there are
no ECL termination resistors mounted on the SMT338-VP. For this reason the pulse
width of the input trigger must be at least 1uS before the FPGA will register it.

As this might be a problem for some applications this issue has been resolved on the
newer SMT338-VP modules and appropriate termination resistors are provided to
improve the response time of the FPGA to an external trigger.

For most systems it is likely that there will be a system host (DSP Module). For this
reason it is also possible to send a software trigger to the SMT391-VP over Comport

3. There will however be latency from the time that the command is sent to the time
that data are acquired.

Version 1.3 Page 11 of 41 SMT391-VP User Manual

Clocks generation

The sampling clock of the ADC can be generated by an on-board VCO or an on­board clock synthesiser. Inputs for external clocks are available on the board but not
supported by the FPGA design.

Refer to the SMT391 user manual for further information.

Firmware

Block diagram

The following diagram represents the internal architecture of the FPGA of the
SMT391-VP.

Buffer SDB

SMT391
interface

block

64 bits

64 bits

Buffer

Registers Comport

RSL

RSL

SDB

SMT391 interface block

The following diagram shows the various blocks constituting the SMT391 block.
The SMT391 interface block implements the interface to the SMT391 daughter

module.
It receives the 1Gsps data stream coming from the ADC and provides it to the rest of

the design.
The data sampled by the ADC are output by this block, 8 samples at a time (64 bits)

at a 1/8 of the sampling clock of the ADC.

The firmware of the SMT391-VP supports one clock input for the ADC.
The ADC must be configured using the following clock selection mode:

- CLKI

Æ

ADCI

Version 1.3 Page 12 of 41 SMT391-VP User Manual

- CLKI Æ ADCQ

Any other configuration isn’t supported by the SMT391-VP. For example the
interlacing mode of the ADC is not supported by the default firmware of the
SMT391-VP.

The SMT391 block also includes the 3-wires interface used to configure the ADC as
well as the interfaces used to configure the clocks of the SMT391 daughter module.
Refer to the SMT391 user manual for more information about the clocks generation
feature of the SMT391-VP module.

ADC data interface
Support for a sub-set of the command controllable features of the Atmel ADC is

implemented in the firmware of the SMT391-VP. The ADC should be configured as
follow:

• Data Demux 1:2 mode

• Output Clock Fs/4

ADC 3-wire interface
The settings stored in the register block of the SMT391-VP are sent to the ADC via

this interface.
Refer to the appendix for more information about this interface.

PLL - VCO (LMX2330U) interface
A three wire uni-directional control interface is implemented between the FPGA and

the PLL on the daughter card. This PLL sets and controls the voltage for the VCO
that generates the main clock.

Refer to the

LMX2330U user guide for the detailed description of the PLL.

Clock synthesiser (SY89430) interface
A three wire uni-directional controls interface is implemented between the FPGA and

the Micrel clock synthesizer on the daughter card. The clock synthesizer can
generate a variable 50 – 950 MHz clock. The jitter on this clock is higher than on the
main PLL+VCO clock, but it is convenient for testing.

External clocks
The external clocks are not supported by the SMT391-VP.

Triggers
There are two main sources for the trigger. The first is an LVPECL trigger received

over the MMBX connector. The second is a trigger command. The trigger command
is received over the Comport interface.

Version 1.3 Page 13 of 41 SMT391-VP User Manual

When the SMT391-VP receives a trigger, the SMT391 interface block gets activated
and starts capturing the samples sent by the ADC.

Connector J9 should be used to externally trigger the acquisition of both channels I
and Q.

Connector J10 should be left unconnected.

The following diagram is a graphical representation of the trigger structure and
sources on the SMT391-VP:

FPGAExternal Trigger

External Trigger Input

(MMBX)

LVPECL

Buffer

Trigger Setup

Register

ComPort Interface

ComPo rt Rx Cmd

State Machine

Trigger Generation

Trigger

Distribution

Figure 1 – Module Trigger Structure.