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SMT384
User Manual
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Sundance SMT384 User Manual

SMT384
User Manual
Version 1.4 Page 2 of 47 SMT384 User Manual
Revision History
Date Comments Engineer Version
02/05/06 Original Version PhSR 1.0
26/01/07 Connector description and location added PhSR 1.2
25/05/07 FPGA Registers are read-back from FPGA. PhSR 1.3
25/11/09 Clarification AC/DC version PhSR 1.4
Version 1.4 Page 3 of 47 SMT384 User Manual
Table of Contents
Revision History............................................................................................................ 2
Table of Contents ......................................................................................................... 3
Table of Figures............................................................................................................ 5
Physical Properties ....................................................................................................... 7
Precautions................................................................................................................... 8
Introduction ................................................................................................................... 9
Overview ................................................................................................................... 9
Module features ........................................................................................................ 9
Possible applications .............................................................................................. 10
Related Documents ................................................................................................ 10
Functional Description ................................................................................................ 11
Block Diagram......................................................................................................... 11
Module Description ................................................................................................. 11
ADC Channels. ....................................................................................................... 13
ADC Main Characteristics. .................................................................................. 13
ADC Input Stage (standard SMT384). ................................................................ 14
Clock Structure........................................................................................................ 15
Power Supply and Reset Structure......................................................................... 17
Green LEDs. ........................................................................................................... 17
Mezzanine module Interface................................................................................... 17
Control Register Settings............................................................................................ 25
Control Packet Structure......................................................................................... 25
Reading and Writing Registers ............................................................................... 25
Memory Map ........................................................................................................... 26
Register Descriptions.............................................................................................. 27
Reset Register – 0x0........................................................................................... 27
Test Register – 0x1. ............................................................................................ 28
ADCA Register 0 – 0x2. ...................................................................................... 28
ADCA Register 1 – 0x3. ...................................................................................... 28
ADCA Register 2 – 0x4. ...................................................................................... 29
ADCB Register 0 – 0x5. ...................................................................................... 29
Version 1.4 Page 4 of 47 SMT384 User Manual
ADCB Register 1 – 0x6. ...................................................................................... 30
ADCB Register 2 – 0x7. ...................................................................................... 30
ADCC Register 0 – 0x8. ...................................................................................... 30
ADCC Register 1 – 0x9. ...................................................................................... 31
ADCC Register 2 – 0xA....................................................................................... 31
ADCD Register 0 – 0xB....................................................................................... 32
ADCD Register 1 – 0xC. ..................................................................................... 32
ADCD Register 2 – 0xD. ..................................................................................... 32
Main Module Temperature – 0x18 ...................................................................... 33
Main Module FPGA Temperature – 0x19 ........................................................... 33
Mezzanine Module Temperature – 0x1A ............................................................ 33
Mezzanine Module Converters Temperature – 0x1B ......................................... 33
Miscellaneous Register – 0x1C........................................................................... 33
Updates, Read-back and Firmware Version Registers – 0x1D .......................... 35
Decimator Register – 0x1E. ................................................................................ 35
AD9510 Register 0 – 0x30. ................................................................................. 36
AD9510 Register 1 – 0x31. ................................................................................. 36
AD9510 Register 2 – 0x32. ................................................................................. 36
AD9510 Register 3 – 0x33. ................................................................................. 36
AD9510 Register 4 – 0x34. ................................................................................. 37
AD9510 Register 5 – 0x35. ................................................................................. 37
AD9510 Register 6 – 0x36. ................................................................................. 37
AD9510 Register 7 – 0x37. ................................................................................. 37
AD9510 Register 8 – 0x38. ................................................................................. 38
AD9510 Register 9 – 0x39. ................................................................................. 38
AD9510 Register A – 0x3A. ................................................................................ 38
AD9510 Register 0 – 0x3B.................................................................................. 38
AD9510 Register 0 – 0x3C. ................................................................................ 39
AD9510 Register D – 0x3D. ................................................................................ 39
AD9510 Register E – 0x3E. ................................................................................ 39
AD9510 Register F – 0x3F.................................................................................. 39
AD9510 Register 10 – 0x40. ............................................................................... 40
AD9510 Register 11 – 0x41. ............................................................................... 40
Version 1.4 Page 5 of 47 SMT384 User Manual
AD9510 Register 12 – 0x42. ............................................................................... 40
AD9510 Register 13 – 0x43. ............................................................................... 40
AD9510 Register 14 – 0x44. ............................................................................... 41
AD9510 Register 15 – 0x45. ............................................................................... 41
AD9510 Register 16 – 0x46. ............................................................................... 41
AD9510 Register 17 – 0x47. ............................................................................... 41
AD9510 Register 18 – 0x48. ............................................................................... 42
AD9510 Register 19 – 0x49. ............................................................................... 42
PCB and Firmware Version Registers ................................................................ 42
FPGA Design.............................................................................................................. 43
Serial Interfaces ...................................................................................................... 43
Block of registers .................................................................................................... 44
Space available in FPGA ........................................................................................ 44
PCB Layout................................................................................................................. 44
Connectors ................................................................................................................. 46
Description .............................................................................................................. 46
Location on the board ............................................................................................. 47
Table of Figures
Figure 1 – Fan across PCI............................................................................................ 8
Figure 2 - Block Diagram............................................................................................ 11
Figure 3 - Main features. ............................................................................................ 14
Figure 4 - ADC Input Stage (AC coupling). ................................................................ 14
Figure 5 - ADC Input Stage (DC Coupling) ................................................................ 15
Figure 6 - Clock Structure........................................................................................... 15
Figure 7 - External Clock. ........................................................................................... 16
Figure 8 - Clock Architecture Main Characteristics.................................................... 17
Figure 9 – Mezzanine module Connector Interface (SLB data and power connectors).
.................................................................................................................................... 18
Figure 10 – Mezzanine Module Interface Power Connector and Pinout. .................. 20
Figure 11 – Daughter Module Interface: Data Signals Connector and Pinout (Bank
A). ............................................................................................................................... 21
Version 1.4 Page 6 of 47 SMT384 User Manual
Figure 12 – Daughter Module Interface: Data Signals Connector and Pinout (Bank
B). ............................................................................................................................... 23
Figure 13 – Daughter Module Interface: Data Signals Connector and Pinout (Bank
C). ............................................................................................................................... 24
Figure 14 – Setup Packet Structure. .......................................................................... 25
Figure 15 – Control Register Read Sequence. .......................................................... 25
Figure 16 – Register Memory Map............................................................................. 27
Figure 17 - Firmware Block Diagram.......................................................................... 43
Figure 18 – Main Module Component Side................................................................ 44
Figure 19 - Main Module (SMT368) Solder Side........................................................ 45
Figure 20 - Daughter Module Component Side. ........................................................ 45
Figure 21 - Daughter Module Solder Side.................................................................. 46
Figure 22 - Connectors Location. ............................................................................... 47
Version 1.4 Page 7 of 47 SMT384 User Manual
Physical Properties
Dimensions 63.5mm x 106.7mm x 18mm
Weight 35 grams
Supply Voltages
Supply Current +12V
+5V
+3.3V
-5V
-12V
MTBF
Version 1.4 Page 8 of 47 SMT384 User Manual
Precautions
In order to guarantee that Sundance’s boards function correctly and to protect the module from damage, the following precautions should be taken:
- They are static sensitive products and should be handled accordingly.
Always place the modules in a static protective bag during storage and transition.
- When operated in a closed environment make sure that the heat generated by the system is extracted e.g. a fan extracting heat or blowing cool air. Sundance recommends and uses PAPST 12-Volt fans (Series 8300) producing an air flow of 54 cubic meters per hour (equivalent to 31.8 CFM). Fans are placed so they blow across the PCI bus as show on the following picture:
Figure 1 – Fan across PCI.
Version 1.4 Page 9 of 47 SMT384 User Manual
Introduction
Overview
The SMT384 is a single width expansion TIM that plugs onto an SLB
(for instance SMT368
, SMT338-VP or SMT398-VP) and incorporates 4 Texas
base module
Instrument Analog-to-Digital Converters (ADS5500). The SMT384 implements a
comprehensive clock circuitry based on a AD9510
chip that allows synchronisation among the converters and cascading modules for multiple receiver systems as well as the use of an external reference clock. It provides a complete conversion solution and stands as a platform that can be part of a receive base station.
ADCs are 14-bit and can sample at up to 125 MHz. All converters are 3.3-Volt. As a standard, the ADCs are all AC-coupled (RF Transformers), but can also be optionally DC-coupled (TI opamp THS4509
The Xilinx FPGA
on the base module is responsible for handling data or control
commands coming from the TI converters, Comports (TIM-40 standard High-speed Bus (SHB
). These interfaces are compatible with a wide range of
).
), Sundance
Sundance’s modules.
Converter configuration, sampling and transferring modes are set via internal control registers stored inside the FPGA and accessible via Comport.
Module features
The main features of the SMT384 are listed below:
● Quad 14-bit 125MSPS ADC (ADS5500
),
MMCX
● On-board low-jitter clock generation (AD9510
),
● One external clocks, two external triggers and one reference clock via connector,
● One SLB
connector to link SMT384 and the base SLB module,
● Synchronisation signals,
● All Analogue inputs to be connected to 50-Ohm sources/loads.
● Temperature sensors.
Version 1.4 Page 10 of 47 SMT384 User Manual
Possible applications
The SMT384 can be used for the following application (this non-exhaustive list
should be taken as an example):
● High Intermediate-Frequency (IF) sampling architecture,
● Cellular base station such as CDMA and TDMA,
● Baseband I&Q systems,
● Wireless communication systems,
● Communication instrumentation,
● ...
Related Documents
ADS5500 Datasheet – Texas Instrument:
http://focus.ti.com/docs/prod/folders/print/ads5500.html
AD9510 Datasheet – Analog Devices:
http://www.analog.com/en/prod/0,2877,AD9510,00.html
Sundance High-speed Bus (SHB) specifications – Sundance.
ftp://ftp2.sundance.com/Pub/documentation/pdf­files/SHB_Technical_Specification.pdf
Sundance LVDS Bus (SLB) specifications – Sundance.
http://www.sundance.com/docs/SLB%20-%20Technical%20Specifications.pdf
TIM specifications.
ftp://ftp2.sundance.com/Pub/documentation/pdf-files/tim_spec_v1.01.pdf
MMCX Connectors – Hubert Suhner.
MMCX Connectors
Surface Mount MMCX connector
Sundance Multiprocessor Technology Ltd.
SMT368 SMT338-VP SMT398-VP
Version 1.4 Page 11 of 47 SMT384 User Manual
Functional Description
In this part, we will see the general block diagram and some comments on some the
SMT384 entities.
Block Diag ram
The following diagram describes the architecture of the SMT384, coupled – as an example – with an SMT368 to show how mezzanine and base modules are
connected together:
Figure 2 - Block Diagram.
Module Description
The module is built around four TI ADS5500
ADCs
: Analog data enters the module via four MMCX connectors, one for each
14-bit sampling analog-to-digital.
channel. Both signals are then conditioned (AC coupling as standard via RF transformers; DC optional via Texas Instrument amplifier THS4509) before being
Version 1.4 Page 12 of 47 SMT384 User Manual
digitized. ADCs get their own sampling clock, which can be either on-board generated or from an external reference or an external clock, common to all ADCs (MMCX connector). Digital samples travel to the FPGA on the base module via the
inter-module connector (SLB
– Sundance LVDS Bus, used in this case as ‘single-
ended’).
Clock generator and distribution
: All samplings clocks are generated by the same chip. It allows having them all synchronized to a single reference clock. The on-board clock uses the VCXO locked on an on-board 10MHz reference. The reference also can be external, in that case the VCXO is still used. In the case of an external clock, the VCXO is no longer used as the AD9510 then acts as a clock multiplexer. In all cases, all sampling clocks are synchronized to the same clock source.
Multi-module Synchronization
: SMT384s can be cascaded and still be synchronized
as either the external reference or the external clock can be passed the next module in the chain. The external reference goes through a 0-delay buffer and is then output. Please note that symchronisation is in frequency and not in phase.
Inter-module Connector
pins). It is called Sundance LVDS Bus. Please refer to the SLB specifications
: it is made of a power (33 pins) and data connectors (120
for
more details. In the case of the SMT384, the SLB is used as ‘single-ended’.
A global reset signal is mapped to the FPGA from the bottom TIM connector.
External Clock signals
, used to generate Sampling clocks. There is one external clock, common to all four ADCs. When used, the AD9510 is used as a clock multiplexer. Also available, an external reference clock that can be passed to an
other SMT384 (cascaded modules) module with ‘0-delay’.
External Trigger
: passed directly to the base module. There are two, one for each
pair of ADCs (Channel A & B and Channel C & D).
Temperature Sensor
: available for constant monitoring.
Version 1.4 Page 13 of 47 SMT384 User Manual
ADC Channels.
ADC Main Characteristics.
The main characteristics of the SMT384 ADCs are gathered into the following table.
Analogue Inputs
AC coupled option. 2.4 Vp-p (11.5 dbm –
50 Ohm) Full scale - AC coupled via RF transformer.
Input voltage range
Impedance
Bandwidth
External Reference Input
DC coupled option. 1.15 Vp-p (Gain
amplifier 6dB) centered around 0. DC coupled via amplifier. Gai n can be adjust ed to a required input amplitude centered around 0. Minimm gain 6dBs, which should allow input swing +/-0.575V as full scale.
AC Coupled option. ADC single-ended inputs are to be connected to an AC 50-Ω source. Source impedance matching implemented between RF transformers and ADC.
DC Coupled option. Impedance matching done at the connector. To be connected to a Dc 50-Ω source.
ADC bandwidth: 750 MHz.
Input Voltage Level
Input Impedance
Frequency Range
Output Voltage Level
Output Impedance
External Sampling Clock Input
Input Voltage Level
Input Format
Frequency range
Input Voltage Level
Format
0.5 – 3.3 Volts peak-to-peak (AC-coupled) 50-Ohm (Termination implemented at the
connector)
0 – 100 MHz.
External Reference Output
1.6 Volts peak-to-peak (AC-coupled)
50-Ohm (Termination implemented at the
connector)
0.5 – 3.3 Volts peak-to-peak (AC-coupled)
Single-ended or differential on option (3.3V
LVPECL).
10-125 MHz
External Trigger Inputs
1.5-3.3 Volts peak-to-peak.
DC-coupled and Single-ended (Termination implemented at the connector). Differentia l
Version 1.4 Page 14 of 47 SMT384 User Manual
on option (3.3 V PECL).
Impedance
Frequency range
Output Data Width
Data Format
SFDR
SNR
Minimum Sampling Clock
Maximum Sampling Frequency
Figure 3 - Main features.
ADCs Output
14-Bits 2’s Complement or offset binary (Changeable via control register) 82dBs maximum (manufacturer) 70dBs maximum (manufacturer)
10 MHz (ADC DLL off)
125 MHz (ADC DLL on)
50-Ohm.
62.5 MHz maximum
ADC Input Stage (standard SMT384).
Each ADC Analogue input is AC-coupled via and RF transformer. Both sides of the transformers are balanced so the input is 50-Ohm single-ended.
Figure 4 - ADC Input Stage (AC coupling).
The SMT384 can also receive an DC-coupling input stage on request as shown below :
It is based around a Texas Instrument amplifier (THS4509
), which gain is set to 6
dBs and is to match a 50-Ohm signal source.
Version 1.4 Page 15 of 47 SMT384 User Manual
Figure 5 - ADC Input Stage (DC Coupling)
Clock Structure
There is one integrated clock generator on the module (AD9510 – Analog Devices). The user can either use this clock (on-board) or provide the module with an external clock (input via MMCX connector).
Figure 6 - Clock Structure.
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