Sundance SMT381 User Manual
Unit / Module Name:
Dual channel 14-bit DAC – 840 MSPS
Unit / Module Number:
Used On:
Document Issue:
Date:
SMT381
SMT338-VP, SMT320, SMT310Q, SMT327, SMT300Q
1.6.0
23/09/2004
CONFIDENTIAL
Approvals Date
Managing Director
Software Manager
Design Engineer
Sundance Multiprocessor Technology Ltd, Chiltern House, Waterside, Chesham, Bucks. HP5 1PS.
This documents is the property of Sundance and may not be copied nor communicated to a third party
without the written permission of Sundance. © Sundance Multiprocessor Technology Limited 1999
Revision History
01/06/04
28/06/04
15/07/04
16/07/04
11/08/04
20/09/04
23/09/04
Changes Made Issue Initials
First release 1.0.0 LPS
Updated analog output circuit and PCB placement 1.1.0 LPS
General Updated to Document 1.2.0 LPS
Updated ext clock input description and updated part
1.3.0 LPS
descriptions
Added figure indicating test points on SMT381 1.4.0 LPS
General Updates to Document 1.5.0 MRV
Added waveform performance specifications 1.6.0 MRV
List of Abbreviations
Abbreviation Explanation
ATP Acceptance Test Procedure
BCD Binary Coded Decimal
BER Bit Error Rate
BOM Bill Of Materials
CDR Clock and Data Recovery
CPCI Compact PCI
DAC Digital to Analog Converter
DDR Double Data Rate
DLL Delay Lock Loop
DSP Digital Signal Processor
FPGA Field Programmable Gate Array
GSPS Giga Sample Per Second
LSB Least Significant Bit
LVDS Low Voltage Differential Signalling
LVPECL Low Voltage Positive ECL
MSB Most Significant Bit
NA Not Applicable
PC Personal Computer
PCB Printed Circuit Board
PCI Peripheral Component Interconnect
POR Power On Reset
RSL Rocket Serial Link
RSLCC Rocket Serial Link Communications Channel
SDRAM Synchronous Dynamic Random Access Memory
SHB Sundance High-speed Bus
SI Serial Interface
SMT Sundance Multiprocessor Technology
SPI Serial Peripheral Interface
TBD To Be Determined
TI Texas Instruments
VCO Voltage Controlled Oscillator
Table of Contents
1 Introduction...........................................................................................................10
1.1 Overview ........................................................................................................10
1.2 Module Features.............................................................................................10
1.3 Possible Applications......................................................................................10
1.4 Related Documents........................................................................................11
2 Functional Description...........................................................................................12
2.1 Module Overview............................................................................................12
2.2 Communication Ports (ComPorts) ..................................................................13
2.3 Sundance High-Speed Bus (SHB)..................................................................13
2.4 Main Analogue characteristics........................................................................14
2.5 Data stream description..................................................................................14
2.5.1 Description of internal FPGA blocks ............................................................15
2.6 Clock Structure...............................................................................................17
2.7 Trigger Structure.............................................................................................18
2.8 Power Supply and Reset Structure.................................................................19
2.9 MSP430 Functionality.....................................................................................20
2.10 FPGA Configuration......................................................................................22
2.11 Analogue output section...............................................................................22
2.12 DAC Settings................................................................................................24
3 Description of interfaces........................................................................................24
3.1 DAC Control Interface.....................................................................................24
3.2 DAC Data Interface ........................................................................................25
3.3 Memory Interface............................................................................................25
3.4 MSP430 Interface...........................................................................................25
3.5 Serial Number ................................................................................................25
3.6 PLL Interface..................................................................................................25
3.7 Clock Synthesizer Interface............................................................................26
3.8 TIM Interface..................................................................................................26
3.9 External Trigger..............................................................................................26
3.10 Daughter card Interface................................................................................26
3.11 RSL Interface (RSL not yet available)...........................................................33
3.11.1 RSL Connector and Pinout Definition.....................................................33
3.11.2 RSL Cable Definition..............................................................................35
3.12 SHB Interface...............................................................................................35
4 Firmware Description............................................................................................39
4.1 Main States ....................................................................................................39
4.2 Configuring the FPGA.....................................................................................40
4.3 Setting up the FPGA.......................................................................................40
5 Control Register Settings......................................................................................41
5.1 Control Packet Structure.................................................................................41
5.2 Reading and Writing Registers.......................................................................42
5.3 Memory Map ..................................................................................................43
5.4 Register Descriptions......................................................................................45
5.4.1 The Reset Register..................................................................................45
5.4.2 Firmware Version Register (Read Add 0x000) .........................................45
5.4.3 Temperature Registers (Read Add 0x020, 0x021, 0x028,0x029).............46
5.4.4 Serial Number Registers (Read Add 0x022 – 0x025 and 0x02A – 0x02D)
.........................................................................................................................46
5.4.5 DAC Clock Source Registers (Write Add 0x801)......................................47
5.4.6 Clock Synthesizer Setup Register (Write Add 0x800)...............................47
5.4.7 PLL Setup Registers (Write Add 0x802 – 0x809) .....................................48
5.4.8 DAC Setup Registers (Write Add 0x900 – 0x905)....................................48
6 PCB Layout...........................................................................................................50
6.1 SMT381 PCB View.........................................................................................50
6.2 Assembly Drawings........................................................................................51
6.3 SMT338-VP Assembly Drawings....................................................................53
6.4 SMT381 PCB View.........................................................................................54
7 General Properties................................................................................................58
7.1 FPGA Mounted on SMT338-VP......................................................................58
7.2 Design Resource Usage.................................................................................58
7.3 Power Supply.................................................................................................58
7.4 Module Dimensions........................................................................................59
7.5 FPGA/JTAG Connector..................................................................................60
8 System Setup........................................................................................................61
8.1 How to connect the SMT381 to SMT338-VP ..................................................61
9 Module Performance.............................................................................................65
9.1 Introduction.....................................................................................................65
9.2 LVDS Data interface.......................................................................................65
9.3 Waveform Memory.........................................................................................66
10 Firmware Building Blocks....................................................................................70
10.1 Introduction...................................................................................................70
10.2 Clock Synthesizer......................................................................................... 70
10.3 DAC serial setup...........................................................................................71
10.4 PLL Configuration.........................................................................................74
11 Test Points..........................................................................................................77
12 APPENDIX A – Waveform Memory Setup ..........................................................78
12.1 Introduction...................................................................................................78
10.2 System Setup...............................................................................................78
10.2 Software Setup.............................................................................................78
Table of Tables
Table 1. Main analogue characteristics of the SMT381............................................14
Table 2. Daughter Card Interface Power Connector and Pinout...............................29
Table 3. Register Memory Map (DAC registers not yet fixed in firmware).................45
Table 4. Table of Connector Locations on SMT381. ................................................56
Table 5. Table of Component Locations on SMT381................................................57
Table 6. Virtex-II Pro IO Count.................................................................................58
Table 7. Virtex-II Pro Device Utilization Summary....................................................58
Table 8. SMT381 Power Supply Voltages................................................................59
Table 9. SMT381-VP Power Supply Voltages..........................................................59
Table 10. Internal Power Supply Voltages................................................................59
Table 11. SMT381-VP Dimensions..........................................................................60
Table 12. Clock Synthesizer Test Output.................................................................70
Table 13. Clock Synthesizer Division Setup.............................................................71
Table 14. Configuration of the DACSerialSetupReg register....................................73
Table of Figures
Figure 1. Functional Block diagram of SMT381........................................................12
Figure 2. Internal Data path of the SMT338-VP........................................................15
Figure 3. Clock tree of the SMT381..........................................................................17
Figure 4. Trigger structure of the SMT381 and SMT338-VP.....................................19
Figure 5. Power Generation and distribution............................................................20
Figure 6. Microcontroller State Machine...................................................................21
Figure 7. Option 1 for the SMT381 analog output stage...........................................23
Figure 8. Option 2 for the SMT381 analog output stage...........................................23
Figure 9. Combined analog output circuit.................................................................24
Figure 10. Daughter card connector interface..........................................................27
Figure 11. Daughter Card Interface: Data Signals Connector and Pinout (Bank A).30
Figure 12. Daughter Card Interface: Data Signals Connector and Pinout (Bank B).31
Figure 13. Daughter Card Interface: Data Signals Connector and Pinout (Bank C).32
Figure 14. Rocket Serial Link Interface. ...................................................................33
Figure 15. Rocket Serial Link Interface Connector and Pinout (RSL A)....................34
Figure 16. Rocket Serial Link Interface Connector and Pinout (RSL B)....................35
Figure 17. Samtec HFEM Series Data Cable...........................................................35
Figure 18. Possible SHB Configurations. .................................................................36
Figure 19. SHB Connector Configuration 1 Pinout...................................................37
Figure 20. SHB Connector Configuration 2 Pinout...................................................38
Figure 21. SMT381-VP Firmware State Diagram.....................................................39
Figure 22. Setup Packet Structure. ..........................................................................41
Figure 23. Packet Structure – Defined Commands. .................................................42
Figure 24. Control Register Read Sequence............................................................42
Figure 25. Reset Register (Write Only).....................................................................45
Figure 26. Firmware Version Register (Read Only)..................................................45
Figure 27. Temperature Registers (Read Only)........................................................46
Figure 28. Serial Number Registers (Read Only).....................................................46
Figure 29. Serial Number Registers Cont. (Read Only)............................................47
Figure 30. Clock Source Selection Table (Write Only)..............................................47
Figure 31. Clock Source Register (Write Only).........................................................47
Figure 32. Clock Synthesizer Setup Register (Write Only). ......................................47
Figure 33. PLL Setup Registers (Write Only). ..........................................................48
Figure 34. DAC Setup Registers (Write Only). .........................................................48
Figure 35. SMT 381 PCB layout - TOP. ...................................................................50
Figure 36. SMT 381 PCB layout – BOTTOM............................................................50
Figure 37. SMT381 Top Assembly Drawings. ..........................................................51
Figure 38. SMT381 Bottom Assembly Drawings......................................................51
Figure 39. Main Module Top Assembly Drawing......................................................53
Figure 40. Main Module Bottom Assembly Drawing.................................................54
Figure 41. Side view of SMT381-VP (Height)...........................................................54
Figure 42. Side view of SMT381-VP. .......................................................................55
Figure 43. Top view of SMT381-VP. ........................................................................55
Figure 44. Connector Location on SMT381,.............................................................56
Figure 45. FPGA/JTAG connector for the SMT381-VP. ...........................................60
Figure 46. SMT381 to SMT338-VP Interconnection.................................................61
Figure 47. Components Used to Connect the SMT381 to the SMT338-VP..............62
Figure 48. Fitting of Nylon Screws and Nuts to the SMT338-VP. .............................63
Figure 49. Securing the SMT338-VP onto a Sundance Carrier................................63
Figure 50. Connecting the SMT381 to the SMT338-VP............................................64
Figure 51. Time View Captures of LVDS Interface Data...........................................65
Figure 52. Measurements of Time View Capture. ....................................................65
Figure 53. Waveform Memory - Time View Capture – 1000MHz sample frequency
(500MHz VCO Clock) – 125MHz analog output................................................66
Figure 54. Measurements of Capture – 1000MHz sample frequency (500MHz VCO
Clock) – 125MHz analog output........................................................................66
Figure 55. Waveform Memory - FFT – 1000MHz sample frequency (500MHz VCO
Clock) – 125MHz analog output – Channel A....................................................67
Figure 56. Waveform Memory - FFT – 1000MHz sample frequency (500MHz VCO
Clock) – 125MHz analog output – Channel B....................................................67
Figure 57. Waveform Memory - FFT – 1400MHz sample frequency (700MHz
Synthesizer Clock) – 175MHz analog output – Channel A................................68
Figure 58. Waveform Memory - FFT – 1400MHz sample frequency (700MHz
Synthesizer Clock) – 175MHz analog output – Channel B................................68
Figure 59. Waveform Memory - FFT – 600MHz sample frequency (300MHz VCO
Clock) – 75MHz analog output – Channel A......................................................69
Figure 60. Waveform Memory - FFT – 600MHz sample frequency (300MHz VCO
Clock) – 75MHz analog output – Channel B......................................................69
Figure 61. Clock Synthesizer Register.....................................................................70
Figure 62. Clock Synthesizer Frequency Calculation. ..............................................71
Figure 63. DAC serial write operation.......................................................................72
Figure 64. DAC serial read operation.......................................................................72
Figure 65. State machine of the DAC for the SMT381..............................................73
Figure 66. Register Setup for PLL............................................................................74
Figure 67. PLL Configuration Sequence...................................................................75
Figure 68. State Machine Driving the PLL Serial Interface. ......................................76
Figure 69. Test point locations on the SMT381........................................................ 77
Figure 70. Test Program Main Menu........................................................................ 78
Figure 71. SMT338-VP Sub-Menu...........................................................................79
Figure 72. SMT381 Sub-Menu.................................................................................80
Figure 73. Waveform Memory Setup Sequence.......................................................81
Precautions (Please Read this!).
In order to guarantee that the SMT381-VP functions correctly and
to protect the module from damage, the following precautions
should be taken:
The SMT381-VP is a static sensitive product and should be
handled accordingly. Always place the module in a static protective
bag during storage and transition.
When operated, make sure that the heat generated by the system
is extracted e.g. by the use of a fan extractor or an air blower.
SHB and RSL connectors are similar but their use is really
different. Do NOT connect an SHB and an RSL connectors
together with and SHB cable! This would cause irreversible
damages to the modules.
Naming Conventions.
The SMT381 refers to a dual channel, 14-bit, 840MSPS DAC
daughter card.
The SMT338-VP refers to a single width Virtex-II Pro based FPGA
module with a Sundance LVDS Bus interface (used for connecting
TIM modules to daughter cards)
The SMT381-VP refers to the SMT381 plugged onto the SMT338VP forming a complete module DAC + FPGA Module.
1 Introduction
1.1 Overview
The SMT381-VP is a single width expansion module that plugs onto the SMT338-VP.
It is capable of converting two external digital inputs coming form the SMT338-VP at
840 MSPS with a resolution of 14 bits, or from internal memory at 1GSPS. A Fujitsu
dual channel DAC (MB86064) performs the digital to analogue conversion.
The SMT381 (daughter card) is plugged into the SMT338-VP (main module). Digital
data is then supplied from the SMT338-VP via the daughter card connector over the
Sundance LVDS Bus to the SMT381 which converts the digital data stream to an
analogue signal.
The SMT338-VP controls data transfers via ComPorts, Sundance High-speed Bus
(SHB) or the Rocket Serial Link (RSL) (The RSL interface is not yet implemented).
These interfaces are compatible with a wide range of Sundance processor and I/O
modules.
A very important aspect must be kept in mind by the user. The DAC is rated for
1 GSPS but the SMT338-VP’s FPGA can only supply data to the DAC at 840MHz. It
is however possible to load data into the onboard memory on the DAC. This internal
data can be converted at 1GSPS.
1.2 Module Features
The main features of the SMT381 are listed underneath:
• Dual channel DAC
• 1 GSPS conversion frequency from internal memory
• 840MSPS conversion frequency for data coming from the SMT338-VP
• 14 Bit data resolution
• Custom Clock and Trigger inputs via external connectors
• Internal Waveform generator
• Standard Sundance ComPorts and SHB interfaces for easy interconnection to
Sundance products (interfaces for data sample and non-real-time processing)
1.3 Possible Applications
The SMT381-VP can be used for the following applications (this non-exhaustive list
should be taken as an example):
• Broadband cable modem head-end systems
• 3G Radio transceivers
• High-data-rate point-to-point radios
• Medical imaging systems
• Spectrum analyzers
1.4 Related Documents
[1] Sundance High-speed Bus (SHB) specifications – Sundance.
ftp://ftp2.sundance.com/Pub/documentation/pdffiles/SHB_Technical_Specification_v1_0.pdf
[2] RocketIO Serial Links (RSL) specifications – Sundance.
ftp://ftp2.sundance.com/Pub/documentation/pdffiles/RSL_Technical_Specification_v1_0.pdf
[3] TIM specifications.
ftp://ftp2.sundance.com/Pub/documentation/pdf-files/tim_spec_v1.01.pdf
[4] Sundance LVDS Bus (SLB) specifications – Sundance.
http://www.sundance.com/docs/SLB%20-%20Technical%20Specifications.pdf
[5] Virtex-II Pro FPGA datasheet - Xilinx.
http://direct.xilinx.com/bvdocs/publications/ds083.pdf
[6] Fujitsu MB86064 DAC datasheet.
http://www.fme.fujitsu.com
[7] ComPort specification – Texas Instruments.
http://focus.ti.com/lit/ug/spru63c.pdf
2 Functional Description
2.1 Module Overview
600MHz 1200MHz
VCO
div
2
SMT338
FPGA
Ext
Trigger
(1d)
Daughter
Card
Connector
The numbers in brackes denote the
Notes:
amount of FPGA IO pins requires.
'd' is used for differential pairs. 1d
Will thus requre 2 IOs
Data Sync Clock (1d)
Data Channel A (14d)
Data Channel B (14d)
Loop Clock (1d)
Loop Clock (1d)
SMT381SMT338-VP
Ext
Trigger
Ch A and Ch B
div
Input Clock (1d)
8
1V8
Convertor
circuit
Figure 1. Functional Block diagram of SMT381.
Clock Generation
Distribution
Digital to Analog
(MB86064)
Control (4)
LVPECL
and
Input Clock
Convertor
25MHz 400MHz
Clock Synth
(1d)
External Clock
Signal
Conditioning
Signal
Conditioning
Output
CHA
Output
CHB
Ch
A
Ch
B
The SMT338-VP sends the digital data to the module via the daughter card
connector. Data is clocked out of the FPGA on both edges of the DAC clock (DDR).
The user can provide this clock by means of the VCO, Clock synthesizer or custom
external clock. The external clock can be provided as an LVPECL clock or as an RF
clock (two separate inputs).
All digital functions on the module are controlled by the SMT338-VP. There are two
14-bit LVDS ports on the DAC which converts the data on a DDR clock. The sampled
data can either be supplied to the DAC cores externally via the LVDS data bus or
internally from the Waveform Memory Module. The data may be routed to the DAC
cores through a number of paths. The most direct path routes data straight from the
LVDS input buffers to the DAC core input latches.
There are two DAC cores present in the MB86064. Thus two channels are available
for outputs. The outputs of the DAC are differential currents, which are converted to a
voltage by the analogue output stage. Details on the set up will be discussed later.
The design of the SMT381 is split over two PCBs. The main PCB (main module –
SMT338-VP) contains the FPGA and the digital connector interfaces (TIM, SHB and
RSL). The main memory as well as the MSP430 microprocessor is also located on
this PCB. The second PCB (daughter card – SMT381) contains all the analog
circuitry. The clock generation, trigger control, analog signal conditioning and DAC is
located on this PCB. The SMT381-VP refers to the combination of the SMT338-VP
and the SMT381.
The depth of the SMT381-VP is 21 mm. If the SMT381-VP is mated with a PCI
carrier two PCI slots will be required for the Module + Carrier combination. If the
SMT381-VP is mated with a cPCI carrier the Module + Carrier will require two cPCI
slots.
The FPGA gets control words over a ComPort interface following the Texas
Instruments C4x ComPort standard. The FPGA receives data through the onboard
memory or SHB interface. It is then sent to the DAC cores over two 14-bit LVDS
busses according to the SLB standard. The DACs convert the data and sends the
data to the output connectors.
Two full (60-pin) SHB connectors are accessible from the FPGA. Their main function
is to receive digital samples from other modules. Please refer to the SHB
specification for more details about the way connectors can be configured.
A global reset signal is mapped to the FPGA from the bottom TIM connector via the
MSP430 microcontroller.
2.2 Communication Ports (ComPorts)
The SMT381-VP provides two ComPorts – ComPort 0 and ComPort 3. Both of these
ComPorts are connected to the FPGA on the SMT338-VP. ComPort 3 is also
connected to the MSP430 microprocessor. The microprocessor is the master of this
ComPort after reset and configures the FPGA with configuration data received over
this link. After configuration the microprocessor releases the ComPort to the FPGA.
These ComPorts are driven at 3.3V levels.
2.3 Sundance High-Speed Bus (SHB)
Two SHB connectors are used to transmit data to the SMT381-VP from the external
world. Both SHB busses are identical and 60-bits wide. See the SHB specification
for more information.
2.4 Main Analogue characteristics
The main analogue characteristics are listed in the following table:
Analogue outputs
Output current range 20mA
Data Format Analogue current
External sampling clock inputs (The clock frequency is divided by 2 on the SMT381 for a DDR clock for the DAC)
LVPECL Clock
Signal format LVPECL
Frequency range 25MHz to 1000 MHz
RF Clock
Signal format Sinus wave
Frequency range 25MHz to 1000 MHz
Amplitude 0dBm Typ
External trigger inputs
Signal format LVPECL
Frequency range DC to 100 MHz
ADC Performance @ Single tone at -1dBFS, 800MSa/s, DC to 400MHz (From DAC datasheet)
Spurious Free Dynamic Range (SFDR) @ 20MHz
Spurious Free Dynamic Range (SFDR) @ 300MHz
Cross-talk 4 tone test, each tone at -15dBFS, centred at 276MHz
75dBc
58dBc
67dBc
Table 1. Main analogue characteristics of the SMT381.
2.5 Data stream description
The data paths for both channels on the module are the same. The DAC is driven by
a single clock either generated on the module or provided by the user through an
MMBX connector. As only a single clock is present on the module the two data-paths
will always be in exact synchronization. As the data path on this module finds its
origin in the SMT338-VP’s FPGA the internal data path of the FPGA must also be
explained. Figure 2 shows the SMT338-VP’s FPGA data path.
DDR SDRAM
Memory Interface
DAC
Channel A
DAC
Channel B
Mux
Mux
Pre-process
Data
Pre-process
Data
Pre-process
Data
Pre-process
Data
Retrieve from
Memory
Retrieve from
Memory
Memory Interface
DDR SDRAM
Store in
Memory
Store in
Memory
SHB
Interface
SI
SI
SHB
Interface
SHB for Channel A
RSL for Channel A
RSL for Channel B
SHB for Channel B
Figure 2. Internal Data path of the SMT338-VP.
The digital data stream is received from two interfaces. The first data stream is a
direct RSL interface for real-time type applications (RSL is not yet implemented).
While the second stream comes from the DDR SDRAM memory for non-real-time
type module transmits (the memory is initialized over the SHB interface).
Each data stream is then conditioned and sent to the SMT381 via the daughter card
connector. A multiplexer selects between the two data streams.
2.5.1 Description of internal FPGA blocks
Pre-processing Data
The user can implement his own type of processing on the data stream if required.
SI
The Serial Interface block takes the high-speed serial input data stream and converts
it into a parallel data stream (Not yet implemented).
Mux
The multiplexer connected to the RSL and SHB/memory interfaces selects between
these two data streams to send to the SMT381.
Store in Memory
The store in memory block takes the incoming data stream from the SHB and stores
the data into DDR SDRAM. This block will only transfer data from the memory to the
SMT381 when a valid trigger command is received. The amount of data that must be
stored is configurable.
Memory Interface
The memory interface block is the DDR SDRAM controller. This block is responsible
to all write and read transactions to and from the DDR SDRAM.
Retrieve from Memory
The retrieve from memory block retrieves stored data in the DDR SDRAM when it
receives a valid read command. The read command specifies the location and
amount of data that needs to be retrieved.
SHB Interface
The data received from the SHB interface is stored in memory. The SHB interface
controls the SHB bus between the SMT338-VP and any module connected to the
SHB sending the data.
In addition to the above interface blocks the FPGA also implements the following
functions (not indicated on the diagram):
Trigger Interface
Handles all triggers. Triggers may be received from the external hardware trigger
connectors (two separate triggers – one for each channel), or by receiving a trigger
command over the ComPort (also separate commands for each channel). When a
trigger is received data is sent to the SMT381 from the memory on the SMT338-VP.
DAC Control Interface
Control interface for writing setup information to the DAC on the SMT381 to configure
it for any selected mode of operation. Data is received over the ComPort interface
and written out to the DAC over a serial interface.
Clock Synthesizer Interface
Control interface for writing setup information to the clock synthesizer on the SMT381
to configure its clock output frequency. Data is received over the ComPort interface
and written out to the clock synthesizer over a serial interface.
PLL Interface
Control interface for writing setup information to the PLL on the SMT381 to configure
the VCO output voltage. Data is received over the ComPort interface and written out
to the PLL over a serial interface. The PLL drives one VCO circuit. This VCO + PLL
circuit generates the main system clock and is configurable between 600 and 1200
MHz. The side is called the RF side. This clock is then divided by two which enables
the DAC to have a very stable PLL + VCO clock ranging from 300 to 600MHz.
DAC Interface
The DAC interface sends a high speed data stream from the FPGA to the DAC
present on the SMT381. There are two channels available on the DAC and data is
latched into the DAC on the rising and falling edge (DDR) of the DAC’s input clock
which is clocked into the FPGA to make data synchronization easier. The inputs are
14bit data streams which is clocked out of the FPGA at a maximum frequency of
420MHz (on both edges, thus 840MSPS).
Clock Tree Setup Interface
There are various clock routing configurations available for the SMT381. This
interface configures the clock tree.
2.6 Clock Structure
There are two integrated clock generators on the module. The user can either use
these clocks or provide the module with an external clock (input via MMBX
connectors). The following figure shows the SMT381 clock tree.
External Clocks
Ext RF
Clock
Input
(MMBX)
ECL
Comp-
arator
2:1 Mux
Clock Div 2
External Trigger
External Trigger Input
(MMBX)
Ext
LVPECL
Clock
Input
(MMBX)
ECL
Reciever/
Driver
Clock
Div 8
Clk Synth (25MHz -
400MHz)
Clk Synth
LVPECL
Buffer
3:1 Mux with Dual Output
Fanout
Buffer
DAC
VCO (600MHz -
1200MHz)
PLL
Voltage Controlled
Oscillator
Comparator
div 2
TTL to LVPECL
Loop
Clock
DAC clock
output
(MMBX)
LVPECL
Buffer
PLL
SMT338
Data
Clock
Clock
Control
Figure 3. Clock tree of the SMT381.
The main clock tree of the SMT381 consists of two clock sources to achieve the
DAC’s full range of input frequencies (DC – 500MHz). The first clock source is a
MICREL clock synthesizer which has a range from 50MHz to 950MHz. This source’s
disadvantage however is that it has a jittery output and thus the clock is not that
stable. Its advantage however is that it can attain a wide range of frequencies,
especially the lower frequencies. The output clock is LVPECL.
The second clock source is a voltage controlled oscillator with a phase lock loop.
This combination has a very stable output. However a limited frequency range can be
attained by this combination (300MHz – 600MHz). This is achieved by taking a
600MHz -1200MHz VCO and dividing the output by 2. The output clock must also be
scaled to LVPECL.
Alternatively the user can provide the module with an external LVPECL clock or an
external RF clock. The user can select between any of these input clocks.
The selected clock then drives the DAC and is also distributed to the main module
(SMT338-VP) for data synchronization purposes. On the FPGA of the SMT338-VP a
PLL synchronizes the clock with the data being sent by using the supplied clock and
looping that same clock to the DAC and back. This technique synchronizes the clock
to the data is being sent out on (SMT338-VP side) even further with the clock used in
the DAC. Synchronization issues become a bigger factor as the clock frequencies get
bigger.
All the clock control is done on the SMT338-VP side in firmware on the FPGA. The
multiplexer selects the clock and this clock is then used inside the DAC and SMT338VP for data transmitting purposes. The set up of the clock packages is also done in
firmware.
Finally an external trigger is supplied to the SMT338-VP and the multiplexed clock
divided by 8. The trigger can be used for memory storing and retrieving functions etc.
while the clock divided by 8 is mainly for debugging purposes.
2.7 Trigger Structure
There are two main data-paths (per channel) for data received either from RSL
interface (not yet implemented) or SHB/memory interface. The first data path is
directly connected to the DAC interface and sends the data as is. The second data
path is either a direct link to the DAC interface or to memory. The trigger settings
differ depending on the path used.
There are two main sources for the trigger. The first is an LVPECL trigger received
over the MMBX connector (triggered on rising edge). The second is a trigger
command. The trigger command can be received either over the RSL interface or via
the ComPorts.
The following trigger settings are possible for the RSL interface (RSL not yet
implemented):
• Start transmitting data when a trigger is received. Stop transmitting when the
next trigger is received.
• Transmit a pre-determined amount of samples when a trigger is received.
• Ignore all triggers and transmit data continuously (cycle through memory).
The following trigger settings are possible for the DDR SDRAM data-path:
• Transmit a pre-determined amount of samples when a trigger is received, and
carry on cycling through them.
The following diagram is a graphical representation of the trigger structure and
sources on the SMT381 and SMT338-VP:
FPGAExternal Trigger
RSL CDR Interface
RSL Rx Cmd State
Trigger Generation
External Trigger Input
(MMBX)
LVPECL
Buffer
SMT338-VP
ComPort Interface
ComPort Rx Cmd
State Machine
Trigger Generation
SMT381
Trigger Setup
Register
Figure 4. Trigger structure of the SMT381 and SMT338-VP.
Machine
Trigger
Distribution
2.8 Power Supply and Reset Structure
The SMT381 uses the following voltages: 12V, -12V, 5V, -5.2V, 3.3V and 1.8V. Only
two voltages must be generated on the SMT381 as the rest are supplied by the
carrier. The voltages that must be generated are -5.2V and 1.8V. -5.2V is used for
the comparator and op amp in the clock circuitry while 1.8V is used for the serial
control interface on the DAC.
All the other voltages are supplied by the carrier and thus present on the SMT338-
VP. The required voltages are then supplied to the SMT381 by a daughter card
power connector present on the SMT338-VP and SMT381. The SMT381 plugs into
this power connector and thus has power for all its modules.
Pin X_RESET is the only reset option on the SMT381. This pin resides on the DAC.
On the falling edge of X_RESET the DAC is reset and all registers are set to their
default values. After a reset most parts of the device are powered down.
The following figure shows the power structure of the SMT338-VP and SMT381:
TIM Connector
D+5V0_IN
Vccaux
DC / DC
Converter
D+2V5
Daughter Card
D+5V0
TIM
Mounting Hole
D+3V3_IN
TIM Connector
D+12V0 and
D-12V0
Voltage
Measure
Vccint
DC / DC
Converter
Analog Power
Switch
Microprocessor
On / Off
Control
MSP430
D+1V5
D+3V3
Voltage
Measure
Main Module to
Daughter Card
Power
Connector
Low Dropout
Regulator
Analog Filter
Analog Filter
Analog Filter
Low Dropout
Regulator
D-5V2
D-12V0
D+12V0
D+3V3
A+3V3
D+1V8
Main Module
Figure 5. Power Generation and distribution.
2.9 MSP430 Functionality
The MSP430 implements analog control functionality that is difficult to implement in
the FPGA. The microprocessor
• Controls the power start-up sequence
• Controls the reset structure on the module
Figure 6. Microcontroller State Machine.
At power-up or on a TIM Reset or on a nConfig line going low, the state machine
goes into an INIT State. TIM Reset and nConfig lines are available on the carrier
module – see TIM Specifications for location on TIM connectors).
From there, it has two choices depending on the state of the FPGA (configured i.e.
DONE pin high or un-programmed i.e. DONE Pin Low). To configure the FPGA,
simply send a Start Key followed by the bitstream and then and End Key. To re-start
the FPGA with the current bitstream loaded, simply send a End Key.
Start Key = 0xBCBCBCBC and End Key = 0xBCBCBC00.
A TIM Reset can be issued to reconfigure the FPGA at anytime, but may reset other
modules as well. In the case of reconfiguring a particular module, the nConfig line is
used.
MSP430 is connected to ComPort 3 of the TIM. With the standard firmware
implementation ComPort 3 is used to communicate with the FPGA. ComPort 0 is
open for custom applications as it is not used by the SMT381-VP.
2.10 FPGA Configuration
In a typical Sundance system a carrier and host module (most likely a DSP module)
is needed to configure the SMT381-VP.
After a hardware reset the FPGA of the SMT381-VP is un-configured and the
microprocessor (MSP430) waits for a data stream. At this point the microprocessor is
in control of ComPort 3. The host can then send a data stream over ComPort 3
starting with a STARTKEY, then the data, and ending with an ENDKEY. This will
configure the FPGA via the microprocessor, and after configuration the
microprocessor will release ComPort3 so that the host can talk straight to the FPGA.
If at any time the host want to reset the FPGA the host must send a reset command
to it the SMT381-VP over the ComPort – Any hardware resets coming over the TIM
site will be caught by the microprocessor but will not be passed on to the FPGA.
If the FPGA is configured, but the host restarts its application, it must send an
ENDKEY only. This will ‘wake up’ the FPGA and the uP will release ComPort 3 so
that the host can use it for FPGA communication.
If the host want to reconfigure the FPGA it must toggle the nConfig line on the TIM
site. This will give control of the ComPort back to the microprocessor, but it will not
un-configure the FPGA. If the host then start sending a new bit-stream starting with a
STARTKEY, the FPGA will be un-configured and the new bit-stream will load. If after
toggling the nConfig line, if the host does not want to re-configure the FPGA, it must
send an ENDKEY like described above.
The above structure makes it possible to:
• Reset only the FPGA in the system and
• Make sure that the FPGA is not un-configured every time the host application
is re-run as it takes time for the FPGA to re-configure (approximately 35
seconds).
2.11 Analogue output section
Two options are hardwired into the design. The options are shown below with a
figure of each.
Option 1
Single ended AC coupled output with Macom TP-101 transformer.
TP101
+
Output
Connector
-
R1 R1
Figure 7. Option 1 for the SMT381 analog output stage.
Option 2
Differential DC coupled output with + and – channels going to separate connectors
+
Output
Connector
-
R2
Figure 8. Option 2 for the SMT381 analog output stage.
R2
Output
Connector
Combined circuit
The two combined:
+
-
0 ohm
TP101
R3 R3
0 ohm
Figure 9. Combined analog output circuit.
Depending on whether an AC or DC coupled version is ordered the board will be
assembled accordingly to either give the AC or DC coupled circuit shown above.
For more information consult the Fujitsu (MB86064) DAC datasheet [6].
2.12 DAC Settings
All DAC settings are controlled and implemented by the 4 wire serial control
interface. The serial interface uses pins SERIAL_IN, SERIAL_OUT, SERIAL_CLK
and SERIAL_EN. Programmed settings are stored in a number of registers which are
individually accessible using either a 7-bit (WMM Registers) or 10-bit (DAC Core
Registers) address/control word. Data may be written to or read from each of these
registers.
For more information consult the Fujitsu (MB86064) DAC datasheet [6].
3 Description of interfaces
3.1 DAC Control Interface
A four wire uni-directional control interface is implemented between the FPGA and
the DAC. This interface is used for clocking configuration information into the DAC.
Note 1: The serial interface on the DAC side uses 1.8V signalling levels. These
control lines are however connected unto a 3.3V bank on the FPGA with additional
pull-up resistors on the SMT381 to 1.8V. For this reason the FPGA firmware may
never drive ‘1’ out on these pins as it will drive the DAC at 3.3V and thus damage it.
The firmware may only drive ‘0’ for ‘0’ and ‘Z’ for ‘1’. Because of the pull-up resistor
the ‘Z’ will be pulled up to 1.8V. This approach works well and any used wishing to
develop his own firmware is advised to take a look at the SMT381 example firmware
before developing his own.
3.2 DAC Data Interface
The output of each channel from the SMT338-VP to the DAC is a 14 bit LVDS data
bus clocked on the synchronized DAC clock.
Note 1: The data bus between the FPGA and the DAC is wired in a strange way to
assist routing. If a user wants to develop his own VHDL design and not use the
example design he is advised to take a look at the wiring of the example design to
assist him with his own design.
Note 2: On Rev 01 of the SMT381 the positive and negative data pairs of the LVDS
bus between the FPGA and the DAC is swapped for one of the two channels. This
results in a data flip. This issue is corrected in firmware by inverting the data before
writing it out over the interface. Once again any user wanting to do his own design is
advised to take a look at the example firmware design.
3.3 Memory Interface
Two groups of two 16 bit Micron DDR SDRAMs form the volatile sample storage
space of the module. Each DDR SDRAM is 256 MBits in size. This provides the
module with a total of 64Mbytes (or 32 Mega samples) of storage space per channel.
Each channel contains a 32 bit DDR SDRAM controller. This interface is capable of
data transfer at 1 GBytes / s. It is thus fast enough to write the outgoing DAC data
stream.
3.4 MSP430 Interface
After configuration the microprocessor communicates with the FPGA using the IO
pins of the FPGA Slave Select Configuration interface. The MSP is the master of the
interface and will continually write the serial number and the measured on-board
voltages to the FPGA. A system host can then read this data from the FPGA over the
ComPort interface.
3.5 Serial Number
A Maxim 1-Wire silicon serial number device is located on the SMT381 and the
SMT338-VP. This is used to assign a unique serial number to each module.
3.6 PLL Interface
A three wire uni-directional control interface is implemented between the FPGA and
the PLL on the daughter card. This PLL sets and controls the voltage for the VCO
that generates the main clock.
Loading...