Sundance SMT376 User Manual

SMT376

User Manual

User Manual (QCF42); Version 3.0, 5/2/01; © Sundance Multiprocessor Technology Ltd. 2001

Version 1.7 Page 2 of 24 SMT376 User Manual

Revision History

Date Comments Engineer Version

17/7/02 First rev, based on 361 GP 1.0.0

14/10/02 Remove SDBC, comport 2,5 and update

Y.C 1.0.1

memory mapping

30/01/03 Firmware version 1.8 J.V 1.1

05/03/03 Firmware version 1.9

J.V. 1.4

Update of the pinout for serial port header

Table of content updated no other change

13/08/03 Firmware version display and update via the

J.V. 1.5

SMT6001 utility.

Comport notation updated and reference to
support system added.

26/08/03 Version number updated at the top of each

J.V. 1.6

page

19/08/03 McBSP table corrected J.V. 1.7

Version 1.7 Page 3 of 24 SMT376 User Manual

Table of Contents

Revision History ....................................................................................................... 2

Contacting Sundance............................................................................................... 4

Notational Conventions ........................................................................................... 5

SMT376 .................................................................................................................. 5

C60 ......................................................................................................................... 5

SDB ........................................................................................................................ 5

Register Descriptions.............................................................................................. 5

Outline Description .................................................................................................. 6

Block Diagram .......................................................................................................... 7

Architecture Description.......................................................................................... 7

TMS320C6211/6711 .................................................................................................. 8

Boot Mode............................................................................................................... 8

EMIF Control Registers........................................................................................... 9

SDRAM ................................................................................................................... 9

FLASH .................................................................................................................. 10

Version control ....................................................................................................... 10

Reprogramming the firmware and boot code ...................................................... 10

Interrupts................................................................................................................. 10

Communication ports ............................................................................................ 10

SDB.......................................................................................................................... 11

SDB Clock selection ............................................................................................. 11

Global bus............................................................................................................... 11

LED Setting ............................................................................................................. 12

LED Register......................................................................................................... 12

CONFIG & NMI ........................................................................................................ 12

Timer........................................................................................................................ 12

IIOF interrupt........................................................................................................... 12

Code Composer...................................................................................................... 12

Application Development....................................................................................... 13

Operating Conditions............................................................................................. 14

Safety.................................................................................................................... 14

Version 1.7 Page 4 of 24 SMT376 User Manual

EMC...................................................................................................................... 14

General Requirements.......................................................................................... 14

Power Consumption.............................................................................................. 14

Connector Positions .............................................................................................. 15

Virtex Memory Map................................................................................................. 16

Connector Pin-outs ................................................................................................ 18

SDB0 Pin-Out ....................................................................................................... 18

FPGA JTAG .......................................................................................................... 18

SHB pin-out........................................................................................................... 19

Serial Ports & Other C60 I/O (EXP connector)...................................................... 21

Serial Ports & Other C60 I/O (JP3 connector)....................................................... 22

FPGA PROG Pin Control (JP2 connector)............................................................ 22

DSP JTAG Control (JP1 connector)...................................................................... 22

Data Sheets (Hyperlinks) ....................................................................................... 23

Index ........................................................................................................................ 24

Contacting Sundance

You can contact Sundance for additional information log onto Sundance’s support
forum

http://support.sundance.com/

Version 1.7 Page 5 of 24 SMT376 User Manual

Notational Conventions

SMT376

Throughout this document the term SMT376 (or simply 376) will usually be used to
refer to all processor variants. It should be clear from the context when a distinction is
being drawn between the types of module.

C60

The term C60 will be used throughout this document in place of TMS320C6211,
6711 or 6713.

SDB

The term SDB will be used throughout this document to refer to a 16 bit data bus
carried by either an SDB connector or an SHB connector. The SHB connector can
carry two such SDB buses.

Register Descriptions

The format of registers is described using diagrams of the following form:

31–24 23–16 15–8 7–0

OFLAGLEVEL

R,00000000 RW,10000000 R,00000000 R,10000000

The digits at the top of the diagram indicate bit positions within the register and the
central section names bits or bit fields. The bottom row describes what may be done
to the field and its value after reset. Shaded fields are reserved and should only ever
be written with zeroes.

R Readable by the CPU

W Writeable by the CPU

RW Readable and writeable by the CPU

Binary digits indicate the value of the field after reset.

Version 1.7 Page 6 of 24 SMT376 User Manual

Outline Description

The SMT376 is a C6211/6711/6713-based size 1 TIM offering the following features:

 TMS320C6211 integer processor running at 150MHz

 TMS320C6711 floating point processor running at 150MHz

 TMS320C6713 floating point processor running at 225MHz

 Four 20MB/s communication ports (ComPorts)

 256MBytes of SDRAM (100MHz)

 2MByte Flash ROM for boot code and FPGA programming

 Global expansion connector

 High bandwidth data I/O via Sundance Digital Buses (SDB) and

 Sundance High-speed Buses (SHB)

Version 1.7 Page 7 of 24 SMT376 User Manual

Block Diagram

Linear regulators for
CPU & FPGA cores

4 LEDs &

4 I/O pins

JTAG Header

Sundance High-speed Bus

(60-way Samtec)

Sundance Digital Bus

(40-way ODU)

83 I/O

J1 Top Primary TIM

FPGA Controller

Spartan-IIE, FG456

Global Bus

J3 Global Expansion

Connector

Connector

Comm-Port 0 & 3

24 I/O pins

2x Comm-Ports/SDL

329 I/O Pins

XC2S300E

1.5V

74 I/O pins

J2 Bottom Primary TIM

15 I/O pins

Timer,& Control

24 I/O pins

2x Comm-Port/SDL

Connector

Comm-Port 1 & 4

(2 linked with 5)

TTL I/O

64 pins

McBSP

McBSP &

GPIO

Header

Flash (CE1)

Start-up mode selection.

256M bytes SDRAM (CE2,3)

8 x K4S560832

(32M x 8)

'C6711/6713

DSP

Architecture Description

The SMT376 TIM consists of a Texas Instruments TMS320C6211/6711/6713 running
at up to 225MHz. Modules are populated with 256MBytes of synchronous DRAM
(SDRAM).

A Field Programmable Gate Array (FPGA) is used to manage global bus accesses
and implement four communication ports and Sundance Digital/High-speed Buses.
This is a Xilinx Spartan –IIE device.

Version 1.7 Page 8 of 24 SMT376 User Manual

TMS320C6211/6711

The processor will run with zero wait states from internal SRAM. The internal memory
is 64k bytes in size and can be partitioned between normal SRAM and/or L2 cache.

An on-board crystal oscillator provides the clock used for the C60 which then
multiplies this by 4 internally.

Boot Mode

The SMT376 is configured to use the following boot sequence each time it is taken
out of reset:

1. The processor copies a bootstrap program from the first part of the flash
memory into internal program RAM starting at address 0.

2. Execution starts at address 0.

The standard bootstrap supplied with the SMT376 then performs the following
operations:

1. All relevant C60 internal registers are set to default values;

2. The FPGA is configured from data held in flash memory and sets up the
communication ports, the global bus and the Sundance Digital/High-speed
Buses. This step must have been completed before data can be sent to the
ComPorts from external sources such as the host or other TIMs;

3. A C4x-style boot loader is executed. This will continually examine the four
communication ports until data appears on one of them. The bootstrap will
then load a program in boot format from that port; the loader will not read data
arriving on other ports. See “Application Development” for details of the boot
loader format;

4. Finally, control is passed to the loaded program.