Sundance SMT374 User Manual

SMT374

User Manual

User Manual (QCF42); Version 3.0, 5/2/01; © Sundance Multiprocessor Technology Ltd. 2001

Version 2.2 Page 2 of 29 SMT374 User Manual

Revision History

Date Comments Engineer Version

07/01/03 First rev, based on 376 GP 1.0.0 08/01/03 Tidied Virtex memory map GP 1.0.1 07/03/03 Updated to match V1.2 of the Firmware J.V. 1.0.1 30/06/03 SDB added V1.6 of the firmware. J.V. 1. 0.3 07/07/03 DSP named corrected to DSPA and DSPB.

J.V. 1. 0.4 Comport performances. V1.6 of the firmware.

06/08/03 Update Comport naming.

J.V. 1. 0.5 Update reprogramming and external interface

switch register to use the SMT6001 software

22/08/03 Clarify EMIF register table (i.e. memory map)

J.V. 1. 0.6 Links added to firmware description document Version converted to 3 digits number

26/08/03 SDBC memory map corrected J.V. 1.0.7 04/02/04 Reference to SMT376 page 26 removed J.V. 1.0.8 14/04/04 Update to the external interface switch register

J.V. 1.0.9 to add a warning about dynamic setting in multiprocessor systems.

29/09/04 Added address of the DPRAM for each

J.V. 1.1 processor

04/08/05 Update: the user manual supports the new

SM 2.0

firmware implementation

18/10/05 Corrected: SHB architecture SM 2.1 14/02/06 Minor change: SHB architecture SM 2.2 19/07/06 Updates for the SMT374_300 EW 2.3

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Table of Contents

Revision History....................................................................................................... 2

Contacting Sundance............................................................................................... 4

Notational Conventions ........................................................................................... 5

DSP ........................................................................................................................ 5

SDB ........................................................................................................................ 5

SHB ........................................................................................................................ 5

Outline Description .................................................................................................. 6

Intended Audience ................................................................................................... 6

Block Diagram .......................................................................................................... 7

Architecture Description.......................................................................................... 8

DSPs....................................................................................................................... 8

Boot Mode............................................................................................................... 9

Board Control Registers (BCRs)............................................................................. 9

DPRAM................................................................................................................... 9

EMIF Control Registers........................................................................................... 9

SDRAM................................................................................................................. 10

FLASH .................................................................................................................. 10

FPGA.................................................................................................................... 11

Version control...................................................................................................... 11

Firmware versions.................................................................................................. 11

Reprogramming the firmware and boot code ...................................................... 11

Comports................................................................................................................. 12

SHB.......................................................................................................................... 13

Architecture........................................................................................................... 13

Global bus............................................................................................................... 14

LED Setting............................................................................................................. 14

LED Register DSP-A ............................................................................................. 14

LED Register DSP-B ............................................................................................. 14

CONFIG & NMI ........................................................................................................ 15

Config Register..................................................................................................... 15

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Timer........................................................................................................................ 16

Timer Control Register.......................................................................................... 16

Code Composer...................................................................................................... 17

Application Development....................................................................................... 17

SMT6400 .............................................................................................................. 17

3L Diamond........................................................................................................... 17

SMT6500 .............................................................................................................. 17

Operating Conditions............................................................................................. 18

Safety.................................................................................................................... 18

EMC...................................................................................................................... 18

General Requirements.......................................................................................... 18

Power Consumption.............................................................................................. 18

Connector Positions .............................................................................................. 19

Virtex Memory Map................................................................................................. 20

Connector Pin-outs ................................................................................................ 23

Serial Ports & Other DSP I/O (JP2 connector)...................................................... 23

SHB generic pin-out.............................................................................................. 24

SHBA pin-out........................................................................................................ 25

SHBB pin-out........................................................................................................ 26

FPGA PROG Pin Control (JP3 connector)............................................................ 27

FPGA JTAG.......................................................................................................... 27

Data Sheets (Hyperlinks) ....................................................................................... 28

Index........................................................................................................................ 29

Contacting Sundance

You can contact Sundance for additional information by login onto the Sundance

support forum.

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Notational Conventions

DSP

The term DSP will be used throughout this document in place of TMS320C6211, 6711 or 6713.

SDB

The term SDB will be used throughout this document to refer to the Sundance Digital Bus interface.

SHB

The term SHB will be used throughout this document to refer to the Sundance Highspeed Bus interface.

Register Descriptions

The format of registers is described using diagrams of the following form:

31–24 23–16 15–8 7–0

OFLAGLEVEL

R,00000000 RW,10000000 R,00000000 R,10000000

The digits at the top of the diagram indicate bit positions within the register and the central section names bits or bit fields. The bottom row describes what may be done to the field and its value after reset. Shaded fields are reserved and should only ever be written with zeroes.

R Readable by the CPU W

Writeable by the CPU

RW Readable and writeable by the CPU Binary digits indicate the value of the field after reset

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Outline Description

The SMT374 is a dual DSP, size 1 TIM offering the following features:

 TMS320C6211 integer processors running at 150MHz  TMS320C6711 floating point processors running at 150MHz  TMS320C6713 floating point processors running at 225MHz  TMS320C6713-300 floating point processors running at 300MHz  Six 20MB/s external communication ports (Comports)  256MB of SDRAM (100MHz, 128MB per DSP)  8MB Flash ROM  Global Bus connector  2 SHB connectors for high-speed data transfer

Intended Audience

There are two existing versions of the firmware for the SMT374. These two versions differ by the number and the type of communication resources (comport and SDB interfaces) provided.

For each of the versions of the different firmware is loaded in the FPGA:

- Firmware version 1.8 or

- Firmware version 2.0

This user manual covers the version 2.0 of the firmware for the SMT374 implemented with the model described in the

The changes between the firmware version 1.8 and version 2.0 are described in the section Firmware versions.

SMT6500 help file.

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Block Diagram

The following drawing shows the block diagram of the SMT374 module. The main components of the SMT374 are:

- Two Texas Instruments DSPs

- One Xilinx FPGA Virtex-II device

- 256MB of SDRAM

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Architecture Description

DSPs

The two Texas Instruments DSPs can run up to 300MHz. Each of them is doted of 128MB of Synchronous DRAM (SDRAM).

The DSPs can be of two types:

• TMS320C6211 or C6711 This is a fixed-point digital signal processor provided by Texas Instruments. The

processor will run with zero wait states from internal SRAM. The internal memory is 64KB in size and can be partitioned between normal SRAM and L2 cache.

A 37.5MHz on-board crystal oscillator provides the clock used for the DSP which then multiplies this by four internally. So the DSPs run at 150MHz.

• TMS320C6713 The processor will run with zero wait states from internal SRAM. The internal

memory is 256KB in size and can be partitioned between normal SRAM and L2 cache.

A 37.5MHz on-board crystal oscillator provides the clock used for the DSP which then multiplies this by a programmable amount internally to provide the required core and EMIF clocks. In this case the DSPs will run at 225MHz.

• TMS320C6713-300 The processor will run with zero wait states from internal SRAM. The internal

memory is 256KB in size and can be partitioned between normal SRAM and L2 cache.

A 50MHz on-board crystal oscillator provides the clock used for the DSP which then multiplies this by a programmable amount internally to provide the required core and EMIF clocks. In this case the DSPs will run at 300MHz.

Remark: SMT374_300 built before june 2006 may be fitted with a 37.5MHz instead of a 50MHz crystal oscillator. The DSPs will then run at 225MHz with the default bootloader. The SMT374_300 can be programmed with a “special” bootloader to make the DSPs run at 300MHz. Sundance will provide this “special” bootloader on demand:

http://support.sundance.com/viewtopic.php?p=19911#19911

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Boot Mode

The two DSPs are called DSP-A and DSP-B. DSP-A is connected to the on-board flash ROM that contains the Sundance bootloader and the FPGA bitstream.

Following reset, DSP-A will automatically load the first 1KB from the flash ROM into its internal memory at address 0 and then start executing from there; DSP-B remains held in reset. DSP-A now explicitly loads the next 3KB from ROM, giving the effect of an initial load of 4KB. All this code is the Sundance bootloader, and it is made up of three parts: FPGA configuration, processor configuration, and the Comport boot procedure. FPGA configuration uses data in the ROM to configure the FPGA. Processor configuration sets the processor into a standard state, copies its comport boot procedure into a 2KB dual-port RAM (DPRAM) implemented in the FPGA, and releases DSP-B from reset. DSP-B is configured to boot from this DPRAM, and this leaves both DSPs executing their own copies of the Comport boot procedure.

The DPRAM is managed by writing to one of the board control registers (BCR) implemented in a CPLD. The BCR bit functions are described in the SMT6001 help

file.

Board Control Registers (BCRs)

DSP-A will take approximately 800ms to configure the FPGA following reset, assuming a 150MHz clock. The external devices implemented in the FPGA (such as comports) must not be used during this configuration.

It is safest to wait for the configuration to complete. Note that comports will appear to be "not ready" until the FPGA has been configured.

The FPGA programming algorithm is not described here. It can be found in the boot code.

DPRAM

The DPRAM in the FPGA is only intended to be used during this boot process; more general use is not recommended. The DPRAM is accessible from the following locations:

• DSPA has access to the DPRAM from address 0xB0100000

• DSPB has access to the DPRAM from address 0x90000000

EMIF Control Registers

The DSP has a single external memory interface (EMIF) which is 32 bits wide.

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