Sundance SMT370 User Manual

SMT370v2/v3

User Manual

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999

Version 2.0 Page 2 of 46 SMT370v2/v3 User Manual

Revision History

Date Comments Engineer Version

14/02/03 First release PSR 1.0

08/03/03

31/03/03

Details added about registers and external signals – figure references – examples.

FPGA Firmware changed – ADC/DAC Triggers and ADC decimators added – SHBA and B 16

PSR 1.1

PSR 1.2

or 32 bits.

15/05/03 ComPorts description improved – Two

PSR 1.3 separate options to the board – FPGA Global reset register added – More comments on register settings – FPGA utilisation added – Example code removed

01/08/03 Corrects spelling mistakes - adds temperature

PSR 1.4 measurements – mentions SMT6600 package

05/09/03 One link (fig11 was missing) PSR 1.5

15/10/03 Updated for SMT370v3 PSR 1.6

17/12/03 Pattern generator description a bit confused.

PSR 1.7 Modified it. Module.

18/12/03 Module Height added PSR 1.8

27/05/04 AWG term added. PSR 1.9

13/07/04 Input and output stages ADC/DAC schematics

PSR 2.0 added. ADC input voltage corrected.

02/06/05 Figure 13 corrected PSR 2.1

Version 2.0 Page 3 of 46 SMT370v2/v3 User Manual

Table of Contents

Revision History.......................................................................................................... 2

Table of Contents ....................................................................................................... 3

Contacting Sundance. ................................................................................................ 5

Notes. ......................................................................................................................... 5

Precautions................................................................................................................. 5

Outline description...................................................................................................... 6

Block Diagram - Architecture. ..................................................................................... 7

Architecture Description. ............................................................................................ 8

Virtex FPGA. ........................................................................................................... 9

What the FPGA does........................................................................................... 9

Ressource occupied.......................................................................................... 10

Memory................................................................................................................. 10

ADCs and DAC. .................................................................................................... 11

Clock management. .............................................................................................. 11

Sundance High-speed Bus - SHB......................................................................... 11

SHBA – ADCs. .................................................................................................. 11

SHBB – DAC. .................................................................................................... 12

Communication Ports (ComPorts). ....................................................................... 12

External triggering................................................................................................. 12

LEDs. .................................................................................................................... 12

TTL I/Os................................................................................................................ 13

Sundance Standards. ............................................................................................... 13

Communication Ports (ComPorts). ....................................................................... 13

Sundance High-speed Bus - SHB......................................................................... 14

Communication links implemented on the SMT370. ............................................. 15

For more details about ComPorts and SHB. ......................................................... 15

DAC Performance. ................................................................................................... 19

SHB pinout. .............................................................................................................. 21

FPGA Pinout............................................................................................................. 22

At power-up and on reset. ........................................................................................ 26

Connector position.................................................................................................... 27

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Operating conditions................................................................................................. 28

Safety.................................................................................................................... 28

EMC...................................................................................................................... 28

General Requirements.......................................................................................... 28

Power Consumption.............................................................................................. 28

Temperature ......................................................................................................... 28

Register settings....................................................................................................... 30

datasheet for more details). ...... 30

datasheet for more details)......... 31

datasheet for more details)......... 32

datasheet for more details)......... 33

datasheet for more details)......... 34

SMT370 package. .................................................................................................... 46

SMT370 Dimensions. ............................................................................................... 46

Figure 1 - Block Diagram............................................................................................ 7

Figure 2 - FPGA utilisation........................................................................................ 10

Figure 3 - ComPort interface data path. ................................................................... 14

Figure 4 - SHB interface structure. ........................................................................... 15

Figure 5 - ADC Performance. ................................................................................... 16

Figure 6 - ADC input stage - AC-coupled. ................................................................ 17

Figure 7 - ADC input stage - DC-coupled. ................................................................ 17

Figure 8 - FFT ADC Channel - On-board clock. ....................................................... 18

Figure 9 - DAC Performance. ................................................................................... 19

Figure 10 - DAC output stage. .................................................................................. 20

Figure 11 - FFT DAC Channel.................................................................................. 20

Figure 12 - SHB Pinout............................................................................................. 21

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Figure 13 - Connector Location. ............................................................................... 27

Figure 14 - Clock Routing......................................................................................... 36

Figure 15 - SHBB data path...................................................................................... 41

Contacting Sundance.

You can contact Sundance for additional information by sending email to

support@sundance.com

Notes.

- SMT370 denotes in this document SMT370v2 or SMT370v3. The board in available in two options: AC or DC-coupled inputs (ADC). It is to be specified when placing an ordering.

- SHB stands for Sundance High-speed Bus.

- ComPort denotes an 8-bit communication port following the TI C4x standards.

Precautions.

In order to guarantee that the SMT370 functions correctly and to protect the module from damage, the following precautions should be taken:

- The SMT370 is a static sensitive product and should be handled accordingly.

Always place the module in a static protective bag during storage and transition.

- When operated in a closed or warm environment make sure that the heat generated by the system is extracted e.g. by the use of a fan extractor or an air blower.

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Outline description.

The SMT370 is a dual high-speed ADC/DAC module offering the following features:

- Two 14-bit ADCs (AD6645-105

- Dual 16-bit TxDAC (AD9777

) sampling at up to 105MHz,

) sampling at up to 400MHz (interpolation),

- 32Mbits (1Mx4bytes) of NtSRAM working at up to 160 MHz for pattern generator or AWG mode,

- Single width module,

- Two Sundance High-speed Bus (SHB) connectors,

- Two 20 MegaByte/s communication ports,

- Low-jitter on-board system clock,

- Xilinx Virtex-II FPGA,

- 50-Ohm terminated analogue inputs and outputs, external triggers and clocks via MMBX (Huber and Suhner) connectors,

- User defined pins for external connections,

- Compatible with a wide range of Sundance SHB modules,

- TIM standard compatible,

- Default FPGA firmware implementing all the functions described in this

documentation.

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Block Diagram - Architecture.

The following diagram shows the architecture of the SMT370.

3 Power

supply

LEDs

‘FPGA configured’

On-board Oscillator

4 LVTTL I/O pins

FPGA PROM

6-pin JTAG

header

2 Sundance High-speed

Bus connector: 2 x 60 bits

One bank of 1Mx32 bits of

NtSRAM - 166 MHz

LED

50 MHz

4 LEDs or

XC18V04

JTAG chain

68 I/O pins; 32-bit data

120 I/O pins

J2 Bottom Primary TIM

Connector

Board Reset

Xilinx FPGA

Virtex-II, FG456

XC2V1000-6

324 I/O Pins

1.5V Core

3.3V I/O

24 I/O pins

2x Comm-Port/SDL

J1 Top Primary TIM

Connector

2x CommPorts/SDLs 0 & 3

Trig

30 I/O pins; 28-bit data; ctl

Clock feedback

Clock

parameters

44 I/O pins; 16-bit data; ctl

Clock feedback

2xClock

synthesizers

Clock selection

AC or DC coupling*

2xAD6645 ADCs

14-bit @ 105MSPS

52-pin LQFP

Multiplexer

1x AD9777 DAC

16-bit @ 400MSPS

80-pin TQFP

transformer

Clock

AC or DC coupling*

transformer

#4#3

* Option to the board

Filter

Clk

Figure 1 - Block Diagram.

Connections to the outside world are greyed out.

Main parts of the board are described in the next part of this document.

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Architecture Description.

The module consists of a Xilinx Virtex-II FPGA, two Analog Devices (14-bit monolithic sampling Analog-to-Digital converters) AD6645 and one Analog Devices AD9777 (Dual TxDAC+ Digital-to-Analog converter).

The AD6645

is a 14-bit monolithic sampling analog-to-digital converter. The chip provides CMOS-compatible digital outputs. It is the Analog Devices’ fourth generation of wideband ADCs. The AD6645 maintains outstanding AC performance up to input frequencies of 200 MHz, which makes it suitable for multi-carrier 3G applications. The AD6645 is able to sample from 30 up to 105 MHz. Nevertheless, it is possible to reduce that rate by performing decimation on the data flow.

The AD9777

dual interpolating (2x/4x/8x) DAC consists of two data channels that can be operated independently or coupled to form a complex modulator in an image reject transmit architecture. This programmable converter has a resolution of 16 bits. It features a Serial Port Interface (SPI) for programming. The chip features a selectable 2x/4x/8x interpolation filter, an Fs/2, Fs/4 or Fs/8 digital quadrature modulation with image rejection, a direct IF mode, a programmable channel gain and offset control, a programmable internal clock divider, a straight binary to two’s complement data interface and a single port or dual data interface.

Parallel busses connect both ADCs and the DAC to the FPGA, which is responsible for transferring samples from/to the converters. An on-board frequency synthesizer generates differential encode lines (sampling clocks) to feed the converters; a connector for external clocks is also available. Each input analogue signal to the ADCs goes through an extra stage, which can be an opamp (DC coupling) or an RF transformer (AC coupling). The option must be defined when ordering the SMT370. When it comes to the DAC, its outputs can only be set as AC coupled (output RF transformer). Both ADCs can be coupled together. i.e. they have the same sampling clock or have two separate clocks, one external and one coming from the on-board clock synthesizer.

The Xilinx FPGA Virtex-II is configured via a 6-pin JTAG header or from the on-board Xilinx PROM (XC18V04

) at startup. The default configuration mode is from a PROM, which contains the standard modes of operation (as described in this document). An on-board red LED (DONE LED) indicates that the FPGA is configured. Both devices, FPGA and PROM are in the same JTAG chain.

The SMT370 is also populated with some NtSRAM memory

. It is 32-bit wide and to store two 16-bit samples at the same address at up 160 MHz. Its size is 1 Megawords of 32-bits. The FPGA is implemented with an NtSRAM interface to write/read to/from it. Memory accesses are made via a control register. A ‘pattern generator’ function is available to store a pattern (or periodic frame) into the memory, read back continuously and send samples out to the DAC. This configuration allows to board to work as a periodic generator in stand-alone mode. In this mode, the SMT370 works as a loadable AWG (Arbitrary Waveform Generator).

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Two Communication links (ComPorts) following the Texas Instrument C4x standard are connected to the FPGA and will be used to receive control words or for other purpose. They can achieve transfers at up to 20Mbytes/s.

Two full SHB connectors (60-pin) are accessible from the FPGA. The first connector (SHBA – J3) is set as output only and is dedicated for sending out samples coming from the ADC. The second connector (SHBB – J4) is set as input only to receive samples, which are redirected to the DAC. Please refer to the SHB specifications

for more details about ways connectors can be configured. Both SHBs can work either as two 16-bit interfaces or a single 32-bit interface. In the case of a 32-bit interface, both ADCs must receive the same sampling clock signal. The SMT370 is therefore fully compatible with Sundance 16-bit and 32-bit processor modules without setting any register.

Four LEDs are driven by the FPGA. Four LVTTL I/Os for general purpose are also available. No clamping diodes to 3.3 Volts and ground are available on the board to avoid damaging pads on the FPGA. It is therefore to the customer to make sure the signals connected to these I/Os are LVTTL and don’t show any overshoots.

External Clock, trigger and analogue input signals are all single-ended. External connections to the board are all 50-Ohm terminated. External triggers have clamping diodes to 3.3V and to Ground to avoid damaging the FPGA they are connected to.

A global reset signal is mapped to the FPGA from the top TIM connector to reset the FPGA and reload the FPGA

Virtex FPGA.

What the FPGA does.

The SMT370 is populated with a Xilinx Virtex FPGA (XC2V1000-6FG456

). This device controls major functions on the module, like ComPorts and SHB communications, data flows to and from the converters, memory and clock management.

This FPGA needs being configured after power-up and after a module reset. This operation is possible thanks to the on-board Xilinx PROM. This operation can be done automatically when jumper J8 (Figure 13 - Connector Location.) is fitted. If it is not fitted, no configuration is loaded into the FPGA and allows therefore the user to program the FPGA via JTAG with no possible conflict.

Ten control registers are implemented into this FPGA to set up converters, their data format, clock synthesizers, ComPort, SHB and memory transfers. Some more details are given in the next parts of this document. Registers can be individually programmed. They can also be read back but all at the same time.

The FPGA is serially programmed using the dedicated pins. The PROM is originally programmed with a default bit stream, which implements all features mentioned in this document.

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Ressource occupied.

The default firmware, as it comes with the board, uses FPGA resources, such as Ram Blocks, Flip-flop, Slices, I/O pads. The following table gathers all of them:

Number of

External IOBs

Number of

RAMB16s

Number of

SLICEs

Number of

BUFGMUXs

Number of

DCMs

Number of

External

DIFFMs

Number of

External

DIFFSs

Number

used

Out of

247 324 76%

9 40 22%

1059 5120 20%

6 16 37%

2 8 25%

1 162 1%

Figure 2 - FPGA utilisation.

Percentage

of utilisation

Most of the resources are not used by the default firmware, which allows the user to implement some extra processing such as for example digital filters to add some processing gain to the chain.

Memory.

The SMT370 is populated with 32Mbits of ZBTRAM (32 bits x 1Meg). It is connected to the FPGA, which controls read and write operations. The default FPGA bit stream implements a pattern generator which consists in storing a pattern into the memory, reading it back continuously and sending data out to the DAC. This generator is controlled via bits in the control registers. It can be loaded, started and stopped by setting bits. For more details, see further in the documentation, the part dealing with control registers.

This pattern generator feature is also called Arbitrary Waveform Generator (AWG). Please, note that to change of waveform, the memory has to be reloaded and the pattern generator to be re-started. This is due to the default firmware starting reading data from address 0, i.e. the start address is not a parameter, unlike the size is.

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ADCs and DAC.

The SMT370 is populated with two AD6645s

(2 channels) and one AD9777 (dual channel). For more details about these converters (inner characteristics), please refer to the manufacturer (Analog Devices) datasheets.

Data and control lines of the converters are all connected to the FPGA.

Clock management.

The SMT370 has two identical on-board low-jitter clock synthesizers (ICS8430

), one

for the ADCs and one for the DAC. Both have a Serial Port Interface. The FPGA is responsible for setting them to the correct values loaded into a control register. A wide range of frequencies can be set this way. The SPIs are write-only, i.e. they can’t be read back directly from the chip.

Clock multiplexers are also available on the board to route the appropriate clock signal (from external or on-board source) to the converters. It is usual to have both ADCs fed with the same sampling clock but it is possible to have an ADC receiving the external clock and the second one receiving the on-board clock. In this particular case, two 16-bit interfaces are necessary to transfer samples to an external TIM. The DAC is fed either with an on-board/DAC or external clock coming from connector J14. The clock selection is made via the control register.

Sundance High-speed Bus - SHB.

The SMT370 provides 2 full SHB (Sundance High-speed Bus) connectors, labelled SHBA (J3) and SHBB (J4) – see Figure 13 - Connector Location.)

SHBA is set as transmitter only to transfer data coming from the Analogue-to-Digital Converters to an external SHB module, for instance SMT365, SMT365E or SMT374. SHBB is set as a receiver only and is dedicated to receive data for the Digital-toAnalogue converter. Transfers at up to 100 MHz are supported on these two SHB connectors.

SHBA – ADCs.

The FPGA routes the data lines coming from the ADCs to SHBA. Data lines go through 7 latch stages inside the FPGA, which means that it takes 7 sampling clock cycles for a sample to go from the ADC to SHBA. The board offers to possibility to output data in either two’s complement or binary format. It is also possible to output a 16-bit counter on each SHB half for system testing purpose – It then becomes easier to detect any missing data. ADCA is mapped onto the lowest part of SHBA and ADCB onto the highest.

As the SMT370 is populated with two ADCs, two data stream are theoretically available on SHBA. Each of them can be synchronised to either an external sampling clock or an on-board clock. In the FPGA, each data stream goes through a Decimator, which value (0 to 31) can be set via control register. Both decimators are independent. If both decimators are set with the same values and if the sampling clocks (for Channel A and Channel B) are the same, i.e. both ADCs are using either the external or the on-board clock, both data streams are synchronised with each

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other and therefore the two 16-bit data streams can be considered as a single 32-bit data stream.

It is possible to control (start/stop) the data flow by the way of an external trigger, for which the active level (high or low) can be set in a control register. It is recommended to have external trigger signal synchronised to the sampling clock. This external trigger also goes thought 7 latch stages.

SHBB – DAC.

Data received on SHBB are samples routed to the DAC. Data from both SHBB channels go through a first row of latched, then stored into a FIFO, read out and finally go through two rows of latches. It takes at least 4 DAC sampling clock cycles to go through the FPGA. As both channels of the DAC are not necessarily synchronised, the two FIFOs are read out at the same time as soon as there is a least one data in each FIFO – it is the case when using two independent 16-bit interfaces. To avoid synchronisation problems, SHBB can be used as a single 32-bit interface. Simply drive both sets of control register with the same signals. DACChannel A is mapped onto the lowest part of SHBB and DAC-Channel B onto the highest.

Communication Ports (ComPorts).

The SMT370 provides 2 physical ComPorts: 0 and 3. The default bit stream provided implements ComPort 3 (Input at reset) to load control registers. A physical connection to a ComPort 0, 1 or 2 (Output at reset) is therefore necessary, to an SMT365 for instance. Please report to the part dealing with ComPorts (Communication Ports (ComPorts).) in this document for more details.

External triggering.

Two external trigger connectors (J15 and J16 – see Figure 13 - Connector Location.) are available on the board to start or stop converters from an external source. The selection is made via a control register, where channel selection can also be set.

Triggering consists in enabling or disabling the converters (ADCs and/or DAC). This is available and accurate as long as the triggering signals are synchronised on the sampling clock. Trigger signals can be set as active high or low in via the control register.

Each trigger input is clamped to 3.3 and Ground to avoid damaging the FPGA I/Os. This is achieved by using single diodes (BAV99

). These diodes can support as maximum, 200mA of forward current and 70 Volts of reverse voltage. It is to the customer to consider this when building a system using an SMT370.

LEDs.

Seven LEDs (Figure 13 - Connector Location.) are available on the board. Four (denoted 1, 2, 3 and 4 on the PCB – top left) of them, green, are driven by the FPGA. In the default bitstream, they indicate what follows:

Version 2.0 Page 13 of 46 SMT370v2/v3 User Manual

1 -> Flashing under the ADC sampling clock (it can be useful to check that the LED is flashing when using an external sampling clock signal),

2 -> Flashing under the DAC sampling clock,

3 -> Direct To DAC mode selected when ON,

4 -> ON when a data is being read out of the DAC FIFO.

Two green LEDs, located at the bottom left and right of the board indicate the status of the power supplies. Both should be on when the board is under power.

A red LED located on the top right of the board indicated when the FPGA is not programme. In normal operation, i.e. J8 fitted (Figure 13 - Connector Location.), it flashes once at power-up and after resetting the module.

Just after a reset (TIM or FPGA Global Reset), the LEDs display the Firmware version. This is available from the Version 4 of the Firmware. For earlier version, the LEDs are connected to un-driven signals:

LED1=ON, LED2=OFF, LED3=ON and LED4-OFF => Version 2.5 of the firmware

LED1=OFF, LED2=ON, LED3=ON and LED4-OFF => Version 3.6 of the firmware

TTL I/Os.

Four TTL I/Os (J6 – see Figure 13 - Connector Location.) are connected directly to the FPGA. They support LVTTL signals. It is recommended to make sure the lines connected to these pins are LVTTL compatible in order not to damage the FPGA pads, as lines are not clamped.

Sundance Standards.

Communication Ports (ComPorts).

According to the Sundance module you can get up to six 8-bit, data-parallel, interprocessor links that follow Texas Instruments’ TMS320C4x Communication Port standard. Additional information on the standard is available in the TMS320C4x User’s Guide chapter 12: Communication ports and the Texas Instrument Module

Specification.

The standard gives a TIM six links numbered from 0 to 5. Each link can be a transmitter or a receiver, and will switch automatically between these states depending on the way you use it. Writing to a receiver or reading from a transmitter will cause a hardware negotiation (token exchange) that will reverse the state of both ends of the link.

Following a processor reset, the first three links (0, 1, and 2) initialise as transmitters and the remainder (3, 4, and 5) initialise as receivers. When you wire TIMs together

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you must make sure that you only ever connect links initialising as transmitters to links initialising as receivers; never connect two transmitters or two receivers. For example, connecting link 0 of one TIM to link 4 of another is safe; connecting link 0 of one TIM to link 2 of another could damage the hardware.

Always connect ComPort 0, 1 or 2 to ComPort 3, 4 or 5.

On most carrier board the physical connection between comm-ports is made with FMS cables (Ref. SMT3xx-FMS). You must be careful when connecting the cables the make sure that one end is inserted in the opposite sense to the other. One end must have the blue backing facing out and the other must have the silver backing facing out. The SMT310Q (SMT320) motherboard communicates with the host PC using ComPort 3 of the site 1 TIM. You should not make any other connections to this ComPort.

ComPorts (Communication ports) links follow Texas Instrument C4x standard. They are 8-bit parallel inter-processor ports of the ‘C4x processors.

The ComPorts drive at 3.3v signal levels.

The FPGA can implement up to two FIFO buffered ComPort interfaces fully compliant with the TIM standard. They are guaranteed for a transfer rate of 20MB/s.

The FIFOs are useful to maintain a maximum bandwidth and to enable parallel transfers.

Therefore, as an example, each ComPort can be associated with two 15x32-bit unidirectional FIFOs implemented into the FPGA; one for input and one for output. An additional one-word buffer makes them appear as 16x32-bit FIFOs.

DATA

D[0..31]

Figure 3 - ComPort interface data path.

FIFO

16 x 32 x 2

Control Logic and Status

D[0..7]

STRB RDY REQ ACK

Port x

Sundance High-speed Bus - SHB.

Both SHB

buses are identical and 60-bit wide.

SHBs are parallel communication links for synchronous transmissions. Each SHB can be divided into two independent 8-bit buses. Each 8-bit bus includes a clock and

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